Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	26595236	5486	0	0
EscTimeoutStoppedByClReset_A	26594678	3873299	0	0
EscTimeoutTriggersReset_A	4987057	307	0	0
RomAllowActiveState_A	26594678	63803	0	0
RomAllowCheckGoodState_A	26594678	63854	0	0
RomBlockActiveState_A	26594678	30006	0	0
RomBlockCheckGoodState_A	26594678	413966	0	0
RomIntgChkDisFalse_A	26594678	25898067	0	0
RomIntgChkDisTrue_A	26594678	150067	0	0
RstreqChkEsctimeout_A	26594678	4897	0	0
RstreqChkFsmterm_A	26594678	120	0	0
RstreqChkGlbesc_A	26594678	4897	0	0
RstreqChkMainpd_A	26594678	1075318	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26595236	5486	0	0
T11	15619	129	0	0
T12	15089	79	0	0
T14	1009	0	0	0
T24	2599	0	0	0
T25	6559	0	0	0
T28	0	4	0	0
T36	2841	0	0	0
T37	1786	0	0	0
T40	2523	0	0	0
T41	2500	0	0	0
T53	7188	0	0	0
T155	0	117	0	0
T156	0	121	0	0
T157	0	174	0	0
T158	0	6	0	0
T159	0	5	0	0
T160	0	8	0	0
T161	0	72	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26594678	3873299	0	0
T1	3238	49	0	0
T2	59034	9472	0	0
T3	3994	75	0	0
T4	2923	3	0	0
T5	2154	60	0	0
T6	5655	238	0	0
T7	2598	95	0	0
T8	805	25	0	0
T9	7660	588	0	0
T10	1691	54	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4987057	307	0	0
T8	264	5	0	0
T9	2570	0	0	0
T10	322	0	0	0
T11	196	2	0	0
T12	0	3	0	0
T13	13656	0	0	0
T23	12286	0	0	0
T24	393	0	0	0
T25	663	0	0	0
T28	0	4	0	0
T53	1507	0	0	0
T80	375	0	0	0
T155	0	2	0	0
T156	0	3	0	0
T157	0	2	0	0
T158	0	2	0	0
T159	0	4	0	0
T162	0	2	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26594678	63803	0	0
T1	3238	5	0	0
T2	59034	202	0	0
T3	3994	6	0	0
T4	2923	16	0	0
T5	2154	5	0	0
T6	5655	9	0	0
T7	2598	5	0	0
T8	805	3	0	0
T9	7660	27	0	0
T10	1691	5	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26594678	63854	0	0
T1	3238	5	0	0
T2	59034	202	0	0
T3	3994	6	0	0
T4	2923	16	0	0
T5	2154	5	0	0
T6	5655	9	0	0
T7	2598	5	0	0
T8	805	3	0	0
T9	7660	27	0	0
T10	1691	5	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26594678	30006	0	0
T6	5655	1221	0	0
T7	2598	0	0	0
T8	805	0	0	0
T9	7660	0	0	0
T10	1691	0	0	0
T11	15618	0	0	0
T13	62831	0	0	0
T23	17936	0	0	0
T24	0	696	0	0
T25	6558	0	0	0
T36	0	680	0	0
T80	2063	0	0	0
T163	0	377	0	0
T164	0	31	0	0
T165	0	7	0	0
T166	0	266	0	0
T167	0	2	0	0
T168	0	32	0	0
T169	0	19	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26594678	413966	0	0
T2	59034	871	0	0
T3	3994	0	0	0
T4	2923	0	0	0
T5	2154	0	0	0
T6	5655	1100	0	0
T7	2598	0	0	0
T8	805	0	0	0
T9	7660	321	0	0
T10	1691	0	0	0
T13	62831	1514	0	0
T20	0	2662	0	0
T23	0	825	0	0
T24	0	371	0	0
T36	0	301	0	0
T137	0	3971	0	0
T138	0	1351	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26594678	25898067	0	0
T1	3238	2851	0	0
T2	59034	57490	0	0
T3	3994	3548	0	0
T4	2923	2830	0	0
T5	2154	1793	0	0
T6	5655	5072	0	0
T7	2598	2220	0	0
T8	805	672	0	0
T9	7660	7499	0	0
T10	1691	1304	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26594678	150067	0	0
T6	5655	409	0	0
T7	2598	0	0	0
T8	805	0	0	0
T9	7660	0	0	0
T10	1691	0	0	0
T11	15618	0	0	0
T13	62831	0	0	0
T23	17936	151	0	0
T24	0	104	0	0
T25	6558	0	0	0
T80	2063	0	0	0
T163	0	159	0	0
T165	0	207	0	0
T166	0	1018	0	0
T167	0	285	0	0
T170	0	3323	0	0
T171	0	977	0	0
T172	0	559	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26594678	4897	0	0
T2	59034	28	0	0
T3	3994	0	0	0
T4	2923	0	0	0
T5	2154	0	0	0
T6	5655	1	0	0
T7	2598	0	0	0
T8	805	1	0	0
T9	7660	0	0	0
T10	1691	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	62831	16	0	0
T24	0	4	0	0
T25	0	4	0	0
T36	0	3	0	0
T40	0	2	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26594678	120	0	0
T17	8550	20	0	0
T18	0	20	0	0
T19	0	40	0	0
T20	325452	0	0	0
T26	0	20	0	0
T27	0	20	0	0
T28	792	0	0	0
T29	3132	0	0	0
T30	7536	0	0	0
T31	982	0	0	0
T32	942	0	0	0
T33	1442	0	0	0
T34	1456	0	0	0
T35	1637	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26594678	4897	0	0
T2	59034	28	0	0
T3	3994	0	0	0
T4	2923	0	0	0
T5	2154	0	0	0
T6	5655	1	0	0
T7	2598	0	0	0
T8	805	1	0	0
T9	7660	0	0	0
T10	1691	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	62831	16	0	0
T24	0	4	0	0
T25	0	4	0	0
T36	0	3	0	0
T40	0	2	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26594678	1075318	0	0
T2	59034	4766	0	0
T3	3994	22	0	0
T4	2923	0	0	0
T5	2154	0	0	0
T6	5655	980	0	0
T7	2598	0	0	0
T8	805	0	0	0
T9	7660	871	0	0
T10	1691	0	0	0
T13	62831	3153	0	0
T23	0	1849	0	0
T25	0	100	0	0
T36	0	371	0	0
T37	0	137	0	0
T173	0	5	0	0