Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	40471	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

29250

1

T2

24

T4

5

T5

18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	35501	1			T2	14		T3	1		T4	4
values[0x0]	16784	1			T2	36		T4	6		T5	14
values[0x1]	17436	1			T1	1		T2	30		T4	16

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	32489	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

37232

1

T2

31

T4

6

T5

23

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	352	1			T14	2		T15	1		T17	2
valid_sources[0x01]	241	1			T2	3		T53	12		T33	2
valid_sources[0x02]	216	1			T12	1		T13	2		T28	4
valid_sources[0x03]	214	1			T2	1		T13	1		T33	2
valid_sources[0x04]	223	1			T36	2		T148	1		T17	5
valid_sources[0x05]	476	1			T33	3		T39	1		T137	1
valid_sources[0x06]	257	1			T7	1		T42	1		T14	2
valid_sources[0x07]	247	1			T28	2		T14	3		T15	1
valid_sources[0x08]	242	1			T7	3		T33	1		T83	2
valid_sources[0x09]	309	1			T33	2		T14	1		T17	2
valid_sources[0x0a]	276	1			T2	2		T13	4		T95	2
valid_sources[0x0b]	446	1			T2	1		T5	51		T82	1
valid_sources[0x0c]	218	1			T2	1		T33	2		T34	1
valid_sources[0x0d]	291	1			T7	1		T13	2		T84	70
valid_sources[0x0e]	223	1			T82	2		T34	3		T65	1
valid_sources[0x0f]	200	1			T12	2		T14	2		T15	1
valid_sources[0x10]	315	1			T2	1		T7	2		T33	4
valid_sources[0x11]	235	1			T33	1		T65	1		T14	1
valid_sources[0x12]	184	1			T2	1		T7	2		T9	1
valid_sources[0x13]	208	1			T42	1		T33	1		T126	2
valid_sources[0x14]	232	1			T33	3		T34	1		T148	3
valid_sources[0x15]	191	1			T2	1		T7	2		T85	6
valid_sources[0x16]	272	1			T2	2		T13	1		T44	1
valid_sources[0x17]	256	1			T6	3		T82	1		T140	4
valid_sources[0x18]	252	1			T33	3		T148	1		T15	1
valid_sources[0x19]	236	1			T2	3		T33	1		T34	2
valid_sources[0x1a]	237	1			T34	1		T126	5		T204	1
valid_sources[0x1b]	418	1			T6	7		T41	26		T85	17
valid_sources[0x1c]	241	1			T7	1		T140	1		T83	1
valid_sources[0x1d]	201	1			T7	1		T93	4		T95	1
valid_sources[0x1e]	289	1			T6	1		T33	2		T34	1
valid_sources[0x1f]	261	1			T82	2		T33	3		T14	1
valid_sources[0x20]	394	1			T2	3		T28	1		T33	1
valid_sources[0x21]	253	1			T82	4		T33	4		T14	4
valid_sources[0x22]	209	1			T2	2		T12	1		T33	1
valid_sources[0x23]	213	1			T6	1		T32	1		T33	1
valid_sources[0x24]	194	1			T93	2		T204	1		T127	2
valid_sources[0x25]	215	1			T6	1		T53	4		T14	2
valid_sources[0x26]	260	1			T2	1		T6	3		T34	1
valid_sources[0x27]	258	1			T2	1		T13	1		T33	1
valid_sources[0x28]	276	1			T15	1		T17	2		T126	2
valid_sources[0x29]	276	1			T6	1		T82	1		T14	2
valid_sources[0x2a]	229	1			T2	1		T6	2		T12	4
valid_sources[0x2b]	206	1			T33	3		T15	2		T204	1
valid_sources[0x2c]	274	1			T28	2		T33	2		T148	1
valid_sources[0x2d]	277	1			T2	2		T12	7		T148	1
valid_sources[0x2e]	226	1			T6	1		T13	1		T39	1
valid_sources[0x2f]	203	1			T2	1		T14	5		T93	1
valid_sources[0x30]	159	1			T7	1		T13	1		T33	1
valid_sources[0x31]	208	1			T28	1		T33	2		T148	1
valid_sources[0x32]	234	1			T83	1		T65	1		T14	1
valid_sources[0x33]	205	1			T12	3		T41	5		T33	3
valid_sources[0x34]	247	1			T2	1		T28	3		T33	2
valid_sources[0x35]	502	1			T34	1		T83	1		T148	1
valid_sources[0x36]	209	1			T2	1		T13	1		T83	1
valid_sources[0x37]	173	1			T33	2		T14	1		T93	2
valid_sources[0x38]	214	1			T33	1		T83	1		T148	1
valid_sources[0x39]	267	1			T14	1		T17	2		T126	1
valid_sources[0x3a]	244	1			T2	1		T33	3		T83	1
valid_sources[0x3b]	358	1			T6	5		T33	2		T148	1
valid_sources[0x3c]	213	1			T7	2		T13	2		T33	1
valid_sources[0x3d]	204	1			T2	1		T39	2		T140	1
valid_sources[0x3e]	189	1			T33	1		T83	2		T14	1
valid_sources[0x3f]	258	1			T205	1		T15	3		T93	1
valid_sources[0x40]	314	1			T28	3		T33	4		T14	3
valid_sources[0x41]	241	1			T2	2		T82	1		T139	1
valid_sources[0x42]	246	1			T13	1		T33	2		T83	2
valid_sources[0x43]	188	1			T6	2		T7	2		T34	1
valid_sources[0x44]	302	1			T6	1		T7	1		T12	4
valid_sources[0x45]	181	1			T6	1		T42	1		T20	2
valid_sources[0x46]	365	1			T86	8		T14	2		T93	2
valid_sources[0x47]	293	1			T6	1		T18	1		T13	1
valid_sources[0x48]	232	1			T2	3		T39	1		T148	1
valid_sources[0x49]	243	1			T6	3		T7	2		T28	2
valid_sources[0x4a]	379	1			T33	3		T34	1		T83	1
valid_sources[0x4b]	382	1			T7	1		T13	1		T65	1
valid_sources[0x4c]	300	1			T43	1		T33	2		T39	1
valid_sources[0x4d]	261	1			T2	2		T7	2		T33	1
valid_sources[0x4e]	223	1			T2	1		T6	1		T13	1
valid_sources[0x4f]	203	1			T2	1		T7	3		T33	1
valid_sources[0x50]	279	1			T2	1		T8	6		T41	1
valid_sources[0x51]	252	1			T6	1		T13	1		T33	1
valid_sources[0x52]	285	1			T33	6		T126	1		T206	3
valid_sources[0x53]	165	1			T28	3		T33	5		T34	1
valid_sources[0x54]	391	1			T2	1		T4	26		T6	2
valid_sources[0x55]	228	1			T6	2		T13	2		T33	2
valid_sources[0x56]	229	1			T13	2		T33	3		T83	1
valid_sources[0x57]	509	1			T82	3		T33	5		T14	1
valid_sources[0x58]	357	1			T7	1		T13	2		T33	5
valid_sources[0x59]	265	1			T31	20		T34	1		T14	3
valid_sources[0x5a]	290	1			T42	2		T33	3		T39	2
valid_sources[0x5b]	263	1			T83	1		T148	2		T15	2
valid_sources[0x5c]	567	1			T7	2		T19	1		T33	2
valid_sources[0x5d]	217	1			T7	1		T13	1		T28	1
valid_sources[0x5e]	436	1			T20	1		T33	1		T14	2
valid_sources[0x5f]	239	1			T28	2		T33	1		T148	3
valid_sources[0x60]	168	1			T7	1		T33	2		T14	3
valid_sources[0x61]	235	1			T83	1		T14	1		T93	4
valid_sources[0x62]	217	1			T20	2		T33	1		T34	1
valid_sources[0x63]	299	1			T2	3		T7	1		T86	3
valid_sources[0x64]	256	1			T33	2		T15	1		T93	7
valid_sources[0x65]	334	1			T2	2		T82	1		T28	1
valid_sources[0x66]	218	1			T6	2		T7	1		T14	4
valid_sources[0x67]	232	1			T13	1		T14	1		T17	1
valid_sources[0x68]	282	1			T7	2		T34	3		T15	1
valid_sources[0x69]	204	1			T16	7		T33	1		T15	1
valid_sources[0x6a]	271	1			T33	3		T15	1		T93	5
valid_sources[0x6b]	233	1			T7	1		T33	2		T14	1
valid_sources[0x6c]	201	1			T2	1		T42	1		T65	1
valid_sources[0x6d]	242	1			T15	1		T207	1		T204	2
valid_sources[0x6e]	322	1			T7	1		T53	2		T83	1
valid_sources[0x6f]	206	1			T6	1		T13	3		T42	1
valid_sources[0x70]	222	1			T2	1		T6	1		T82	3
valid_sources[0x71]	277	1			T6	1		T12	2		T33	2
valid_sources[0x72]	193	1			T2	1		T12	5		T39	1
valid_sources[0x73]	191	1			T13	1		T33	1		T140	4
valid_sources[0x74]	330	1			T8	10		T83	1		T15	1
valid_sources[0x75]	234	1			T2	1		T42	1		T140	1
valid_sources[0x76]	477	1			T2	2		T13	2		T33	4
valid_sources[0x77]	203	1			T8	12		T33	1		T148	1
valid_sources[0x78]	235	1			T82	1		T208	1		T14	1
valid_sources[0x79]	297	1			T12	2		T33	1		T148	2
valid_sources[0x7a]	212	1			T7	1		T20	1		T34	2
valid_sources[0x7b]	253	1			T2	1		T41	20		T34	1
valid_sources[0x7c]	240	1			T7	1		T129	1		T42	1
valid_sources[0x7d]	187	1			T63	1		T64	1		T33	1
valid_sources[0x7e]	284	1			T12	1		T13	7		T34	1
valid_sources[0x7f]	420	1			T7	1		T126	1		T141	1
valid_sources[0x80]	239	1			T38	1		T140	2		T65	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

14563

1

T2

7

T4

3

T5

4

values[0x0]

all_enables

biggest_size

8384

1

T2

14

T4

2

T5

8

values[0x1]

all_enables

biggest_size

6303

1

T2

3

T5

6

T6

8