Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2797208	13285	0	0
intr_enable_rd_A	2797208	2583	0	0
reset_en_rd_A	2797208	1207	0	0
reset_en_regwen_rd_A	2797208	1057	0	0
wake_info_capture_dis_rd_A	2797208	1105	0	0
wakeup_en_rd_A	2797208	1686	0	0
wakeup_en_regwen_rd_A	2797208	977	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2797208	13285	0	0
T23	7651	5	0	0
T24	3098	574	0	0
T25	3703	159	0	0
T57	2973	524	0	0
T58	11899	10	0	0
T59	14038	10	0	0
T60	2281	153	0	0
T67	4649	1168	0	0
T75	3141	13	0	0
T79	4869	5	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2797208	2583	0	0
T15	0	21	0	0
T17	0	48	0	0
T27	2117	0	0	0
T28	5173	0	0	0
T42	2020	0	0	0
T43	15755	0	0	0
T53	1586	0	0	0
T54	0	70	0	0
T55	0	31	0	0
T63	15152	0	0	0
T82	3638	6	0	0
T83	0	13	0	0
T84	2146	0	0	0
T85	2402	3	0	0
T126	0	64	0	0
T127	0	5	0	0
T128	0	8	0	0
T129	3541	0	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2797208	1207	0	0
T25	3703	14	0	0
T80	5318	27	0	0
T113	30541	449	0	0
T130	7905	33	0	0
T131	1710	17	0	0
T132	1200	3	0	0
T133	1852	11	0	0
T134	10831	75	0	0
T135	1968	33	0	0
T136	1400	10	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2797208	1057	0	0
T25	3703	1	0	0
T80	5318	32	0	0
T113	30541	468	0	0
T130	7905	13	0	0
T131	1710	7	0	0
T132	1200	10	0	0
T133	1852	2	0	0
T134	10831	36	0	0
T135	1968	19	0	0
T136	1400	5	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2797208	1105	0	0
T25	3703	4	0	0
T80	5318	28	0	0
T113	30541	482	0	0
T130	7905	28	0	0
T131	1710	13	0	0
T132	1200	1	0	0
T133	1852	10	0	0
T134	10831	34	0	0
T135	1968	58	0	0
T136	1400	8	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2797208	1686	0	0
T25	3703	9	0	0
T80	5318	50	0	0
T113	30541	449	0	0
T130	7905	59	0	0
T131	1710	48	0	0
T132	1200	11	0	0
T133	1852	22	0	0
T134	10831	111	0	0
T135	1968	13	0	0
T136	1400	8	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2797208	977	0	0
T25	3703	4	0	0
T80	5318	13	0	0
T113	30541	478	0	0
T130	7905	9	0	0
T131	1710	10	0	0
T132	1200	8	0	0
T133	1852	15	0	0
T134	10831	22	0	0
T135	1968	26	0	0
T136	1400	9	0	0