Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	6742164	9809	0	0
StatusRise_A	6742164	13294	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6742164	9809	0	0
T1	45744	3	0	0
T2	11301	66	0	0
T3	5442	0	0	0
T4	5070	15	0	0
T5	7122	54	0	0
T6	10215	54	0	0
T7	14217	54	0	0
T8	4467	6	0	0
T9	6780	0	0	0
T10	2067	3	0	0
T12	0	6	0	0
T40	0	54	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6742164	13294	0	0
T1	45744	6	0	0
T2	11301	72	0	0
T3	5442	15	0	0
T4	5070	21	0	0
T5	7122	60	0	0
T6	10215	57	0	0
T7	14217	60	0	0
T8	4467	9	0	0
T9	6780	18	0	0
T10	2067	9	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	2247388	3310	0	0
StatusRise_A	2247388	4482	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2247388	3310	0	0
T1	15248	1	0	0
T2	3767	22	0	0
T3	1814	0	0	0
T4	1690	5	0	0
T5	2374	18	0	0
T6	3405	18	0	0
T7	4739	18	0	0
T8	1489	2	0	0
T9	2260	0	0	0
T10	689	1	0	0
T12	0	2	0	0
T40	0	18	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2247388	4482	0	0
T1	15248	2	0	0
T2	3767	24	0	0
T3	1814	5	0	0
T4	1690	7	0	0
T5	2374	20	0	0
T6	3405	19	0	0
T7	4739	20	0	0
T8	1489	3	0	0
T9	2260	6	0	0
T10	689	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	2247388	3310	0	0
StatusRise_A	2247388	4482	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2247388	3310	0	0
T1	15248	1	0	0
T2	3767	22	0	0
T3	1814	0	0	0
T4	1690	5	0	0
T5	2374	18	0	0
T6	3405	18	0	0
T7	4739	18	0	0
T8	1489	2	0	0
T9	2260	0	0	0
T10	689	1	0	0
T12	0	2	0	0
T40	0	18	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2247388	4482	0	0
T1	15248	2	0	0
T2	3767	24	0	0
T3	1814	5	0	0
T4	1690	7	0	0
T5	2374	20	0	0
T6	3405	19	0	0
T7	4739	20	0	0
T8	1489	3	0	0
T9	2260	6	0	0
T10	689	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	2247388	3189	0	0
StatusRise_A	2247388	4330	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2247388	3189	0	0
T1	15248	1	0	0
T2	3767	22	0	0
T3	1814	0	0	0
T4	1690	5	0	0
T5	2374	18	0	0
T6	3405	18	0	0
T7	4739	18	0	0
T8	1489	2	0	0
T9	2260	0	0	0
T10	689	1	0	0
T12	0	2	0	0
T40	0	18	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2247388	4330	0	0
T1	15248	2	0	0
T2	3767	24	0	0
T3	1814	5	0	0
T4	1690	7	0	0
T5	2374	20	0	0
T6	3405	19	0	0
T7	4739	20	0	0
T8	1489	3	0	0
T9	2260	6	0	0
T10	689	3	0	0