Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	2247748	5244	0	0
EscTimeoutStoppedByClReset_A	2247388	82592	0	0
EscTimeoutTriggersReset_A	317229	315	0	0
RomAllowActiveState_A	2247388	4112	0	0
RomAllowCheckGoodState_A	2247388	4162	0	0
RomBlockActiveState_A	2247388	28563	0	0
RomBlockCheckGoodState_A	2247388	17950	0	0
RomIntgChkDisFalse_A	2247388	2057576	0	0
RomIntgChkDisTrue_A	2247388	34636	0	0
RstreqChkEsctimeout_A	2247388	1027	0	0
RstreqChkFsmterm_A	2247388	140	0	0
RstreqChkGlbesc_A	2247388	1027	0	0
RstreqChkMainpd_A	2247388	58697	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2247748	5244	0	0
T1	15249	31	0	0
T2	3767	0	0	0
T3	1815	0	0	0
T4	1691	0	0	0
T5	2374	0	0	0
T6	3405	0	0	0
T7	4739	0	0	0
T8	1489	0	0	0
T9	2260	0	0	0
T10	690	0	0	0
T11	0	3	0	0
T32	0	5	0	0
T37	0	32	0	0
T43	0	129	0	0
T63	0	95	0	0
T96	0	32	0	0
T137	0	267	0	0
T138	0	15	0	0
T139	0	32	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2247388	82592	0	0
T1	15248	24	0	0
T2	3767	551	0	0
T3	1814	90	0	0
T4	1690	147	0	0
T5	2374	277	0	0
T6	3405	355	0	0
T7	4739	382	0	0
T8	1489	25	0	0
T9	2260	61	0	0
T10	689	12	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317229	315	0	0
T1	661	2	0	0
T2	571	0	0	0
T3	327	0	0	0
T4	524	0	0	0
T5	2048	0	0	0
T6	1083	0	0	0
T7	908	0	0	0
T8	254	0	0	0
T9	417	0	0	0
T10	337	5	0	0
T11	0	9	0	0
T32	0	4	0	0
T37	0	3	0	0
T43	0	2	0	0
T63	0	2	0	0
T137	0	3	0	0
T138	0	4	0	0
T139	0	3	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2247388	4112	0	0
T1	15248	2	0	0
T2	3767	24	0	0
T3	1814	5	0	0
T4	1690	7	0	0
T5	2374	13	0	0
T6	3405	12	0	0
T7	4739	13	0	0
T8	1489	3	0	0
T9	2260	6	0	0
T10	689	3	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2247388	4162	0	0
T1	15248	2	0	0
T2	3767	24	0	0
T3	1814	5	0	0
T4	1690	7	0	0
T5	2374	14	0	0
T6	3405	13	0	0
T7	4739	14	0	0
T8	1489	3	0	0
T9	2260	6	0	0
T10	689	3	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2247388	28563	0	0
T4	1690	217	0	0
T5	2374	0	0	0
T6	3405	0	0	0
T7	4739	0	0	0
T8	1489	0	0	0
T9	2260	0	0	0
T10	689	0	0	0
T12	1143	0	0	0
T18	2834	0	0	0
T27	0	314	0	0
T28	0	1108	0	0
T31	0	22	0	0
T36	0	577	0	0
T39	0	493	0	0
T40	2934	0	0	0
T42	0	318	0	0
T140	0	901	0	0
T141	0	1152	0	0
T142	0	810	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2247388	17950	0	0
T4	1690	45	0	0
T5	2374	0	0	0
T6	3405	0	0	0
T7	4739	0	0	0
T8	1489	0	0	0
T9	2260	0	0	0
T10	689	0	0	0
T12	1143	0	0	0
T18	2834	0	0	0
T27	0	145	0	0
T28	0	815	0	0
T36	0	386	0	0
T39	0	313	0	0
T40	2934	0	0	0
T42	0	51	0	0
T140	0	424	0	0
T141	0	881	0	0
T142	0	654	0	0
T143	0	78	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2247388	2057576	0	0
T1	15248	15173	0	0
T2	3767	3579	0	0
T3	1814	1425	0	0
T4	1690	1438	0	0
T5	2374	1501	0	0
T6	3405	2498	0	0
T7	4739	3746	0	0
T8	1489	1429	0	0
T9	2260	1768	0	0
T10	689	518	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2247388	34636	0	0
T4	1690	98	0	0
T5	2374	0	0	0
T6	3405	0	0	0
T7	4739	0	0	0
T8	1489	0	0	0
T9	2260	0	0	0
T10	689	0	0	0
T12	1143	0	0	0
T18	2834	0	0	0
T27	0	334	0	0
T28	0	173	0	0
T31	0	84	0	0
T36	0	1314	0	0
T39	0	178	0	0
T40	2934	0	0	0
T42	0	968	0	0
T140	0	1447	0	0
T141	0	2472	0	0
T142	0	265	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2247388	1027	0	0
T1	15248	1	0	0
T2	3767	8	0	0
T3	1814	0	0	0
T4	1690	2	0	0
T5	2374	6	0	0
T6	3405	7	0	0
T7	4739	5	0	0
T8	1489	0	0	0
T9	2260	0	0	0
T10	689	1	0	0
T11	0	1	0	0
T40	0	9	0	0
T41	0	9	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2247388	140	0	0
T20	22650	20	0	0
T21	0	20	0	0
T22	0	20	0	0
T29	0	40	0	0
T30	0	40	0	0
T31	982	0	0	0
T32	791	0	0	0
T33	6362	0	0	0
T34	2508	0	0	0
T35	4294	0	0	0
T36	3327	0	0	0
T37	2218	0	0	0
T38	2733	0	0	0
T39	2402	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2247388	1027	0	0
T1	15248	1	0	0
T2	3767	8	0	0
T3	1814	0	0	0
T4	1690	2	0	0
T5	2374	6	0	0
T6	3405	7	0	0
T7	4739	5	0	0
T8	1489	0	0	0
T9	2260	0	0	0
T10	689	1	0	0
T11	0	1	0	0
T40	0	9	0	0
T41	0	9	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2247388	58697	0	0
T2	3767	539	0	0
T3	1814	16	0	0
T4	1690	94	0	0
T5	2374	60	0	0
T6	3405	84	0	0
T7	4739	231	0	0
T8	1489	0	0	0
T9	2260	29	0	0
T10	689	0	0	0
T12	1143	0	0	0
T18	0	10	0	0
T40	0	79	0	0
T41	0	686	0	0