Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
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Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
98.68 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv


Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 64 1 63 98.44


Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
core_cp 2 0 2 100.00 100 1 1 2
io_cp 2 0 2 100.00 100 1 1 2
main_pd_n_cp 2 0 2 100.00 100 1 1 2
sleep_cp 2 0 2 100.00 100 1 1 2
usb_active_cp 2 0 2 100.00 100 1 1 2
usb_lp_cp 2 0 2 100.00 100 1 1 2


Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
control_cross 64 1 63 98.44 100 1 1 0


Summary for Variable core_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for core_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 592 1 T11 2 T12 2 T15 4
auto[1] 494 1 T15 2 T29 1 T50 3


Summary for Variable io_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for io_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 569 1 T11 2 T15 3 T50 1
auto[1] 517 1 T12 2 T15 3 T29 6


Summary for Variable main_pd_n_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for main_pd_n_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 472 1 T15 4 T29 2 T51 2
auto[1] 614 1 T11 2 T12 2 T15 2


Summary for Variable sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sleep_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 892 1 T11 1 T12 1 T15 4
auto[1] 194 1 T11 1 T12 1 T15 2


Summary for Variable usb_active_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_active_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 488 1 T15 5 T50 5 T51 4
auto[1] 598 1 T11 2 T12 2 T15 1


Summary for Variable usb_lp_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_lp_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 627 1 T11 2 T12 2 T15 5
auto[1] 459 1 T15 1 T29 4 T50 2


Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 1 63 98.44 1


Automatically Generated Cross Bins for control_cross

Uncovered bins
core_cpio_cpusb_lp_cpusb_active_cpmain_pd_n_cpsleep_cpCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [auto[1]] [auto[1]] [auto[0]] [auto[0]] [auto[1]] 0 1 1


Covered bins
core_cpio_cpusb_lp_cpusb_active_cpmain_pd_n_cpsleep_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] 30 1 T15 1 T13 1 T16 2
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] 4 1 T15 1 T146 1 T147 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] 30 1 T50 1 T51 1 T16 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] 7 1 T51 1 T148 1 T149 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] 21 1 T150 1 T151 1 T152 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] 1 1 T153 1 - - - -
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] 73 1 T11 1 T16 1 T55 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] 55 1 T11 1 T55 1 T59 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] 18 1 T150 1 T152 1 T154 2
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] 1 1 T150 1 - - - -
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] 23 1 T14 1 T16 2 T98 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] 6 1 T98 1 T56 1 T155 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] 28 1 T38 1 T60 1 T151 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] 6 1 T156 1 T157 1 T54 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] 21 1 T13 1 T38 2 T60 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] 4 1 T158 1 T149 1 T159 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] 22 1 T51 1 T14 1 T60 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] 4 1 T160 1 T161 1 T162 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] 26 1 T15 1 T50 1 T13 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] 7 1 T15 1 T50 1 T98 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] 31 1 T14 1 T16 1 T58 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] 6 1 T58 1 T157 1 T163 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] 37 1 T12 1 T29 1 T51 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] 10 1 T12 1 T51 1 T52 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] 21 1 T51 1 T58 1 T150 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] 5 1 T150 1 T164 1 T56 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] 30 1 T38 1 T97 3 T119 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] 5 1 T165 1 T56 1 T142 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] 23 1 T29 1 T13 1 T14 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] 4 1 T29 1 T26 1 T166 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] 30 1 T29 1 T14 2 T16 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] 3 1 T29 1 T167 1 T147 1
auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] 31 1 T13 1 T38 1 T100 1
auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] 8 1 T168 1 T169 1 T57 1
auto[1] auto[0] auto[0] auto[0] auto[1] auto[0] 22 1 T13 1 T96 1 T120 1
auto[1] auto[0] auto[0] auto[0] auto[1] auto[1] 3 1 T53 1 T158 1 T170 1
auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] 24 1 T15 1 T16 1 T97 2
auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] 3 1 T26 1 T171 2 - -
auto[1] auto[0] auto[0] auto[1] auto[1] auto[0] 22 1 T14 1 T16 1 T119 1
auto[1] auto[0] auto[0] auto[1] auto[1] auto[1] 3 1 T57 1 T170 1 T172 1
auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] 26 1 T38 2 T60 1 T96 3
auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] 5 1 T168 1 T161 1 T173 1
auto[1] auto[0] auto[1] auto[0] auto[1] auto[0] 27 1 T14 1 T16 2 T60 1
auto[1] auto[0] auto[1] auto[0] auto[1] auto[1] 4 1 T164 1 T162 1 T147 1
auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] 22 1 T13 1 T16 2 T38 1
auto[1] auto[0] auto[1] auto[1] auto[0] auto[1] 4 1 T174 1 T175 1 T176 1
auto[1] auto[0] auto[1] auto[1] auto[1] auto[0] 30 1 T14 1 T16 1 T38 2
auto[1] auto[0] auto[1] auto[1] auto[1] auto[1] 7 1 T177 1 T178 1 T153 1
auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] 37 1 T14 1 T16 1 T60 1
auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 8 1 T151 1 T156 1 T177 1
auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] 24 1 T52 1 T26 1 T120 1
auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] 1 1 T52 1 - - - -
auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] 30 1 T13 2 T14 1 T36 1
auto[1] auto[1] auto[0] auto[1] auto[0] auto[1] 4 1 T26 1 T179 1 T180 1
auto[1] auto[1] auto[0] auto[1] auto[1] auto[0] 36 1 T29 1 T50 1 T16 1
auto[1] auto[1] auto[0] auto[1] auto[1] auto[1] 7 1 T181 2 T180 1 T160 1
auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] 19 1 T15 1 T14 1 T96 1
auto[1] auto[1] auto[1] auto[0] auto[1] auto[0] 28 1 T50 1 T13 1 T16 1
auto[1] auto[1] auto[1] auto[0] auto[1] auto[1] 6 1 T50 1 T58 1 T182 1
auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] 24 1 T13 1 T16 1 T58 1
auto[1] auto[1] auto[1] auto[1] auto[0] auto[1] 2 1 T148 1 T183 1 - -
auto[1] auto[1] auto[1] auto[1] auto[1] auto[0] 26 1 T14 2 T96 1 T97 1
auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 1 1 T26 1 - - - -

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