Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::hw_reset_1_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::hw_reset_1_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

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Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::hw_reset_1_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	6	2	4	66.67

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::hw_reset_1_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::hw_reset_1_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
reset_cross	6	2	4	66.67	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

724

1

T7

11

T8

4

T22

8

auto[1]

817

1

T7

17

T8

3

T22

13

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Summary for Variable reset_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for reset_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1200

1

T1

1

T2

1

T3

2

auto[1]

716

1

T7

14

T8

3

T22

11

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1822

1

T1

1

T2

1

T3

2

auto[1]

94

1

T11

1

T12

1

T55

1

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Summary for Cross reset_cross

Samples crossed: reset_cp enable_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	6	2	4	66.67	2
Automatically Generated Cross Bins	6	2	4	66.67	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for reset_cross

Element holes

reset_cp	enable_cp	sleep_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

reset_cp

enable_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

400

1

T7

6

T8

3

T22

4

auto[0]

auto[1]

auto[0]

425

1

T7

8

T8

1

T22

6

auto[1]

auto[0]

auto[0]

324

1

T7

5

T8

1

T22

4

auto[1]

auto[1]

auto[0]

392

1

T7

9

T8

2

T22

7

User Defined Cross Bins for reset_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal	0	Illegal