Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.25 98.23 96.15 99.44 96.00 96.18 100.00 94.76


Total test records in report: 739
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T563 /workspace/coverage/default/42.pwrmgr_reset.3130793778 Jul 24 05:09:11 PM PDT 24 Jul 24 05:09:12 PM PDT 24 158082070 ps
T564 /workspace/coverage/default/13.pwrmgr_esc_clk_rst_malfunc.41456628 Jul 24 05:07:55 PM PDT 24 Jul 24 05:08:01 PM PDT 24 38213528 ps
T208 /workspace/coverage/default/0.pwrmgr_wakeup.3232553029 Jul 24 05:07:04 PM PDT 24 Jul 24 05:07:05 PM PDT 24 57977046 ps
T565 /workspace/coverage/default/24.pwrmgr_reset_invalid.3806909705 Jul 24 05:08:12 PM PDT 24 Jul 24 05:08:14 PM PDT 24 158964101 ps
T566 /workspace/coverage/default/41.pwrmgr_reset_invalid.640738032 Jul 24 05:09:11 PM PDT 24 Jul 24 05:09:12 PM PDT 24 195080100 ps
T173 /workspace/coverage/default/31.pwrmgr_lowpower_invalid.3470317780 Jul 24 05:08:22 PM PDT 24 Jul 24 05:08:22 PM PDT 24 44343232 ps
T567 /workspace/coverage/default/17.pwrmgr_reset_invalid.2910225922 Jul 24 05:07:51 PM PDT 24 Jul 24 05:07:52 PM PDT 24 105591092 ps
T568 /workspace/coverage/default/40.pwrmgr_reset.1398192647 Jul 24 05:08:47 PM PDT 24 Jul 24 05:08:48 PM PDT 24 77827803 ps
T569 /workspace/coverage/default/14.pwrmgr_sec_cm_rstmgr_intersig_mubi.1798769902 Jul 24 05:08:12 PM PDT 24 Jul 24 05:08:14 PM PDT 24 120500326 ps
T147 /workspace/coverage/default/33.pwrmgr_lowpower_wakeup_race.669403493 Jul 24 05:08:39 PM PDT 24 Jul 24 05:08:40 PM PDT 24 134682051 ps
T570 /workspace/coverage/default/25.pwrmgr_reset_invalid.1855872479 Jul 24 05:08:31 PM PDT 24 Jul 24 05:08:32 PM PDT 24 111437518 ps
T207 /workspace/coverage/default/10.pwrmgr_lowpower_wakeup_race.526989167 Jul 24 05:07:44 PM PDT 24 Jul 24 05:07:45 PM PDT 24 91608327 ps
T571 /workspace/coverage/default/18.pwrmgr_global_esc.1927919537 Jul 24 05:08:03 PM PDT 24 Jul 24 05:08:03 PM PDT 24 72200465 ps
T572 /workspace/coverage/default/47.pwrmgr_sec_cm_ctrl_config_regwen.910656949 Jul 24 05:09:15 PM PDT 24 Jul 24 05:09:15 PM PDT 24 52302851 ps
T573 /workspace/coverage/default/38.pwrmgr_disable_rom_integrity_check.2963180299 Jul 24 05:08:33 PM PDT 24 Jul 24 05:08:34 PM PDT 24 89276916 ps
T574 /workspace/coverage/default/31.pwrmgr_aborted_low_power.2577803385 Jul 24 05:08:22 PM PDT 24 Jul 24 05:08:23 PM PDT 24 48001969 ps
T65 /workspace/coverage/default/32.pwrmgr_sec_cm_ctrl_config_regwen.1943804197 Jul 24 05:08:30 PM PDT 24 Jul 24 05:08:31 PM PDT 24 73531688 ps
T575 /workspace/coverage/default/14.pwrmgr_stress_all.3334728187 Jul 24 05:07:57 PM PDT 24 Jul 24 05:07:58 PM PDT 24 145773006 ps
T576 /workspace/coverage/default/48.pwrmgr_sec_cm_rstmgr_intersig_mubi.3396309449 Jul 24 05:09:07 PM PDT 24 Jul 24 05:09:08 PM PDT 24 94738387 ps
T577 /workspace/coverage/default/20.pwrmgr_lowpower_invalid.900251222 Jul 24 05:07:58 PM PDT 24 Jul 24 05:07:59 PM PDT 24 152293800 ps
T578 /workspace/coverage/default/13.pwrmgr_global_esc.3769100467 Jul 24 05:07:44 PM PDT 24 Jul 24 05:07:45 PM PDT 24 64263267 ps
T579 /workspace/coverage/default/49.pwrmgr_reset_invalid.597130856 Jul 24 05:09:20 PM PDT 24 Jul 24 05:09:21 PM PDT 24 149439322 ps
T580 /workspace/coverage/default/30.pwrmgr_reset.2182293251 Jul 24 05:08:27 PM PDT 24 Jul 24 05:08:27 PM PDT 24 95306506 ps
T581 /workspace/coverage/default/30.pwrmgr_aborted_low_power.1465499712 Jul 24 05:08:25 PM PDT 24 Jul 24 05:08:26 PM PDT 24 38778019 ps
T582 /workspace/coverage/default/29.pwrmgr_glitch.1380843293 Jul 24 05:08:42 PM PDT 24 Jul 24 05:08:43 PM PDT 24 72233074 ps
T583 /workspace/coverage/default/25.pwrmgr_escalation_timeout.62991977 Jul 24 05:08:19 PM PDT 24 Jul 24 05:08:20 PM PDT 24 231336587 ps
T584 /workspace/coverage/default/8.pwrmgr_global_esc.874328576 Jul 24 05:07:31 PM PDT 24 Jul 24 05:07:31 PM PDT 24 78618134 ps
T585 /workspace/coverage/default/25.pwrmgr_lowpower_invalid.3661253962 Jul 24 05:08:01 PM PDT 24 Jul 24 05:08:02 PM PDT 24 41641387 ps
T586 /workspace/coverage/default/47.pwrmgr_escalation_timeout.3428273800 Jul 24 05:09:18 PM PDT 24 Jul 24 05:09:19 PM PDT 24 314522964 ps
T587 /workspace/coverage/default/36.pwrmgr_esc_clk_rst_malfunc.2631319475 Jul 24 05:08:47 PM PDT 24 Jul 24 05:08:48 PM PDT 24 64758608 ps
T588 /workspace/coverage/default/3.pwrmgr_reset_invalid.2556249277 Jul 24 05:07:05 PM PDT 24 Jul 24 05:07:06 PM PDT 24 104768966 ps
T589 /workspace/coverage/default/8.pwrmgr_reset.2965915825 Jul 24 05:07:11 PM PDT 24 Jul 24 05:07:12 PM PDT 24 199756576 ps
T590 /workspace/coverage/default/21.pwrmgr_aborted_low_power.406122805 Jul 24 05:08:04 PM PDT 24 Jul 24 05:08:04 PM PDT 24 20952867 ps
T591 /workspace/coverage/default/48.pwrmgr_global_esc.1486558883 Jul 24 05:09:06 PM PDT 24 Jul 24 05:09:07 PM PDT 24 39668633 ps
T592 /workspace/coverage/default/14.pwrmgr_reset_invalid.3048495519 Jul 24 05:07:41 PM PDT 24 Jul 24 05:07:42 PM PDT 24 296555860 ps
T593 /workspace/coverage/default/6.pwrmgr_reset.3879034771 Jul 24 05:07:35 PM PDT 24 Jul 24 05:07:36 PM PDT 24 42396158 ps
T594 /workspace/coverage/default/24.pwrmgr_reset.2880928034 Jul 24 05:08:21 PM PDT 24 Jul 24 05:08:22 PM PDT 24 59740775 ps
T595 /workspace/coverage/default/6.pwrmgr_esc_clk_rst_malfunc.3805315626 Jul 24 05:07:36 PM PDT 24 Jul 24 05:07:37 PM PDT 24 31741776 ps
T596 /workspace/coverage/default/48.pwrmgr_smoke.2347221496 Jul 24 05:09:02 PM PDT 24 Jul 24 05:09:03 PM PDT 24 160728739 ps
T597 /workspace/coverage/default/42.pwrmgr_glitch.3068099682 Jul 24 05:09:08 PM PDT 24 Jul 24 05:09:09 PM PDT 24 45512469 ps
T598 /workspace/coverage/default/14.pwrmgr_lowpower_invalid.2714960885 Jul 24 05:07:59 PM PDT 24 Jul 24 05:08:00 PM PDT 24 45405059 ps
T599 /workspace/coverage/default/32.pwrmgr_reset_invalid.1857349793 Jul 24 05:08:35 PM PDT 24 Jul 24 05:08:37 PM PDT 24 111893354 ps
T600 /workspace/coverage/default/38.pwrmgr_aborted_low_power.249816653 Jul 24 05:08:52 PM PDT 24 Jul 24 05:08:53 PM PDT 24 53346521 ps
T601 /workspace/coverage/default/45.pwrmgr_esc_clk_rst_malfunc.2271103295 Jul 24 05:09:15 PM PDT 24 Jul 24 05:09:16 PM PDT 24 31604201 ps
T602 /workspace/coverage/default/14.pwrmgr_smoke.709493183 Jul 24 05:08:22 PM PDT 24 Jul 24 05:08:23 PM PDT 24 31574907 ps
T603 /workspace/coverage/default/42.pwrmgr_sec_cm_rstmgr_intersig_mubi.761860715 Jul 24 05:08:53 PM PDT 24 Jul 24 05:08:54 PM PDT 24 146288875 ps
T604 /workspace/coverage/default/35.pwrmgr_escalation_timeout.2184701960 Jul 24 05:08:33 PM PDT 24 Jul 24 05:08:35 PM PDT 24 164936400 ps
T605 /workspace/coverage/default/34.pwrmgr_esc_clk_rst_malfunc.3888869584 Jul 24 05:08:39 PM PDT 24 Jul 24 05:08:39 PM PDT 24 29400048 ps
T606 /workspace/coverage/default/44.pwrmgr_aborted_low_power.1312576533 Jul 24 05:09:08 PM PDT 24 Jul 24 05:09:09 PM PDT 24 41042972 ps
T607 /workspace/coverage/default/16.pwrmgr_reset.2294930695 Jul 24 05:07:46 PM PDT 24 Jul 24 05:07:47 PM PDT 24 104449655 ps
T608 /workspace/coverage/default/4.pwrmgr_sec_cm_rstmgr_intersig_mubi.3820884413 Jul 24 05:07:20 PM PDT 24 Jul 24 05:07:21 PM PDT 24 186907710 ps
T609 /workspace/coverage/default/11.pwrmgr_smoke.2948666696 Jul 24 05:07:39 PM PDT 24 Jul 24 05:07:40 PM PDT 24 33121188 ps
T610 /workspace/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.2541056563 Jul 24 05:07:37 PM PDT 24 Jul 24 05:07:38 PM PDT 24 67602138 ps
T611 /workspace/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.970272583 Jul 24 05:07:33 PM PDT 24 Jul 24 05:07:34 PM PDT 24 28626452 ps
T612 /workspace/coverage/default/20.pwrmgr_escalation_timeout.2586125425 Jul 24 05:08:00 PM PDT 24 Jul 24 05:08:01 PM PDT 24 1259832243 ps
T172 /workspace/coverage/default/16.pwrmgr_lowpower_invalid.3877488503 Jul 24 05:08:00 PM PDT 24 Jul 24 05:08:01 PM PDT 24 111879424 ps
T613 /workspace/coverage/default/1.pwrmgr_global_esc.4187882190 Jul 24 05:07:07 PM PDT 24 Jul 24 05:07:08 PM PDT 24 49447682 ps
T614 /workspace/coverage/default/15.pwrmgr_sec_cm_rstmgr_intersig_mubi.1071168957 Jul 24 05:07:58 PM PDT 24 Jul 24 05:07:59 PM PDT 24 75783689 ps
T615 /workspace/coverage/default/34.pwrmgr_glitch.4274555239 Jul 24 05:08:36 PM PDT 24 Jul 24 05:08:37 PM PDT 24 46092450 ps
T209 /workspace/coverage/default/25.pwrmgr_wakeup.48775610 Jul 24 05:08:12 PM PDT 24 Jul 24 05:08:13 PM PDT 24 74795152 ps
T616 /workspace/coverage/default/29.pwrmgr_reset.1114297659 Jul 24 05:08:26 PM PDT 24 Jul 24 05:08:32 PM PDT 24 53751611 ps
T617 /workspace/coverage/default/39.pwrmgr_aborted_low_power.1788304693 Jul 24 05:08:56 PM PDT 24 Jul 24 05:08:57 PM PDT 24 44673913 ps
T618 /workspace/coverage/default/21.pwrmgr_reset_invalid.4105389709 Jul 24 05:08:08 PM PDT 24 Jul 24 05:08:10 PM PDT 24 113192196 ps
T619 /workspace/coverage/default/43.pwrmgr_smoke.1555824479 Jul 24 05:09:10 PM PDT 24 Jul 24 05:09:11 PM PDT 24 59184798 ps
T620 /workspace/coverage/default/0.pwrmgr_sec_cm_ctrl_config_regwen.1588523330 Jul 24 05:07:22 PM PDT 24 Jul 24 05:07:23 PM PDT 24 38870816 ps
T621 /workspace/coverage/default/31.pwrmgr_escalation_timeout.3425823818 Jul 24 05:08:40 PM PDT 24 Jul 24 05:08:41 PM PDT 24 634876248 ps
T622 /workspace/coverage/default/37.pwrmgr_sec_cm_rstmgr_intersig_mubi.2072923230 Jul 24 05:08:48 PM PDT 24 Jul 24 05:08:49 PM PDT 24 95887066 ps
T623 /workspace/coverage/default/5.pwrmgr_sec_cm_rstmgr_intersig_mubi.2558171513 Jul 24 05:07:25 PM PDT 24 Jul 24 05:07:26 PM PDT 24 55822226 ps
T624 /workspace/coverage/default/18.pwrmgr_smoke.402593194 Jul 24 05:07:59 PM PDT 24 Jul 24 05:08:00 PM PDT 24 64832202 ps
T31 /workspace/coverage/default/4.pwrmgr_sec_cm.2355470605 Jul 24 05:07:31 PM PDT 24 Jul 24 05:07:33 PM PDT 24 627437654 ps
T625 /workspace/coverage/default/12.pwrmgr_reset_invalid.2915436573 Jul 24 05:07:42 PM PDT 24 Jul 24 05:07:43 PM PDT 24 95187250 ps
T626 /workspace/coverage/default/41.pwrmgr_esc_clk_rst_malfunc.877241221 Jul 24 05:08:53 PM PDT 24 Jul 24 05:08:54 PM PDT 24 39080196 ps
T627 /workspace/coverage/default/47.pwrmgr_global_esc.4066622907 Jul 24 05:09:12 PM PDT 24 Jul 24 05:09:13 PM PDT 24 46167009 ps
T628 /workspace/coverage/default/41.pwrmgr_aborted_low_power.2307159613 Jul 24 05:08:58 PM PDT 24 Jul 24 05:08:59 PM PDT 24 37787470 ps
T23 /workspace/coverage/cover_reg_top/4.pwrmgr_tl_errors.3441797522 Jul 24 05:06:44 PM PDT 24 Jul 24 05:06:46 PM PDT 24 110962930 ps
T24 /workspace/coverage/cover_reg_top/14.pwrmgr_tl_errors.2203663573 Jul 24 05:06:52 PM PDT 24 Jul 24 05:06:53 PM PDT 24 55974206 ps
T66 /workspace/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.1592238909 Jul 24 05:07:06 PM PDT 24 Jul 24 05:07:07 PM PDT 24 20758755 ps
T78 /workspace/coverage/cover_reg_top/37.pwrmgr_intr_test.3690578151 Jul 24 05:07:04 PM PDT 24 Jul 24 05:07:04 PM PDT 24 45139734 ps
T25 /workspace/coverage/cover_reg_top/0.pwrmgr_tl_errors.4288115240 Jul 24 05:06:35 PM PDT 24 Jul 24 05:06:37 PM PDT 24 48106501 ps
T82 /workspace/coverage/cover_reg_top/12.pwrmgr_csr_rw.937424234 Jul 24 05:06:57 PM PDT 24 Jul 24 05:06:58 PM PDT 24 17527419 ps
T77 /workspace/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.3456431743 Jul 24 05:07:07 PM PDT 24 Jul 24 05:07:08 PM PDT 24 43849341 ps
T61 /workspace/coverage/cover_reg_top/5.pwrmgr_tl_errors.599992876 Jul 24 05:06:58 PM PDT 24 Jul 24 05:07:00 PM PDT 24 110250211 ps
T62 /workspace/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.2096250926 Jul 24 05:07:05 PM PDT 24 Jul 24 05:07:06 PM PDT 24 230480434 ps
T67 /workspace/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.335830194 Jul 24 05:06:58 PM PDT 24 Jul 24 05:06:59 PM PDT 24 80198353 ps
T68 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.4034344580 Jul 24 05:06:38 PM PDT 24 Jul 24 05:06:39 PM PDT 24 74273631 ps
T79 /workspace/coverage/cover_reg_top/29.pwrmgr_intr_test.677225455 Jul 24 05:07:07 PM PDT 24 Jul 24 05:07:09 PM PDT 24 22687897 ps
T69 /workspace/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.2143651698 Jul 24 05:06:50 PM PDT 24 Jul 24 05:06:52 PM PDT 24 47116517 ps
T99 /workspace/coverage/cover_reg_top/3.pwrmgr_tl_errors.2507847435 Jul 24 05:06:45 PM PDT 24 Jul 24 05:06:47 PM PDT 24 196946370 ps
T80 /workspace/coverage/cover_reg_top/34.pwrmgr_intr_test.1965885721 Jul 24 05:07:02 PM PDT 24 Jul 24 05:07:03 PM PDT 24 17130562 ps
T114 /workspace/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.4119121432 Jul 24 05:06:53 PM PDT 24 Jul 24 05:06:54 PM PDT 24 71885637 ps
T187 /workspace/coverage/cover_reg_top/18.pwrmgr_intr_test.2238081699 Jul 24 05:07:08 PM PDT 24 Jul 24 05:07:14 PM PDT 24 53570735 ps
T184 /workspace/coverage/cover_reg_top/35.pwrmgr_intr_test.145353239 Jul 24 05:07:06 PM PDT 24 Jul 24 05:07:07 PM PDT 24 19443926 ps
T185 /workspace/coverage/cover_reg_top/39.pwrmgr_intr_test.940572088 Jul 24 05:06:53 PM PDT 24 Jul 24 05:06:54 PM PDT 24 42382568 ps
T63 /workspace/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.1488236274 Jul 24 05:06:58 PM PDT 24 Jul 24 05:07:00 PM PDT 24 432246556 ps
T115 /workspace/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.2499760801 Jul 24 05:06:48 PM PDT 24 Jul 24 05:06:49 PM PDT 24 51193155 ps
T87 /workspace/coverage/cover_reg_top/15.pwrmgr_tl_errors.2697368076 Jul 24 05:06:40 PM PDT 24 Jul 24 05:06:42 PM PDT 24 280734074 ps
T64 /workspace/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.1044503820 Jul 24 05:06:47 PM PDT 24 Jul 24 05:06:49 PM PDT 24 283222111 ps
T88 /workspace/coverage/cover_reg_top/11.pwrmgr_tl_errors.2937145962 Jul 24 05:06:56 PM PDT 24 Jul 24 05:06:57 PM PDT 24 287660956 ps
T629 /workspace/coverage/cover_reg_top/45.pwrmgr_intr_test.1583385197 Jul 24 05:07:05 PM PDT 24 Jul 24 05:07:06 PM PDT 24 32874588 ps
T85 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.2254544881 Jul 24 05:06:51 PM PDT 24 Jul 24 05:06:52 PM PDT 24 177201901 ps
T186 /workspace/coverage/cover_reg_top/36.pwrmgr_intr_test.810207917 Jul 24 05:07:01 PM PDT 24 Jul 24 05:07:02 PM PDT 24 43537103 ps
T630 /workspace/coverage/cover_reg_top/21.pwrmgr_intr_test.2099023065 Jul 24 05:06:53 PM PDT 24 Jul 24 05:06:54 PM PDT 24 31915226 ps
T631 /workspace/coverage/cover_reg_top/16.pwrmgr_intr_test.1372577065 Jul 24 05:07:06 PM PDT 24 Jul 24 05:07:07 PM PDT 24 17586936 ps
T632 /workspace/coverage/cover_reg_top/43.pwrmgr_intr_test.2142499313 Jul 24 05:07:01 PM PDT 24 Jul 24 05:07:02 PM PDT 24 16704055 ps
T105 /workspace/coverage/cover_reg_top/6.pwrmgr_csr_rw.433029127 Jul 24 05:06:52 PM PDT 24 Jul 24 05:06:53 PM PDT 24 17899926 ps
T116 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_rw.3855807854 Jul 24 05:06:41 PM PDT 24 Jul 24 05:06:42 PM PDT 24 33980417 ps
T633 /workspace/coverage/cover_reg_top/38.pwrmgr_intr_test.2132885255 Jul 24 05:07:07 PM PDT 24 Jul 24 05:07:08 PM PDT 24 19629163 ps
T117 /workspace/coverage/cover_reg_top/15.pwrmgr_csr_rw.2386286024 Jul 24 05:07:02 PM PDT 24 Jul 24 05:07:03 PM PDT 24 51136553 ps
T75 /workspace/coverage/cover_reg_top/2.pwrmgr_tl_errors.4146529064 Jul 24 05:06:43 PM PDT 24 Jul 24 05:06:51 PM PDT 24 97685399 ps
T86 /workspace/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.4076601321 Jul 24 05:06:44 PM PDT 24 Jul 24 05:06:45 PM PDT 24 40364286 ps
T634 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.2629400280 Jul 24 05:06:49 PM PDT 24 Jul 24 05:06:55 PM PDT 24 23912629 ps
T123 /workspace/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.906179184 Jul 24 05:06:52 PM PDT 24 Jul 24 05:06:53 PM PDT 24 67593954 ps
T635 /workspace/coverage/cover_reg_top/7.pwrmgr_intr_test.3916757168 Jul 24 05:06:57 PM PDT 24 Jul 24 05:06:58 PM PDT 24 19614307 ps
T636 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.3949790732 Jul 24 05:06:40 PM PDT 24 Jul 24 05:06:41 PM PDT 24 76726885 ps
T144 /workspace/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.2378618836 Jul 24 05:06:48 PM PDT 24 Jul 24 05:06:50 PM PDT 24 236855534 ps
T118 /workspace/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.3397201786 Jul 24 05:06:41 PM PDT 24 Jul 24 05:06:43 PM PDT 24 408513739 ps
T637 /workspace/coverage/cover_reg_top/19.pwrmgr_csr_rw.2780055951 Jul 24 05:07:24 PM PDT 24 Jul 24 05:07:25 PM PDT 24 50838536 ps
T81 /workspace/coverage/cover_reg_top/17.pwrmgr_tl_errors.2522236257 Jul 24 05:06:54 PM PDT 24 Jul 24 05:06:56 PM PDT 24 37150446 ps
T638 /workspace/coverage/cover_reg_top/42.pwrmgr_intr_test.1394344060 Jul 24 05:07:16 PM PDT 24 Jul 24 05:07:17 PM PDT 24 17093875 ps
T124 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.971981941 Jul 24 05:06:41 PM PDT 24 Jul 24 05:06:44 PM PDT 24 169482767 ps
T106 /workspace/coverage/cover_reg_top/10.pwrmgr_csr_rw.1905344714 Jul 24 05:06:51 PM PDT 24 Jul 24 05:06:51 PM PDT 24 51163484 ps
T639 /workspace/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.4085922628 Jul 24 05:07:04 PM PDT 24 Jul 24 05:07:05 PM PDT 24 30838509 ps
T125 /workspace/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.2340576877 Jul 24 05:06:47 PM PDT 24 Jul 24 05:06:48 PM PDT 24 543296823 ps
T126 /workspace/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.4287924224 Jul 24 05:06:49 PM PDT 24 Jul 24 05:06:50 PM PDT 24 73965957 ps
T83 /workspace/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.2861015348 Jul 24 05:06:58 PM PDT 24 Jul 24 05:07:00 PM PDT 24 197470336 ps
T640 /workspace/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.3950578349 Jul 24 05:06:53 PM PDT 24 Jul 24 05:06:54 PM PDT 24 114050962 ps
T641 /workspace/coverage/cover_reg_top/24.pwrmgr_intr_test.3727875924 Jul 24 05:06:55 PM PDT 24 Jul 24 05:06:55 PM PDT 24 34649164 ps
T642 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.925492466 Jul 24 05:06:50 PM PDT 24 Jul 24 05:06:51 PM PDT 24 33938193 ps
T643 /workspace/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.3030904599 Jul 24 05:07:03 PM PDT 24 Jul 24 05:07:05 PM PDT 24 814439100 ps
T644 /workspace/coverage/cover_reg_top/12.pwrmgr_tl_errors.3370700290 Jul 24 05:06:57 PM PDT 24 Jul 24 05:06:59 PM PDT 24 94017228 ps
T645 /workspace/coverage/cover_reg_top/17.pwrmgr_csr_rw.30769703 Jul 24 05:06:47 PM PDT 24 Jul 24 05:06:48 PM PDT 24 150376830 ps
T646 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.110785170 Jul 24 05:06:56 PM PDT 24 Jul 24 05:06:58 PM PDT 24 173941476 ps
T647 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.2810641267 Jul 24 05:06:46 PM PDT 24 Jul 24 05:06:48 PM PDT 24 47236985 ps
T648 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.105740510 Jul 24 05:06:41 PM PDT 24 Jul 24 05:06:45 PM PDT 24 1031985033 ps
T649 /workspace/coverage/cover_reg_top/47.pwrmgr_intr_test.789248711 Jul 24 05:06:56 PM PDT 24 Jul 24 05:06:57 PM PDT 24 19454164 ps
T650 /workspace/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.2138979679 Jul 24 05:06:51 PM PDT 24 Jul 24 05:06:52 PM PDT 24 71022653 ps
T651 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.2610411232 Jul 24 05:06:45 PM PDT 24 Jul 24 05:06:46 PM PDT 24 32553793 ps
T652 /workspace/coverage/cover_reg_top/6.pwrmgr_intr_test.3211410073 Jul 24 05:06:47 PM PDT 24 Jul 24 05:06:49 PM PDT 24 18858343 ps
T653 /workspace/coverage/cover_reg_top/3.pwrmgr_intr_test.3783957288 Jul 24 05:06:48 PM PDT 24 Jul 24 05:06:49 PM PDT 24 39466639 ps
T654 /workspace/coverage/cover_reg_top/8.pwrmgr_intr_test.2057116993 Jul 24 05:06:54 PM PDT 24 Jul 24 05:06:55 PM PDT 24 22078658 ps
T655 /workspace/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.3578205251 Jul 24 05:06:53 PM PDT 24 Jul 24 05:06:54 PM PDT 24 30001228 ps
T656 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.3397308933 Jul 24 05:06:47 PM PDT 24 Jul 24 05:06:49 PM PDT 24 61401333 ps
T657 /workspace/coverage/cover_reg_top/5.pwrmgr_csr_rw.1446212245 Jul 24 05:07:01 PM PDT 24 Jul 24 05:07:02 PM PDT 24 18484381 ps
T658 /workspace/coverage/cover_reg_top/30.pwrmgr_intr_test.879948741 Jul 24 05:07:05 PM PDT 24 Jul 24 05:07:06 PM PDT 24 32776470 ps
T659 /workspace/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.209294780 Jul 24 05:06:54 PM PDT 24 Jul 24 05:06:56 PM PDT 24 233396479 ps
T660 /workspace/coverage/cover_reg_top/0.pwrmgr_intr_test.3041759251 Jul 24 05:06:54 PM PDT 24 Jul 24 05:06:55 PM PDT 24 19781420 ps
T661 /workspace/coverage/cover_reg_top/48.pwrmgr_intr_test.3017678292 Jul 24 05:07:08 PM PDT 24 Jul 24 05:07:09 PM PDT 24 18530174 ps
T76 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.1161378105 Jul 24 05:06:45 PM PDT 24 Jul 24 05:06:46 PM PDT 24 41574557 ps
T662 /workspace/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.2734293333 Jul 24 05:06:44 PM PDT 24 Jul 24 05:06:45 PM PDT 24 40917256 ps
T107 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.121595538 Jul 24 05:06:36 PM PDT 24 Jul 24 05:06:37 PM PDT 24 35237657 ps
T663 /workspace/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.346360786 Jul 24 05:06:53 PM PDT 24 Jul 24 05:06:54 PM PDT 24 64737441 ps
T664 /workspace/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.1269972967 Jul 24 05:07:00 PM PDT 24 Jul 24 05:07:01 PM PDT 24 53343673 ps
T665 /workspace/coverage/cover_reg_top/20.pwrmgr_intr_test.3325666654 Jul 24 05:07:03 PM PDT 24 Jul 24 05:07:03 PM PDT 24 18142135 ps
T666 /workspace/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.1665550616 Jul 24 05:06:41 PM PDT 24 Jul 24 05:06:42 PM PDT 24 46525173 ps
T667 /workspace/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.2090092336 Jul 24 05:06:56 PM PDT 24 Jul 24 05:06:57 PM PDT 24 55088097 ps
T668 /workspace/coverage/cover_reg_top/14.pwrmgr_intr_test.3787081309 Jul 24 05:06:52 PM PDT 24 Jul 24 05:06:52 PM PDT 24 45791972 ps
T669 /workspace/coverage/cover_reg_top/23.pwrmgr_intr_test.3353785204 Jul 24 05:07:14 PM PDT 24 Jul 24 05:07:15 PM PDT 24 27268369 ps
T89 /workspace/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.1735466962 Jul 24 05:06:37 PM PDT 24 Jul 24 05:06:39 PM PDT 24 263735749 ps
T670 /workspace/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.1472245331 Jul 24 05:06:59 PM PDT 24 Jul 24 05:07:00 PM PDT 24 312687033 ps
T671 /workspace/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.80214465 Jul 24 05:06:48 PM PDT 24 Jul 24 05:06:49 PM PDT 24 52958356 ps
T672 /workspace/coverage/cover_reg_top/22.pwrmgr_intr_test.3237402388 Jul 24 05:06:57 PM PDT 24 Jul 24 05:06:57 PM PDT 24 33840099 ps
T673 /workspace/coverage/cover_reg_top/19.pwrmgr_tl_errors.3015452609 Jul 24 05:06:57 PM PDT 24 Jul 24 05:06:59 PM PDT 24 70510703 ps
T674 /workspace/coverage/cover_reg_top/8.pwrmgr_tl_errors.4293701286 Jul 24 05:06:50 PM PDT 24 Jul 24 05:06:52 PM PDT 24 47397646 ps
T675 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_rw.3386949572 Jul 24 05:06:53 PM PDT 24 Jul 24 05:06:53 PM PDT 24 48549803 ps
T676 /workspace/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.3729655928 Jul 24 05:06:44 PM PDT 24 Jul 24 05:06:45 PM PDT 24 51364797 ps
T108 /workspace/coverage/cover_reg_top/7.pwrmgr_csr_rw.657992189 Jul 24 05:06:49 PM PDT 24 Jul 24 05:06:50 PM PDT 24 44442420 ps
T677 /workspace/coverage/cover_reg_top/32.pwrmgr_intr_test.3140459506 Jul 24 05:06:59 PM PDT 24 Jul 24 05:07:00 PM PDT 24 18613444 ps
T90 /workspace/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.2124678852 Jul 24 05:06:53 PM PDT 24 Jul 24 05:06:59 PM PDT 24 156573279 ps
T91 /workspace/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.177142296 Jul 24 05:07:01 PM PDT 24 Jul 24 05:07:03 PM PDT 24 323289455 ps
T678 /workspace/coverage/cover_reg_top/12.pwrmgr_intr_test.254712585 Jul 24 05:06:54 PM PDT 24 Jul 24 05:06:55 PM PDT 24 18342696 ps
T679 /workspace/coverage/cover_reg_top/1.pwrmgr_tl_errors.2865950332 Jul 24 05:06:57 PM PDT 24 Jul 24 05:07:00 PM PDT 24 144890334 ps
T680 /workspace/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.253746841 Jul 24 05:07:14 PM PDT 24 Jul 24 05:07:15 PM PDT 24 24279596 ps
T681 /workspace/coverage/cover_reg_top/1.pwrmgr_intr_test.2518216263 Jul 24 05:06:50 PM PDT 24 Jul 24 05:06:51 PM PDT 24 54766845 ps
T109 /workspace/coverage/cover_reg_top/14.pwrmgr_csr_rw.3087513454 Jul 24 05:06:53 PM PDT 24 Jul 24 05:06:54 PM PDT 24 22422020 ps
T682 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.4293462539 Jul 24 05:06:50 PM PDT 24 Jul 24 05:06:51 PM PDT 24 42205527 ps
T683 /workspace/coverage/cover_reg_top/18.pwrmgr_tl_errors.4264935964 Jul 24 05:07:03 PM PDT 24 Jul 24 05:07:04 PM PDT 24 70056074 ps
T684 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_rw.2062107261 Jul 24 05:07:04 PM PDT 24 Jul 24 05:07:05 PM PDT 24 60676672 ps
T685 /workspace/coverage/cover_reg_top/15.pwrmgr_intr_test.2918346095 Jul 24 05:06:49 PM PDT 24 Jul 24 05:06:50 PM PDT 24 21105060 ps
T686 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.417654150 Jul 24 05:06:47 PM PDT 24 Jul 24 05:06:51 PM PDT 24 1698214015 ps
T687 /workspace/coverage/cover_reg_top/6.pwrmgr_tl_errors.3517357818 Jul 24 05:06:57 PM PDT 24 Jul 24 05:06:59 PM PDT 24 771847261 ps
T688 /workspace/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.1875801667 Jul 24 05:06:56 PM PDT 24 Jul 24 05:06:58 PM PDT 24 212757017 ps
T689 /workspace/coverage/cover_reg_top/40.pwrmgr_intr_test.1831683960 Jul 24 05:07:25 PM PDT 24 Jul 24 05:07:26 PM PDT 24 16600732 ps
T690 /workspace/coverage/cover_reg_top/16.pwrmgr_tl_errors.1967691647 Jul 24 05:06:56 PM PDT 24 Jul 24 05:06:58 PM PDT 24 106928698 ps
T691 /workspace/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.3346008559 Jul 24 05:07:09 PM PDT 24 Jul 24 05:07:10 PM PDT 24 167427644 ps
T692 /workspace/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.2604820199 Jul 24 05:06:53 PM PDT 24 Jul 24 05:06:54 PM PDT 24 25221064 ps
T693 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.2703471561 Jul 24 05:06:59 PM PDT 24 Jul 24 05:07:01 PM PDT 24 81713635 ps
T694 /workspace/coverage/cover_reg_top/27.pwrmgr_intr_test.1994261775 Jul 24 05:06:56 PM PDT 24 Jul 24 05:06:57 PM PDT 24 27781379 ps
T695 /workspace/coverage/cover_reg_top/19.pwrmgr_intr_test.3038567849 Jul 24 05:06:47 PM PDT 24 Jul 24 05:06:48 PM PDT 24 45072546 ps
T696 /workspace/coverage/cover_reg_top/11.pwrmgr_csr_rw.660328372 Jul 24 05:06:56 PM PDT 24 Jul 24 05:06:57 PM PDT 24 37972702 ps
T145 /workspace/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.184867300 Jul 24 05:06:48 PM PDT 24 Jul 24 05:06:50 PM PDT 24 172555536 ps
T697 /workspace/coverage/cover_reg_top/16.pwrmgr_csr_rw.1772962373 Jul 24 05:07:00 PM PDT 24 Jul 24 05:07:01 PM PDT 24 18081090 ps
T698 /workspace/coverage/cover_reg_top/26.pwrmgr_intr_test.1234197548 Jul 24 05:06:53 PM PDT 24 Jul 24 05:06:53 PM PDT 24 39208901 ps
T699 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.444598833 Jul 24 05:06:42 PM PDT 24 Jul 24 05:06:46 PM PDT 24 218379855 ps
T700 /workspace/coverage/cover_reg_top/49.pwrmgr_intr_test.3653585950 Jul 24 05:07:28 PM PDT 24 Jul 24 05:07:28 PM PDT 24 30858360 ps
T143 /workspace/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.1408803129 Jul 24 05:06:55 PM PDT 24 Jul 24 05:06:57 PM PDT 24 169363083 ps
T110 /workspace/coverage/cover_reg_top/18.pwrmgr_csr_rw.1226281411 Jul 24 05:07:15 PM PDT 24 Jul 24 05:07:16 PM PDT 24 19944398 ps
T701 /workspace/coverage/cover_reg_top/17.pwrmgr_intr_test.1388697601 Jul 24 05:07:00 PM PDT 24 Jul 24 05:07:01 PM PDT 24 16560306 ps
T702 /workspace/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.1874773242 Jul 24 05:06:50 PM PDT 24 Jul 24 05:06:51 PM PDT 24 57800775 ps
T703 /workspace/coverage/cover_reg_top/5.pwrmgr_intr_test.2480382934 Jul 24 05:06:53 PM PDT 24 Jul 24 05:06:54 PM PDT 24 38213637 ps
T704 /workspace/coverage/cover_reg_top/25.pwrmgr_intr_test.3253568537 Jul 24 05:06:54 PM PDT 24 Jul 24 05:06:55 PM PDT 24 31635535 ps
T705 /workspace/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.3501213656 Jul 24 05:06:40 PM PDT 24 Jul 24 05:06:42 PM PDT 24 452742497 ps
T706 /workspace/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.1769431083 Jul 24 05:06:33 PM PDT 24 Jul 24 05:06:35 PM PDT 24 219729516 ps
T707 /workspace/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.3230962859 Jul 24 05:07:03 PM PDT 24 Jul 24 05:07:04 PM PDT 24 114152800 ps
T708 /workspace/coverage/cover_reg_top/10.pwrmgr_intr_test.2156307836 Jul 24 05:06:45 PM PDT 24 Jul 24 05:06:46 PM PDT 24 22557184 ps
T84 /workspace/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.87225678 Jul 24 05:06:53 PM PDT 24 Jul 24 05:06:55 PM PDT 24 389479260 ps
T709 /workspace/coverage/cover_reg_top/7.pwrmgr_tl_errors.2361425294 Jul 24 05:06:48 PM PDT 24 Jul 24 05:06:51 PM PDT 24 81745091 ps
T710 /workspace/coverage/cover_reg_top/9.pwrmgr_intr_test.4182804057 Jul 24 05:06:48 PM PDT 24 Jul 24 05:06:49 PM PDT 24 53598976 ps
T711 /workspace/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.1614919175 Jul 24 05:07:13 PM PDT 24 Jul 24 05:07:14 PM PDT 24 72234604 ps
T712 /workspace/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.1250284998 Jul 24 05:06:56 PM PDT 24 Jul 24 05:06:58 PM PDT 24 85448919 ps
T713 /workspace/coverage/cover_reg_top/28.pwrmgr_intr_test.2427820248 Jul 24 05:06:57 PM PDT 24 Jul 24 05:06:58 PM PDT 24 54818154 ps
T714 /workspace/coverage/cover_reg_top/33.pwrmgr_intr_test.1514142305 Jul 24 05:06:55 PM PDT 24 Jul 24 05:06:56 PM PDT 24 17597584 ps
T715 /workspace/coverage/cover_reg_top/13.pwrmgr_csr_rw.4116905787 Jul 24 05:07:03 PM PDT 24 Jul 24 05:07:04 PM PDT 24 22862641 ps
T111 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.1912051647 Jul 24 05:06:49 PM PDT 24 Jul 24 05:06:50 PM PDT 24 81815872 ps
T716 /workspace/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.2174481152 Jul 24 05:06:55 PM PDT 24 Jul 24 05:06:56 PM PDT 24 168045915 ps
T717 /workspace/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.179424738 Jul 24 05:07:19 PM PDT 24 Jul 24 05:07:21 PM PDT 24 120673086 ps
T718 /workspace/coverage/cover_reg_top/9.pwrmgr_tl_errors.1002869184 Jul 24 05:06:48 PM PDT 24 Jul 24 05:06:51 PM PDT 24 48410431 ps
T112 /workspace/coverage/cover_reg_top/8.pwrmgr_csr_rw.895719985 Jul 24 05:06:43 PM PDT 24 Jul 24 05:06:44 PM PDT 24 29884616 ps
T719 /workspace/coverage/cover_reg_top/2.pwrmgr_intr_test.673136679 Jul 24 05:06:45 PM PDT 24 Jul 24 05:06:46 PM PDT 24 17836948 ps
T720 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_rw.2931379409 Jul 24 05:06:47 PM PDT 24 Jul 24 05:06:48 PM PDT 24 32432809 ps
T721 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.419650585 Jul 24 05:06:30 PM PDT 24 Jul 24 05:06:31 PM PDT 24 26391447 ps
T722 /workspace/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.1965954668 Jul 24 05:07:14 PM PDT 24 Jul 24 05:07:15 PM PDT 24 677040188 ps
T723 /workspace/coverage/cover_reg_top/11.pwrmgr_intr_test.1737207960 Jul 24 05:06:56 PM PDT 24 Jul 24 05:06:56 PM PDT 24 19316639 ps
T724 /workspace/coverage/cover_reg_top/4.pwrmgr_intr_test.1203764245 Jul 24 05:06:44 PM PDT 24 Jul 24 05:06:44 PM PDT 24 23676063 ps
T725 /workspace/coverage/cover_reg_top/41.pwrmgr_intr_test.792619858 Jul 24 05:07:20 PM PDT 24 Jul 24 05:07:21 PM PDT 24 19810872 ps
T726 /workspace/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.750037027 Jul 24 05:06:44 PM PDT 24 Jul 24 05:06:45 PM PDT 24 149845397 ps
T727 /workspace/coverage/cover_reg_top/31.pwrmgr_intr_test.1597018339 Jul 24 05:06:57 PM PDT 24 Jul 24 05:06:58 PM PDT 24 20787118 ps
T728 /workspace/coverage/cover_reg_top/10.pwrmgr_tl_errors.3181907380 Jul 24 05:07:29 PM PDT 24 Jul 24 05:07:36 PM PDT 24 397232106 ps
T729 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_rw.3505005179 Jul 24 05:06:50 PM PDT 24 Jul 24 05:06:51 PM PDT 24 99981101 ps
T730 /workspace/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.2356200002 Jul 24 05:06:42 PM PDT 24 Jul 24 05:06:44 PM PDT 24 99965556 ps
T113 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.1969806062 Jul 24 05:07:06 PM PDT 24 Jul 24 05:07:07 PM PDT 24 28741154 ps
T731 /workspace/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.2633439613 Jul 24 05:06:46 PM PDT 24 Jul 24 05:06:47 PM PDT 24 60531799 ps
T732 /workspace/coverage/cover_reg_top/46.pwrmgr_intr_test.662947829 Jul 24 05:07:03 PM PDT 24 Jul 24 05:07:04 PM PDT 24 91717102 ps
T733 /workspace/coverage/cover_reg_top/44.pwrmgr_intr_test.3085437302 Jul 24 05:06:59 PM PDT 24 Jul 24 05:07:00 PM PDT 24 18310686 ps
T734 /workspace/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.664863909 Jul 24 05:06:45 PM PDT 24 Jul 24 05:06:47 PM PDT 24 1162113988 ps
T735 /workspace/coverage/cover_reg_top/9.pwrmgr_csr_rw.4225558257 Jul 24 05:06:57 PM PDT 24 Jul 24 05:06:58 PM PDT 24 27727249 ps
T736 /workspace/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.2368513960 Jul 24 05:07:13 PM PDT 24 Jul 24 05:07:14 PM PDT 24 41506259 ps
T737 /workspace/coverage/cover_reg_top/13.pwrmgr_intr_test.2070824787 Jul 24 05:07:26 PM PDT 24 Jul 24 05:07:27 PM PDT 24 29496524 ps
T738 /workspace/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.1233258065 Jul 24 05:06:56 PM PDT 24 Jul 24 05:06:57 PM PDT 24 54850157 ps
T739 /workspace/coverage/cover_reg_top/13.pwrmgr_tl_errors.2548006097 Jul 24 05:06:56 PM PDT 24 Jul 24 05:06:58 PM PDT 24 308252914 ps

Test location /workspace/coverage/default/22.pwrmgr_disable_rom_integrity_check.2848197830
Short name T8
Test name
Test status
Simulation time 55435476 ps
CPU time 0.77 seconds
Started Jul 24 05:07:57 PM PDT 24
Finished Jul 24 05:07:58 PM PDT 24
Peak memory 199100 kb
Host smart-39ca74a7-3948-4278-8eca-94a1ea4357ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848197830 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_dis
able_rom_integrity_check.2848197830
Directory /workspace/22.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/0.pwrmgr_smoke.2492108657
Short name T11
Test name
Test status
Simulation time 55944991 ps
CPU time 0.62 seconds
Started Jul 24 05:07:13 PM PDT 24
Finished Jul 24 05:07:13 PM PDT 24
Peak memory 199004 kb
Host smart-b2312d14-428d-420b-be4c-782679cebd4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492108657 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_smoke.2492108657
Directory /workspace/0.pwrmgr_smoke/latest

Test location /workspace/coverage/default/38.pwrmgr_reset_invalid.1211964099
Short name T74
Test name
Test status
Simulation time 149334735 ps
CPU time 0.82 seconds
Started Jul 24 05:08:36 PM PDT 24
Finished Jul 24 05:08:37 PM PDT 24
Peak memory 210048 kb
Host smart-b92214fc-b44d-4d32-baa5-c5e84bf4c5a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211964099 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset_invalid.1211964099
Directory /workspace/38.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/23.pwrmgr_aborted_low_power.1532254022
Short name T14
Test name
Test status
Simulation time 40114675 ps
CPU time 0.87 seconds
Started Jul 24 05:07:42 PM PDT 24
Finished Jul 24 05:07:44 PM PDT 24
Peak memory 201308 kb
Host smart-03002d73-4121-46d9-bf9f-ca9d6216f00a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532254022 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_aborted_low_power.1532254022
Directory /workspace/23.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.2096250926
Short name T62
Test name
Test status
Simulation time 230480434 ps
CPU time 1.07 seconds
Started Jul 24 05:07:05 PM PDT 24
Finished Jul 24 05:07:06 PM PDT 24
Peak memory 200912 kb
Host smart-90b87eaf-5dba-4d79-810f-fee880b775dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096250926 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_intg_er
r.2096250926
Directory /workspace/15.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm.1449569373
Short name T20
Test name
Test status
Simulation time 375157066 ps
CPU time 1.18 seconds
Started Jul 24 05:07:05 PM PDT 24
Finished Jul 24 05:07:06 PM PDT 24
Peak memory 217404 kb
Host smart-47a0b89b-d209-4770-a6ad-97c958809547
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449569373 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm.1449569373
Directory /workspace/1.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/49.pwrmgr_lowpower_invalid.1082829581
Short name T15
Test name
Test status
Simulation time 49958358 ps
CPU time 0.67 seconds
Started Jul 24 05:09:13 PM PDT 24
Finished Jul 24 05:09:14 PM PDT 24
Peak memory 201968 kb
Host smart-4dd4682b-c6f3-4751-a63f-ac34137ac4a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082829581 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_lowpower_inval
id.1082829581
Directory /workspace/49.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/17.pwrmgr_sec_cm_ctrl_config_regwen.4129363552
Short name T26
Test name
Test status
Simulation time 89329837 ps
CPU time 0.7 seconds
Started Jul 24 05:07:55 PM PDT 24
Finished Jul 24 05:07:56 PM PDT 24
Peak memory 199148 kb
Host smart-facd82c0-d776-4d46-a5f9-3ffdd3881a34
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129363552 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_
cm_ctrl_config_regwen.4129363552
Directory /workspace/17.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.2254544881
Short name T85
Test name
Test status
Simulation time 177201901 ps
CPU time 0.89 seconds
Started Jul 24 05:06:51 PM PDT 24
Finished Jul 24 05:06:52 PM PDT 24
Peak memory 195760 kb
Host smart-a0b61622-e21f-4db0-91f0-9f4cc88c7ae9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254544881 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.pwrmgr_csr_mem_rw_with_rand_reset.2254544881
Directory /workspace/4.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/36.pwrmgr_sec_cm_rstmgr_intersig_mubi.2456600853
Short name T46
Test name
Test status
Simulation time 74312411 ps
CPU time 0.75 seconds
Started Jul 24 05:08:46 PM PDT 24
Finished Jul 24 05:08:47 PM PDT 24
Peak memory 198624 kb
Host smart-6e4c66f2-d92c-4356-95ae-0a23e700f503
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456600853 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2456600853
Directory /workspace/36.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/34.pwrmgr_aborted_low_power.658877694
Short name T152
Test name
Test status
Simulation time 32922439 ps
CPU time 0.97 seconds
Started Jul 24 05:08:28 PM PDT 24
Finished Jul 24 05:08:29 PM PDT 24
Peak memory 201336 kb
Host smart-4c11081e-4362-4411-99ba-33f82530a755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658877694 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_aborted_low_power.658877694
Directory /workspace/34.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/10.pwrmgr_esc_clk_rst_malfunc.3714136916
Short name T6
Test name
Test status
Simulation time 33175102 ps
CPU time 0.62 seconds
Started Jul 24 05:07:39 PM PDT 24
Finished Jul 24 05:07:40 PM PDT 24
Peak memory 197872 kb
Host smart-e1c66d79-eee6-4522-88f6-29549eb39ef5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714136916 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_esc_clk_rst
_malfunc.3714136916
Directory /workspace/10.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/cover_reg_top/29.pwrmgr_intr_test.677225455
Short name T79
Test name
Test status
Simulation time 22687897 ps
CPU time 0.63 seconds
Started Jul 24 05:07:07 PM PDT 24
Finished Jul 24 05:07:09 PM PDT 24
Peak memory 195540 kb
Host smart-309e7a54-b6d3-4eaa-be49-3f48233cb0f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677225455 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.pwrmgr_intr_test.677225455
Directory /workspace/29.pwrmgr_intr_test/latest

Test location /workspace/coverage/default/26.pwrmgr_wakeup.2349612157
Short name T56
Test name
Test status
Simulation time 77530856 ps
CPU time 0.82 seconds
Started Jul 24 05:08:29 PM PDT 24
Finished Jul 24 05:08:30 PM PDT 24
Peak memory 198804 kb
Host smart-30183328-d64d-4ee2-9ff4-9a53cd2ac481
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349612157 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_wakeup.2349612157
Directory /workspace/26.pwrmgr_wakeup/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.1912051647
Short name T111
Test name
Test status
Simulation time 81815872 ps
CPU time 0.78 seconds
Started Jul 24 05:06:49 PM PDT 24
Finished Jul 24 05:06:50 PM PDT 24
Peak memory 197848 kb
Host smart-42cfad23-7f73-4566-8916-e91f4d1db6c5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912051647 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_aliasing.1
912051647
Directory /workspace/1.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/default/40.pwrmgr_lowpower_invalid.389352715
Short name T58
Test name
Test status
Simulation time 54416915 ps
CPU time 0.67 seconds
Started Jul 24 05:08:51 PM PDT 24
Finished Jul 24 05:08:52 PM PDT 24
Peak memory 201952 kb
Host smart-6b8cec42-0e4d-4b2f-a752-7f33921a8fed
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389352715 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_lowpower_invali
d.389352715
Directory /workspace/40.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/0.pwrmgr_aborted_low_power.3291440285
Short name T60
Test name
Test status
Simulation time 308780340 ps
CPU time 0.7 seconds
Started Jul 24 05:07:17 PM PDT 24
Finished Jul 24 05:07:18 PM PDT 24
Peak memory 199252 kb
Host smart-470d7dff-4bdc-4fa5-8fa6-7051e1045385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291440285 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_aborted_low_power.3291440285
Directory /workspace/0.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/48.pwrmgr_disable_rom_integrity_check.2714059873
Short name T192
Test name
Test status
Simulation time 74894684 ps
CPU time 0.64 seconds
Started Jul 24 05:09:01 PM PDT 24
Finished Jul 24 05:09:01 PM PDT 24
Peak memory 199008 kb
Host smart-8dacd4ab-b294-4bdd-85ac-7f817545b630
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714059873 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_dis
able_rom_integrity_check.2714059873
Directory /workspace/48.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_tl_errors.4146529064
Short name T75
Test name
Test status
Simulation time 97685399 ps
CPU time 1.88 seconds
Started Jul 24 05:06:43 PM PDT 24
Finished Jul 24 05:06:51 PM PDT 24
Peak memory 198036 kb
Host smart-73c3083d-2cda-4b3b-b285-5acec63fc727
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146529064 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_errors.4146529064
Directory /workspace/2.pwrmgr_tl_errors/latest

Test location /workspace/coverage/default/33.pwrmgr_lowpower_wakeup_race.669403493
Short name T147
Test name
Test status
Simulation time 134682051 ps
CPU time 0.83 seconds
Started Jul 24 05:08:39 PM PDT 24
Finished Jul 24 05:08:40 PM PDT 24
Peak memory 198884 kb
Host smart-45722848-994f-4b8f-8a09-a7424534633b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669403493 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_lowpower_wa
keup_race.669403493
Directory /workspace/33.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/41.pwrmgr_sec_cm_ctrl_config_regwen.4107404390
Short name T54
Test name
Test status
Simulation time 182411590 ps
CPU time 0.66 seconds
Started Jul 24 05:08:55 PM PDT 24
Finished Jul 24 05:08:56 PM PDT 24
Peak memory 199188 kb
Host smart-5919de94-1102-4acb-a552-0b091819a460
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107404390 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_
cm_ctrl_config_regwen.4107404390
Directory /workspace/41.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/28.pwrmgr_disable_rom_integrity_check.4143898847
Short name T204
Test name
Test status
Simulation time 49638984 ps
CPU time 0.77 seconds
Started Jul 24 05:08:32 PM PDT 24
Finished Jul 24 05:08:33 PM PDT 24
Peak memory 199656 kb
Host smart-736d67b3-4e17-4dc9-8a29-740a3294c176
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143898847 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_dis
able_rom_integrity_check.4143898847
Directory /workspace/28.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/4.pwrmgr_lowpower_wakeup_race.3964684230
Short name T52
Test name
Test status
Simulation time 63004706 ps
CPU time 0.66 seconds
Started Jul 24 05:07:29 PM PDT 24
Finished Jul 24 05:07:29 PM PDT 24
Peak memory 199688 kb
Host smart-ddf1feaf-6fc3-41d3-820c-b48de6274e5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964684230 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_lowpower_wa
keup_race.3964684230
Directory /workspace/4.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/24.pwrmgr_disable_rom_integrity_check.2938816668
Short name T134
Test name
Test status
Simulation time 131451360 ps
CPU time 0.66 seconds
Started Jul 24 05:08:20 PM PDT 24
Finished Jul 24 05:08:21 PM PDT 24
Peak memory 199008 kb
Host smart-e0f1654c-735a-47dd-90de-9d7b89d5081e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938816668 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_dis
able_rom_integrity_check.2938816668
Directory /workspace/24.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/22.pwrmgr_lowpower_invalid.1198064387
Short name T150
Test name
Test status
Simulation time 46386554 ps
CPU time 0.69 seconds
Started Jul 24 05:08:13 PM PDT 24
Finished Jul 24 05:08:15 PM PDT 24
Peak memory 201748 kb
Host smart-4783a281-53ad-4f67-bf4f-c1a017073ba2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198064387 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_lowpower_inval
id.1198064387
Directory /workspace/22.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.2861015348
Short name T83
Test name
Test status
Simulation time 197470336 ps
CPU time 1.67 seconds
Started Jul 24 05:06:58 PM PDT 24
Finished Jul 24 05:07:00 PM PDT 24
Peak memory 195856 kb
Host smart-12dc6867-dcf8-41d9-93f3-c09c75cc91b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861015348 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_intg_er
r.2861015348
Directory /workspace/11.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/15.pwrmgr_smoke.3566392227
Short name T33
Test name
Test status
Simulation time 28485666 ps
CPU time 0.71 seconds
Started Jul 24 05:07:58 PM PDT 24
Finished Jul 24 05:07:59 PM PDT 24
Peak memory 199776 kb
Host smart-b3ccaf08-3856-43c8-b01b-55fcfd115d7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566392227 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_smoke.3566392227
Directory /workspace/15.pwrmgr_smoke/latest

Test location /workspace/coverage/default/16.pwrmgr_disable_rom_integrity_check.3723693187
Short name T199
Test name
Test status
Simulation time 65212051 ps
CPU time 0.65 seconds
Started Jul 24 05:07:54 PM PDT 24
Finished Jul 24 05:07:55 PM PDT 24
Peak memory 198788 kb
Host smart-5d2a248e-d712-44c4-bf3e-65a9d401a4e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723693187 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_dis
able_rom_integrity_check.3723693187
Directory /workspace/16.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_csr_rw.2386286024
Short name T117
Test name
Test status
Simulation time 51136553 ps
CPU time 0.61 seconds
Started Jul 24 05:07:02 PM PDT 24
Finished Jul 24 05:07:03 PM PDT 24
Peak memory 195424 kb
Host smart-17a70e26-5da4-4f31-991d-fb921048719e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386286024 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_csr_rw.2386286024
Directory /workspace/15.pwrmgr_csr_rw/latest

Test location /workspace/coverage/default/0.pwrmgr_lowpower_invalid.523539539
Short name T158
Test name
Test status
Simulation time 90681324 ps
CPU time 0.65 seconds
Started Jul 24 05:07:08 PM PDT 24
Finished Jul 24 05:07:09 PM PDT 24
Peak memory 201792 kb
Host smart-5b5f13e0-25f7-4179-b827-bde521a227ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523539539 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_lowpower_invalid
.523539539
Directory /workspace/0.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/10.pwrmgr_disable_rom_integrity_check.2453804425
Short name T136
Test name
Test status
Simulation time 105254020 ps
CPU time 0.62 seconds
Started Jul 24 05:07:42 PM PDT 24
Finished Jul 24 05:07:44 PM PDT 24
Peak memory 198792 kb
Host smart-d004b715-f70f-44ee-8839-79ff6f35addf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453804425 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_dis
able_rom_integrity_check.2453804425
Directory /workspace/10.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/11.pwrmgr_lowpower_invalid.1085211525
Short name T180
Test name
Test status
Simulation time 45698880 ps
CPU time 0.72 seconds
Started Jul 24 05:07:53 PM PDT 24
Finished Jul 24 05:07:54 PM PDT 24
Peak memory 202016 kb
Host smart-81a3bbe7-e63b-425d-aa1b-129580c5d3d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085211525 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_lowpower_inval
id.1085211525
Directory /workspace/11.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.177142296
Short name T91
Test name
Test status
Simulation time 323289455 ps
CPU time 1.49 seconds
Started Jul 24 05:07:01 PM PDT 24
Finished Jul 24 05:07:03 PM PDT 24
Peak memory 195796 kb
Host smart-7dff834c-801f-491c-bc58-029bb6881506
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177142296 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_intg_err
.177142296
Directory /workspace/18.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm.3719532354
Short name T19
Test name
Test status
Simulation time 668056267 ps
CPU time 2.07 seconds
Started Jul 24 05:07:09 PM PDT 24
Finished Jul 24 05:07:12 PM PDT 24
Peak memory 218004 kb
Host smart-3453c137-160a-4bc4-879b-7ca44bf71d05
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719532354 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm.3719532354
Directory /workspace/0.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/11.pwrmgr_esc_clk_rst_malfunc.3899459275
Short name T1
Test name
Test status
Simulation time 35986776 ps
CPU time 0.61 seconds
Started Jul 24 05:07:42 PM PDT 24
Finished Jul 24 05:07:44 PM PDT 24
Peak memory 197732 kb
Host smart-6d6425a5-7e63-44be-9193-d60b0c6a8867
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899459275 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_esc_clk_rst
_malfunc.3899459275
Directory /workspace/11.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_intr_test.1372577065
Short name T631
Test name
Test status
Simulation time 17586936 ps
CPU time 0.6 seconds
Started Jul 24 05:07:06 PM PDT 24
Finished Jul 24 05:07:07 PM PDT 24
Peak memory 195336 kb
Host smart-868c8fab-583a-425f-987d-d665c76deb88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372577065 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_intr_test.1372577065
Directory /workspace/16.pwrmgr_intr_test/latest

Test location /workspace/coverage/default/1.pwrmgr_lowpower_invalid.440776395
Short name T177
Test name
Test status
Simulation time 40216111 ps
CPU time 0.69 seconds
Started Jul 24 05:07:02 PM PDT 24
Finished Jul 24 05:07:03 PM PDT 24
Peak memory 201904 kb
Host smart-a65caee9-b2e0-4bdb-8002-a638bad3e5ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440776395 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_lowpower_invalid
.440776395
Directory /workspace/1.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/12.pwrmgr_lowpower_invalid.3410765110
Short name T176
Test name
Test status
Simulation time 50419479 ps
CPU time 0.69 seconds
Started Jul 24 05:07:42 PM PDT 24
Finished Jul 24 05:07:43 PM PDT 24
Peak memory 201532 kb
Host smart-92a7162b-283d-4461-89d2-4ee539f8b75b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410765110 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_lowpower_inval
id.3410765110
Directory /workspace/12.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/13.pwrmgr_lowpower_invalid.2619188077
Short name T170
Test name
Test status
Simulation time 50806260 ps
CPU time 0.72 seconds
Started Jul 24 05:07:45 PM PDT 24
Finished Jul 24 05:07:46 PM PDT 24
Peak memory 201860 kb
Host smart-2e4dee2d-a0c8-4d62-83be-7aef9069c8f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619188077 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_lowpower_inval
id.2619188077
Directory /workspace/13.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/2.pwrmgr_lowpower_invalid.1021278487
Short name T160
Test name
Test status
Simulation time 46068230 ps
CPU time 0.7 seconds
Started Jul 24 05:07:25 PM PDT 24
Finished Jul 24 05:07:26 PM PDT 24
Peak memory 201932 kb
Host smart-b205f09c-7411-4577-98ec-98e00e0add48
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021278487 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_lowpower_invali
d.1021278487
Directory /workspace/2.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/20.pwrmgr_aborted_low_power.4116381434
Short name T38
Test name
Test status
Simulation time 101766585 ps
CPU time 0.78 seconds
Started Jul 24 05:08:01 PM PDT 24
Finished Jul 24 05:08:02 PM PDT 24
Peak memory 200664 kb
Host smart-1ed486d1-c4cf-4a5f-b9c3-b6f7303d0869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116381434 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_aborted_low_power.4116381434
Directory /workspace/20.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/23.pwrmgr_lowpower_invalid.3346765798
Short name T183
Test name
Test status
Simulation time 233756608 ps
CPU time 0.69 seconds
Started Jul 24 05:08:09 PM PDT 24
Finished Jul 24 05:08:10 PM PDT 24
Peak memory 201968 kb
Host smart-db1b5642-0d74-4acb-a0d3-8fec91b7e187
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346765798 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_lowpower_inval
id.3346765798
Directory /workspace/23.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/32.pwrmgr_sec_cm_ctrl_config_regwen.1943804197
Short name T65
Test name
Test status
Simulation time 73531688 ps
CPU time 0.85 seconds
Started Jul 24 05:08:30 PM PDT 24
Finished Jul 24 05:08:31 PM PDT 24
Peak memory 200336 kb
Host smart-97b9aa47-363f-4726-b580-5bc2a518dbb9
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943804197 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_
cm_ctrl_config_regwen.1943804197
Directory /workspace/32.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/4.pwrmgr_lowpower_invalid.1769882639
Short name T153
Test name
Test status
Simulation time 65116868 ps
CPU time 0.68 seconds
Started Jul 24 05:07:07 PM PDT 24
Finished Jul 24 05:07:08 PM PDT 24
Peak memory 201812 kb
Host smart-9bcfe9b5-c2f4-40bc-a34a-b0c79ff94922
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769882639 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_lowpower_invali
d.1769882639
Directory /workspace/4.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.2703471561
Short name T693
Test name
Test status
Simulation time 81713635 ps
CPU time 1.04 seconds
Started Jul 24 05:06:59 PM PDT 24
Finished Jul 24 05:07:01 PM PDT 24
Peak memory 196616 kb
Host smart-f8ff3144-d22c-4130-a3d0-6232899123ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703471561 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.pwrmgr_csr_mem_rw_with_rand_reset.2703471561
Directory /workspace/1.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.pwrmgr_glitch.1511532317
Short name T17
Test name
Test status
Simulation time 56311224 ps
CPU time 0.63 seconds
Started Jul 24 05:07:14 PM PDT 24
Finished Jul 24 05:07:14 PM PDT 24
Peak memory 198620 kb
Host smart-2bf110d5-ab62-463c-9803-1e785cbe48c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511532317 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_glitch.1511532317
Directory /workspace/0.pwrmgr_glitch/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.4034344580
Short name T68
Test name
Test status
Simulation time 74273631 ps
CPU time 1.01 seconds
Started Jul 24 05:06:38 PM PDT 24
Finished Jul 24 05:06:39 PM PDT 24
Peak memory 195436 kb
Host smart-a7bf2d70-1287-44f6-8df1-a7f4e6cfaa55
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034344580 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_aliasing.4
034344580
Directory /workspace/0.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.444598833
Short name T699
Test name
Test status
Simulation time 218379855 ps
CPU time 3.23 seconds
Started Jul 24 05:06:42 PM PDT 24
Finished Jul 24 05:06:46 PM PDT 24
Peak memory 195620 kb
Host smart-4fc6e96d-b301-4e0d-b5ec-d302f221a21f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444598833 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_bit_bash.444598833
Directory /workspace/0.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.121595538
Short name T107
Test name
Test status
Simulation time 35237657 ps
CPU time 0.76 seconds
Started Jul 24 05:06:36 PM PDT 24
Finished Jul 24 05:06:37 PM PDT 24
Peak memory 197716 kb
Host smart-d3dd037f-70a1-4d91-ab68-aa3d5fd1d91b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121595538 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_hw_reset.121595538
Directory /workspace/0.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.1161378105
Short name T76
Test name
Test status
Simulation time 41574557 ps
CPU time 0.84 seconds
Started Jul 24 05:06:45 PM PDT 24
Finished Jul 24 05:06:46 PM PDT 24
Peak memory 195776 kb
Host smart-1b3fc515-53c1-4f8c-9628-ebb1e255558c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161378105 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.pwrmgr_csr_mem_rw_with_rand_reset.1161378105
Directory /workspace/0.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_rw.3505005179
Short name T729
Test name
Test status
Simulation time 99981101 ps
CPU time 0.61 seconds
Started Jul 24 05:06:50 PM PDT 24
Finished Jul 24 05:06:51 PM PDT 24
Peak memory 197728 kb
Host smart-061a3c8a-a6bf-4397-aa24-d7b60fc2cb88
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505005179 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_rw.3505005179
Directory /workspace/0.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_intr_test.3041759251
Short name T660
Test name
Test status
Simulation time 19781420 ps
CPU time 0.6 seconds
Started Jul 24 05:06:54 PM PDT 24
Finished Jul 24 05:06:55 PM PDT 24
Peak memory 195528 kb
Host smart-ae33799e-ad1d-4669-8c5b-c9a1fffe7d21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041759251 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_intr_test.3041759251
Directory /workspace/0.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.1665550616
Short name T666
Test name
Test status
Simulation time 46525173 ps
CPU time 0.75 seconds
Started Jul 24 05:06:41 PM PDT 24
Finished Jul 24 05:06:42 PM PDT 24
Peak memory 197684 kb
Host smart-e305d4f4-f367-48c0-b4af-4e4ada1a937a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665550616 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sa
me_csr_outstanding.1665550616
Directory /workspace/0.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_tl_errors.4288115240
Short name T25
Test name
Test status
Simulation time 48106501 ps
CPU time 1.64 seconds
Started Jul 24 05:06:35 PM PDT 24
Finished Jul 24 05:06:37 PM PDT 24
Peak memory 196816 kb
Host smart-40a7fd52-8389-40cf-bcf6-5924edde33ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288115240 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_errors.4288115240
Directory /workspace/0.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.1769431083
Short name T706
Test name
Test status
Simulation time 219729516 ps
CPU time 1.02 seconds
Started Jul 24 05:06:33 PM PDT 24
Finished Jul 24 05:06:35 PM PDT 24
Peak memory 201088 kb
Host smart-ca0d5f0e-d96a-4459-a397-27e2c95774eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769431083 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_intg_err
.1769431083
Directory /workspace/0.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.105740510
Short name T648
Test name
Test status
Simulation time 1031985033 ps
CPU time 3.21 seconds
Started Jul 24 05:06:41 PM PDT 24
Finished Jul 24 05:06:45 PM PDT 24
Peak memory 199480 kb
Host smart-7015f34c-e9d9-410b-ad87-212d375f5252
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105740510 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_bit_bash.105740510
Directory /workspace/1.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.4293462539
Short name T682
Test name
Test status
Simulation time 42205527 ps
CPU time 0.62 seconds
Started Jul 24 05:06:50 PM PDT 24
Finished Jul 24 05:06:51 PM PDT 24
Peak memory 195468 kb
Host smart-fa8c9178-53aa-4efa-84de-dcf21bfb1ff0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293462539 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_hw_reset.4
293462539
Directory /workspace/1.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_rw.2931379409
Short name T720
Test name
Test status
Simulation time 32432809 ps
CPU time 0.66 seconds
Started Jul 24 05:06:47 PM PDT 24
Finished Jul 24 05:06:48 PM PDT 24
Peak memory 197828 kb
Host smart-97b2849e-33b4-4721-852c-07685e9974c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931379409 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_rw.2931379409
Directory /workspace/1.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_intr_test.2518216263
Short name T681
Test name
Test status
Simulation time 54766845 ps
CPU time 0.6 seconds
Started Jul 24 05:06:50 PM PDT 24
Finished Jul 24 05:06:51 PM PDT 24
Peak memory 195488 kb
Host smart-1025a1db-1e94-4e0a-b973-252586cc0439
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518216263 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_intr_test.2518216263
Directory /workspace/1.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.3397201786
Short name T118
Test name
Test status
Simulation time 408513739 ps
CPU time 0.87 seconds
Started Jul 24 05:06:41 PM PDT 24
Finished Jul 24 05:06:43 PM PDT 24
Peak memory 198808 kb
Host smart-f52d60f5-b34d-4cf5-8c3c-e672c2d5b91e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397201786 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sa
me_csr_outstanding.3397201786
Directory /workspace/1.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_tl_errors.2865950332
Short name T679
Test name
Test status
Simulation time 144890334 ps
CPU time 3.08 seconds
Started Jul 24 05:06:57 PM PDT 24
Finished Jul 24 05:07:00 PM PDT 24
Peak memory 198108 kb
Host smart-5f07c12a-441f-4d3d-b0c1-5f516c827f26
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865950332 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_errors.2865950332
Directory /workspace/1.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.2356200002
Short name T730
Test name
Test status
Simulation time 99965556 ps
CPU time 1.2 seconds
Started Jul 24 05:06:42 PM PDT 24
Finished Jul 24 05:06:44 PM PDT 24
Peak memory 201068 kb
Host smart-86000486-933c-4e65-b52b-c5af38fc966d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356200002 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_intg_err
.2356200002
Directory /workspace/1.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.4287924224
Short name T126
Test name
Test status
Simulation time 73965957 ps
CPU time 0.7 seconds
Started Jul 24 05:06:49 PM PDT 24
Finished Jul 24 05:06:50 PM PDT 24
Peak memory 195724 kb
Host smart-46a7dbcd-9f98-4ac1-8c11-900749ac1dc5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287924224 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.pwrmgr_csr_mem_rw_with_rand_reset.4287924224
Directory /workspace/10.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_csr_rw.1905344714
Short name T106
Test name
Test status
Simulation time 51163484 ps
CPU time 0.65 seconds
Started Jul 24 05:06:51 PM PDT 24
Finished Jul 24 05:06:51 PM PDT 24
Peak memory 197628 kb
Host smart-65dae126-aa0a-470d-932e-f3a4461a49fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905344714 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_csr_rw.1905344714
Directory /workspace/10.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_intr_test.2156307836
Short name T708
Test name
Test status
Simulation time 22557184 ps
CPU time 0.62 seconds
Started Jul 24 05:06:45 PM PDT 24
Finished Jul 24 05:06:46 PM PDT 24
Peak memory 195340 kb
Host smart-20045569-7f57-4d4a-9786-fd92d1728ecb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156307836 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_intr_test.2156307836
Directory /workspace/10.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.3578205251
Short name T655
Test name
Test status
Simulation time 30001228 ps
CPU time 0.71 seconds
Started Jul 24 05:06:53 PM PDT 24
Finished Jul 24 05:06:54 PM PDT 24
Peak memory 195488 kb
Host smart-c7dcac65-4147-4cf0-8920-4578f8d59645
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578205251 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_s
ame_csr_outstanding.3578205251
Directory /workspace/10.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_tl_errors.3181907380
Short name T728
Test name
Test status
Simulation time 397232106 ps
CPU time 2.25 seconds
Started Jul 24 05:07:29 PM PDT 24
Finished Jul 24 05:07:36 PM PDT 24
Peak memory 196908 kb
Host smart-f66663c2-58fa-4538-b31d-a154d9b3c648
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181907380 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_errors.3181907380
Directory /workspace/10.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.1408803129
Short name T143
Test name
Test status
Simulation time 169363083 ps
CPU time 1.47 seconds
Started Jul 24 05:06:55 PM PDT 24
Finished Jul 24 05:06:57 PM PDT 24
Peak memory 201024 kb
Host smart-e405ca4d-1766-444a-a9a2-ec19d23c2b31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408803129 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_intg_er
r.1408803129
Directory /workspace/10.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.750037027
Short name T726
Test name
Test status
Simulation time 149845397 ps
CPU time 1.41 seconds
Started Jul 24 05:06:44 PM PDT 24
Finished Jul 24 05:06:45 PM PDT 24
Peak memory 199544 kb
Host smart-16ec705a-e4b4-4d82-bfec-33eecd1e3afb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750037027 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.pwrmgr_csr_mem_rw_with_rand_reset.750037027
Directory /workspace/11.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_csr_rw.660328372
Short name T696
Test name
Test status
Simulation time 37972702 ps
CPU time 0.67 seconds
Started Jul 24 05:06:56 PM PDT 24
Finished Jul 24 05:06:57 PM PDT 24
Peak memory 197592 kb
Host smart-222d2393-5657-4542-bde2-97743bda4e36
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660328372 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_csr_rw.660328372
Directory /workspace/11.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_intr_test.1737207960
Short name T723
Test name
Test status
Simulation time 19316639 ps
CPU time 0.67 seconds
Started Jul 24 05:06:56 PM PDT 24
Finished Jul 24 05:06:56 PM PDT 24
Peak memory 195552 kb
Host smart-3b7ed672-985e-4c52-b036-a288e787216f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737207960 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_intr_test.1737207960
Directory /workspace/11.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.4119121432
Short name T114
Test name
Test status
Simulation time 71885637 ps
CPU time 0.88 seconds
Started Jul 24 05:06:53 PM PDT 24
Finished Jul 24 05:06:54 PM PDT 24
Peak memory 198852 kb
Host smart-4104fb27-ae6a-4f7b-9d10-861f5b4898d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119121432 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_s
ame_csr_outstanding.4119121432
Directory /workspace/11.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_tl_errors.2937145962
Short name T88
Test name
Test status
Simulation time 287660956 ps
CPU time 1.52 seconds
Started Jul 24 05:06:56 PM PDT 24
Finished Jul 24 05:06:57 PM PDT 24
Peak memory 196840 kb
Host smart-c908b22e-fc10-4dbe-881f-9e578912cd04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937145962 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_errors.2937145962
Directory /workspace/11.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.1614919175
Short name T711
Test name
Test status
Simulation time 72234604 ps
CPU time 0.75 seconds
Started Jul 24 05:07:13 PM PDT 24
Finished Jul 24 05:07:14 PM PDT 24
Peak memory 195564 kb
Host smart-26b8f9fa-b7bf-4607-8fac-3f17985b3cfd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614919175 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.pwrmgr_csr_mem_rw_with_rand_reset.1614919175
Directory /workspace/12.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_csr_rw.937424234
Short name T82
Test name
Test status
Simulation time 17527419 ps
CPU time 0.63 seconds
Started Jul 24 05:06:57 PM PDT 24
Finished Jul 24 05:06:58 PM PDT 24
Peak memory 197752 kb
Host smart-89235676-47ff-4135-88cb-33b5cdc4f2ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937424234 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_csr_rw.937424234
Directory /workspace/12.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_intr_test.254712585
Short name T678
Test name
Test status
Simulation time 18342696 ps
CPU time 0.57 seconds
Started Jul 24 05:06:54 PM PDT 24
Finished Jul 24 05:06:55 PM PDT 24
Peak memory 195500 kb
Host smart-9bc2ffb6-2e79-40f0-826e-70c7fbf8e123
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254712585 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_intr_test.254712585
Directory /workspace/12.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.2734293333
Short name T662
Test name
Test status
Simulation time 40917256 ps
CPU time 0.75 seconds
Started Jul 24 05:06:44 PM PDT 24
Finished Jul 24 05:06:45 PM PDT 24
Peak memory 195444 kb
Host smart-a05a6ff4-a0a6-403b-8b88-fdec144f86a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734293333 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_s
ame_csr_outstanding.2734293333
Directory /workspace/12.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_tl_errors.3370700290
Short name T644
Test name
Test status
Simulation time 94017228 ps
CPU time 1.22 seconds
Started Jul 24 05:06:57 PM PDT 24
Finished Jul 24 05:06:59 PM PDT 24
Peak memory 195940 kb
Host smart-a6b1f086-3c9e-4ac5-8d4a-cc283dc10af3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370700290 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_errors.3370700290
Directory /workspace/12.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.87225678
Short name T84
Test name
Test status
Simulation time 389479260 ps
CPU time 1.44 seconds
Started Jul 24 05:06:53 PM PDT 24
Finished Jul 24 05:06:55 PM PDT 24
Peak memory 195648 kb
Host smart-1fd2ce92-080e-4145-ab89-795b7502eff8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87225678 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_intg_err.87225678
Directory /workspace/12.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.80214465
Short name T671
Test name
Test status
Simulation time 52958356 ps
CPU time 0.89 seconds
Started Jul 24 05:06:48 PM PDT 24
Finished Jul 24 05:06:49 PM PDT 24
Peak memory 195656 kb
Host smart-45f5b313-550c-4042-809a-6dcb07492e12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80214465 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.pwrmgr_csr_mem_rw_with_rand_reset.80214465
Directory /workspace/13.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_csr_rw.4116905787
Short name T715
Test name
Test status
Simulation time 22862641 ps
CPU time 0.72 seconds
Started Jul 24 05:07:03 PM PDT 24
Finished Jul 24 05:07:04 PM PDT 24
Peak memory 197688 kb
Host smart-233e42fb-6178-46f3-bea6-8680012428b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116905787 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_csr_rw.4116905787
Directory /workspace/13.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_intr_test.2070824787
Short name T737
Test name
Test status
Simulation time 29496524 ps
CPU time 0.61 seconds
Started Jul 24 05:07:26 PM PDT 24
Finished Jul 24 05:07:27 PM PDT 24
Peak memory 195336 kb
Host smart-47e70976-df7d-43f4-b7b2-320da1e29ef6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070824787 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_intr_test.2070824787
Directory /workspace/13.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.1592238909
Short name T66
Test name
Test status
Simulation time 20758755 ps
CPU time 0.77 seconds
Started Jul 24 05:07:06 PM PDT 24
Finished Jul 24 05:07:07 PM PDT 24
Peak memory 197848 kb
Host smart-47ae1843-6074-4957-8b14-e462d16db8d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592238909 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_s
ame_csr_outstanding.1592238909
Directory /workspace/13.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_tl_errors.2548006097
Short name T739
Test name
Test status
Simulation time 308252914 ps
CPU time 1.81 seconds
Started Jul 24 05:06:56 PM PDT 24
Finished Jul 24 05:06:58 PM PDT 24
Peak memory 197024 kb
Host smart-75083cc0-525c-408e-b948-5a20ac3bcbda
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548006097 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_errors.2548006097
Directory /workspace/13.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.1965954668
Short name T722
Test name
Test status
Simulation time 677040188 ps
CPU time 1.06 seconds
Started Jul 24 05:07:14 PM PDT 24
Finished Jul 24 05:07:15 PM PDT 24
Peak memory 200964 kb
Host smart-9c948fa7-bfa9-4725-8e89-246ff366642d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965954668 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_intg_er
r.1965954668
Directory /workspace/13.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.1250284998
Short name T712
Test name
Test status
Simulation time 85448919 ps
CPU time 1.02 seconds
Started Jul 24 05:06:56 PM PDT 24
Finished Jul 24 05:06:58 PM PDT 24
Peak memory 195672 kb
Host smart-76bf33e3-a667-458d-93b2-ad107b7c8778
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250284998 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.pwrmgr_csr_mem_rw_with_rand_reset.1250284998
Directory /workspace/14.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_csr_rw.3087513454
Short name T109
Test name
Test status
Simulation time 22422020 ps
CPU time 0.7 seconds
Started Jul 24 05:06:53 PM PDT 24
Finished Jul 24 05:06:54 PM PDT 24
Peak memory 197708 kb
Host smart-3973410c-a29e-4443-9c62-4df109a9c18a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087513454 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_csr_rw.3087513454
Directory /workspace/14.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_intr_test.3787081309
Short name T668
Test name
Test status
Simulation time 45791972 ps
CPU time 0.65 seconds
Started Jul 24 05:06:52 PM PDT 24
Finished Jul 24 05:06:52 PM PDT 24
Peak memory 195448 kb
Host smart-387c74bf-9456-4977-a778-c3ee299bc69e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787081309 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_intr_test.3787081309
Directory /workspace/14.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.3230962859
Short name T707
Test name
Test status
Simulation time 114152800 ps
CPU time 0.81 seconds
Started Jul 24 05:07:03 PM PDT 24
Finished Jul 24 05:07:04 PM PDT 24
Peak memory 195388 kb
Host smart-260fc28c-66d1-43cb-ab3a-0e8a3674967f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230962859 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_s
ame_csr_outstanding.3230962859
Directory /workspace/14.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_tl_errors.2203663573
Short name T24
Test name
Test status
Simulation time 55974206 ps
CPU time 1.24 seconds
Started Jul 24 05:06:52 PM PDT 24
Finished Jul 24 05:06:53 PM PDT 24
Peak memory 196884 kb
Host smart-8bdc548b-10f4-42f8-8b01-cd68a3b0afa7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203663573 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_errors.2203663573
Directory /workspace/14.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.209294780
Short name T659
Test name
Test status
Simulation time 233396479 ps
CPU time 1.09 seconds
Started Jul 24 05:06:54 PM PDT 24
Finished Jul 24 05:06:56 PM PDT 24
Peak memory 200972 kb
Host smart-9a2b6f02-a59e-4327-bb74-7250a8356827
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209294780 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_intg_err
.209294780
Directory /workspace/14.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.3456431743
Short name T77
Test name
Test status
Simulation time 43849341 ps
CPU time 0.94 seconds
Started Jul 24 05:07:07 PM PDT 24
Finished Jul 24 05:07:08 PM PDT 24
Peak memory 195684 kb
Host smart-cc160b68-19a7-4bce-b0d8-1566aa33f19a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456431743 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.pwrmgr_csr_mem_rw_with_rand_reset.3456431743
Directory /workspace/15.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_intr_test.2918346095
Short name T685
Test name
Test status
Simulation time 21105060 ps
CPU time 0.66 seconds
Started Jul 24 05:06:49 PM PDT 24
Finished Jul 24 05:06:50 PM PDT 24
Peak memory 195456 kb
Host smart-7b9d2926-bbfb-4df5-afa6-3dae714de318
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918346095 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_intr_test.2918346095
Directory /workspace/15.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.2604820199
Short name T692
Test name
Test status
Simulation time 25221064 ps
CPU time 0.71 seconds
Started Jul 24 05:06:53 PM PDT 24
Finished Jul 24 05:06:54 PM PDT 24
Peak memory 195640 kb
Host smart-09d8b21a-db86-4c17-9516-ad08dcb1825c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604820199 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_s
ame_csr_outstanding.2604820199
Directory /workspace/15.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_tl_errors.2697368076
Short name T87
Test name
Test status
Simulation time 280734074 ps
CPU time 1.71 seconds
Started Jul 24 05:06:40 PM PDT 24
Finished Jul 24 05:06:42 PM PDT 24
Peak memory 196844 kb
Host smart-938f0c4e-bb93-40f9-a9d5-d6564ed12c7a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697368076 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_errors.2697368076
Directory /workspace/15.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.179424738
Short name T717
Test name
Test status
Simulation time 120673086 ps
CPU time 1.48 seconds
Started Jul 24 05:07:19 PM PDT 24
Finished Jul 24 05:07:21 PM PDT 24
Peak memory 198884 kb
Host smart-5fcf145e-f86f-453b-ba85-ee2f33adc995
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179424738 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.pwrmgr_csr_mem_rw_with_rand_reset.179424738
Directory /workspace/16.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_csr_rw.1772962373
Short name T697
Test name
Test status
Simulation time 18081090 ps
CPU time 0.63 seconds
Started Jul 24 05:07:00 PM PDT 24
Finished Jul 24 05:07:01 PM PDT 24
Peak memory 195600 kb
Host smart-bfcfd121-6341-4dba-b6a0-fbdf31128d1a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772962373 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_csr_rw.1772962373
Directory /workspace/16.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.335830194
Short name T67
Test name
Test status
Simulation time 80198353 ps
CPU time 0.72 seconds
Started Jul 24 05:06:58 PM PDT 24
Finished Jul 24 05:06:59 PM PDT 24
Peak memory 197756 kb
Host smart-d81e6473-8833-4bc5-a463-8001f8701647
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335830194 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sa
me_csr_outstanding.335830194
Directory /workspace/16.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_tl_errors.1967691647
Short name T690
Test name
Test status
Simulation time 106928698 ps
CPU time 2.04 seconds
Started Jul 24 05:06:56 PM PDT 24
Finished Jul 24 05:06:58 PM PDT 24
Peak memory 196780 kb
Host smart-952d495d-dca0-4763-8d6f-4c0244d105fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967691647 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_errors.1967691647
Directory /workspace/16.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.3950578349
Short name T640
Test name
Test status
Simulation time 114050962 ps
CPU time 1.09 seconds
Started Jul 24 05:06:53 PM PDT 24
Finished Jul 24 05:06:54 PM PDT 24
Peak memory 200844 kb
Host smart-35da3bff-4cb0-4c11-aaf0-2331fe2718e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950578349 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_intg_er
r.3950578349
Directory /workspace/16.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.2368513960
Short name T736
Test name
Test status
Simulation time 41506259 ps
CPU time 0.81 seconds
Started Jul 24 05:07:13 PM PDT 24
Finished Jul 24 05:07:14 PM PDT 24
Peak memory 195680 kb
Host smart-756506a0-f499-4964-8bcb-f1a0788e2224
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368513960 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.pwrmgr_csr_mem_rw_with_rand_reset.2368513960
Directory /workspace/17.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_csr_rw.30769703
Short name T645
Test name
Test status
Simulation time 150376830 ps
CPU time 0.61 seconds
Started Jul 24 05:06:47 PM PDT 24
Finished Jul 24 05:06:48 PM PDT 24
Peak memory 195456 kb
Host smart-8f3e8406-1ceb-4a57-b6c5-1d5a77ba9b49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30769703 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_csr_rw.30769703
Directory /workspace/17.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_intr_test.1388697601
Short name T701
Test name
Test status
Simulation time 16560306 ps
CPU time 0.62 seconds
Started Jul 24 05:07:00 PM PDT 24
Finished Jul 24 05:07:01 PM PDT 24
Peak memory 195432 kb
Host smart-8e8a622a-1940-454e-bfad-ebb2cde98ead
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388697601 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_intr_test.1388697601
Directory /workspace/17.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.2090092336
Short name T667
Test name
Test status
Simulation time 55088097 ps
CPU time 0.74 seconds
Started Jul 24 05:06:56 PM PDT 24
Finished Jul 24 05:06:57 PM PDT 24
Peak memory 198452 kb
Host smart-9ec6b6f7-14c9-41b7-bfc4-06e65498f6c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090092336 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_s
ame_csr_outstanding.2090092336
Directory /workspace/17.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_tl_errors.2522236257
Short name T81
Test name
Test status
Simulation time 37150446 ps
CPU time 1.5 seconds
Started Jul 24 05:06:54 PM PDT 24
Finished Jul 24 05:06:56 PM PDT 24
Peak memory 196752 kb
Host smart-f3c51323-692d-47d7-8220-ee3da5f753dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522236257 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_errors.2522236257
Directory /workspace/17.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.3346008559
Short name T691
Test name
Test status
Simulation time 167427644 ps
CPU time 1.54 seconds
Started Jul 24 05:07:09 PM PDT 24
Finished Jul 24 05:07:10 PM PDT 24
Peak memory 200940 kb
Host smart-fa38ea15-7ec2-4744-83ff-e17ad2092e93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346008559 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_intg_er
r.3346008559
Directory /workspace/17.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.1472245331
Short name T670
Test name
Test status
Simulation time 312687033 ps
CPU time 1.1 seconds
Started Jul 24 05:06:59 PM PDT 24
Finished Jul 24 05:07:00 PM PDT 24
Peak memory 196640 kb
Host smart-0a335547-93bc-4ce7-9c5f-83af7f307c38
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472245331 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.pwrmgr_csr_mem_rw_with_rand_reset.1472245331
Directory /workspace/18.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_csr_rw.1226281411
Short name T110
Test name
Test status
Simulation time 19944398 ps
CPU time 0.67 seconds
Started Jul 24 05:07:15 PM PDT 24
Finished Jul 24 05:07:16 PM PDT 24
Peak memory 197688 kb
Host smart-3763b87b-2b9b-4d14-a5ec-69bdf45c4b28
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226281411 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_csr_rw.1226281411
Directory /workspace/18.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_intr_test.2238081699
Short name T187
Test name
Test status
Simulation time 53570735 ps
CPU time 0.63 seconds
Started Jul 24 05:07:08 PM PDT 24
Finished Jul 24 05:07:14 PM PDT 24
Peak memory 195492 kb
Host smart-8a3bc1a6-a38b-4a88-b03d-0e3dda806146
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238081699 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_intr_test.2238081699
Directory /workspace/18.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.2499760801
Short name T115
Test name
Test status
Simulation time 51193155 ps
CPU time 0.71 seconds
Started Jul 24 05:06:48 PM PDT 24
Finished Jul 24 05:06:49 PM PDT 24
Peak memory 197764 kb
Host smart-df27d845-766c-490e-ad74-cd404df266ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499760801 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_s
ame_csr_outstanding.2499760801
Directory /workspace/18.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_tl_errors.4264935964
Short name T683
Test name
Test status
Simulation time 70056074 ps
CPU time 0.88 seconds
Started Jul 24 05:07:03 PM PDT 24
Finished Jul 24 05:07:04 PM PDT 24
Peak memory 195796 kb
Host smart-0f393605-8984-4f65-9e99-ad89c600bbd3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264935964 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_errors.4264935964
Directory /workspace/18.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.1269972967
Short name T664
Test name
Test status
Simulation time 53343673 ps
CPU time 1.18 seconds
Started Jul 24 05:07:00 PM PDT 24
Finished Jul 24 05:07:01 PM PDT 24
Peak memory 196756 kb
Host smart-49d49b29-d031-47b1-b79f-4374742bc45a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269972967 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.pwrmgr_csr_mem_rw_with_rand_reset.1269972967
Directory /workspace/19.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_csr_rw.2780055951
Short name T637
Test name
Test status
Simulation time 50838536 ps
CPU time 0.65 seconds
Started Jul 24 05:07:24 PM PDT 24
Finished Jul 24 05:07:25 PM PDT 24
Peak memory 197932 kb
Host smart-397106f2-2113-4946-8ab9-93c0ebafeb29
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780055951 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_csr_rw.2780055951
Directory /workspace/19.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_intr_test.3038567849
Short name T695
Test name
Test status
Simulation time 45072546 ps
CPU time 0.59 seconds
Started Jul 24 05:06:47 PM PDT 24
Finished Jul 24 05:06:48 PM PDT 24
Peak memory 195528 kb
Host smart-46f6985e-3ab2-483f-ad2e-56dc090df0b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038567849 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_intr_test.3038567849
Directory /workspace/19.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.1233258065
Short name T738
Test name
Test status
Simulation time 54850157 ps
CPU time 0.72 seconds
Started Jul 24 05:06:56 PM PDT 24
Finished Jul 24 05:06:57 PM PDT 24
Peak memory 195436 kb
Host smart-26fa5f6c-6497-4f85-ad23-b5c06dce0b69
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233258065 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_s
ame_csr_outstanding.1233258065
Directory /workspace/19.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_tl_errors.3015452609
Short name T673
Test name
Test status
Simulation time 70510703 ps
CPU time 1.43 seconds
Started Jul 24 05:06:57 PM PDT 24
Finished Jul 24 05:06:59 PM PDT 24
Peak memory 196812 kb
Host smart-03fcc36b-c1e6-427e-9cc6-4649278a500a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015452609 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_errors.3015452609
Directory /workspace/19.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.3030904599
Short name T643
Test name
Test status
Simulation time 814439100 ps
CPU time 1.09 seconds
Started Jul 24 05:07:03 PM PDT 24
Finished Jul 24 05:07:05 PM PDT 24
Peak memory 195808 kb
Host smart-4f71f9b6-3b3f-411a-81c4-5b13c5ad4041
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030904599 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_intg_er
r.3030904599
Directory /workspace/19.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.3949790732
Short name T636
Test name
Test status
Simulation time 76726885 ps
CPU time 0.95 seconds
Started Jul 24 05:06:40 PM PDT 24
Finished Jul 24 05:06:41 PM PDT 24
Peak memory 199208 kb
Host smart-d9a56f9d-53da-48ca-87f3-39d0ca3695dc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949790732 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_aliasing.3
949790732
Directory /workspace/2.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.417654150
Short name T686
Test name
Test status
Simulation time 1698214015 ps
CPU time 3.38 seconds
Started Jul 24 05:06:47 PM PDT 24
Finished Jul 24 05:06:51 PM PDT 24
Peak memory 195684 kb
Host smart-93bf73b9-7b26-4672-b24b-0c761d606878
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417654150 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_bit_bash.417654150
Directory /workspace/2.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.2610411232
Short name T651
Test name
Test status
Simulation time 32553793 ps
CPU time 0.7 seconds
Started Jul 24 05:06:45 PM PDT 24
Finished Jul 24 05:06:46 PM PDT 24
Peak memory 198968 kb
Host smart-76401e56-cdd3-4159-9988-d5e9de8fc725
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610411232 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_hw_reset.2
610411232
Directory /workspace/2.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.2810641267
Short name T647
Test name
Test status
Simulation time 47236985 ps
CPU time 0.84 seconds
Started Jul 24 05:06:46 PM PDT 24
Finished Jul 24 05:06:48 PM PDT 24
Peak memory 195656 kb
Host smart-064622ae-e0eb-41e1-975c-0e27087b8355
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810641267 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.pwrmgr_csr_mem_rw_with_rand_reset.2810641267
Directory /workspace/2.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_rw.3855807854
Short name T116
Test name
Test status
Simulation time 33980417 ps
CPU time 0.6 seconds
Started Jul 24 05:06:41 PM PDT 24
Finished Jul 24 05:06:42 PM PDT 24
Peak memory 195400 kb
Host smart-d757f24c-cc0c-4837-a16f-90768de0d496
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855807854 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_rw.3855807854
Directory /workspace/2.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_intr_test.673136679
Short name T719
Test name
Test status
Simulation time 17836948 ps
CPU time 0.66 seconds
Started Jul 24 05:06:45 PM PDT 24
Finished Jul 24 05:06:46 PM PDT 24
Peak memory 195436 kb
Host smart-7ccf7659-9efc-4463-af9b-981d447daa84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673136679 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_intr_test.673136679
Directory /workspace/2.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.2143651698
Short name T69
Test name
Test status
Simulation time 47116517 ps
CPU time 0.87 seconds
Started Jul 24 05:06:50 PM PDT 24
Finished Jul 24 05:06:52 PM PDT 24
Peak memory 199244 kb
Host smart-fef53141-f05e-412f-acd2-1355bb67be76
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143651698 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sa
me_csr_outstanding.2143651698
Directory /workspace/2.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.3501213656
Short name T705
Test name
Test status
Simulation time 452742497 ps
CPU time 1.61 seconds
Started Jul 24 05:06:40 PM PDT 24
Finished Jul 24 05:06:42 PM PDT 24
Peak memory 201060 kb
Host smart-23c56144-97f8-48e3-ae53-e906e0ac1d55
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501213656 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_intg_err
.3501213656
Directory /workspace/2.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.pwrmgr_intr_test.3325666654
Short name T665
Test name
Test status
Simulation time 18142135 ps
CPU time 0.62 seconds
Started Jul 24 05:07:03 PM PDT 24
Finished Jul 24 05:07:03 PM PDT 24
Peak memory 195452 kb
Host smart-ffec1aa6-f04d-4b9d-acb4-5814484df318
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325666654 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.pwrmgr_intr_test.3325666654
Directory /workspace/20.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.pwrmgr_intr_test.2099023065
Short name T630
Test name
Test status
Simulation time 31915226 ps
CPU time 0.63 seconds
Started Jul 24 05:06:53 PM PDT 24
Finished Jul 24 05:06:54 PM PDT 24
Peak memory 195464 kb
Host smart-6ce69b5f-81f0-4ccc-a521-28fc4b4d62f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099023065 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.pwrmgr_intr_test.2099023065
Directory /workspace/21.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.pwrmgr_intr_test.3237402388
Short name T672
Test name
Test status
Simulation time 33840099 ps
CPU time 0.61 seconds
Started Jul 24 05:06:57 PM PDT 24
Finished Jul 24 05:06:57 PM PDT 24
Peak memory 195400 kb
Host smart-be0b2a63-5cae-4164-b2f9-a2b394274e29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237402388 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.pwrmgr_intr_test.3237402388
Directory /workspace/22.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.pwrmgr_intr_test.3353785204
Short name T669
Test name
Test status
Simulation time 27268369 ps
CPU time 0.59 seconds
Started Jul 24 05:07:14 PM PDT 24
Finished Jul 24 05:07:15 PM PDT 24
Peak memory 195556 kb
Host smart-bf483452-ee83-4630-aba9-6aec244f0a7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353785204 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.pwrmgr_intr_test.3353785204
Directory /workspace/23.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.pwrmgr_intr_test.3727875924
Short name T641
Test name
Test status
Simulation time 34649164 ps
CPU time 0.56 seconds
Started Jul 24 05:06:55 PM PDT 24
Finished Jul 24 05:06:55 PM PDT 24
Peak memory 195448 kb
Host smart-c4d633a0-5032-4920-8b5e-8fd3f4014d1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727875924 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.pwrmgr_intr_test.3727875924
Directory /workspace/24.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.pwrmgr_intr_test.3253568537
Short name T704
Test name
Test status
Simulation time 31635535 ps
CPU time 0.6 seconds
Started Jul 24 05:06:54 PM PDT 24
Finished Jul 24 05:06:55 PM PDT 24
Peak memory 195476 kb
Host smart-1156c73f-1be9-440d-89d6-5be10b19d056
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253568537 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.pwrmgr_intr_test.3253568537
Directory /workspace/25.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.pwrmgr_intr_test.1234197548
Short name T698
Test name
Test status
Simulation time 39208901 ps
CPU time 0.56 seconds
Started Jul 24 05:06:53 PM PDT 24
Finished Jul 24 05:06:53 PM PDT 24
Peak memory 195516 kb
Host smart-dad06f1c-9a96-4e28-8d44-28204ab628c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234197548 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.pwrmgr_intr_test.1234197548
Directory /workspace/26.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.pwrmgr_intr_test.1994261775
Short name T694
Test name
Test status
Simulation time 27781379 ps
CPU time 0.6 seconds
Started Jul 24 05:06:56 PM PDT 24
Finished Jul 24 05:06:57 PM PDT 24
Peak memory 195492 kb
Host smart-b698c68a-0166-4927-a978-f4222b66905e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994261775 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.pwrmgr_intr_test.1994261775
Directory /workspace/27.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.pwrmgr_intr_test.2427820248
Short name T713
Test name
Test status
Simulation time 54818154 ps
CPU time 0.59 seconds
Started Jul 24 05:06:57 PM PDT 24
Finished Jul 24 05:06:58 PM PDT 24
Peak memory 195372 kb
Host smart-a92d766e-dd96-4327-807c-14cadf1f2ee8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427820248 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.pwrmgr_intr_test.2427820248
Directory /workspace/28.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.419650585
Short name T721
Test name
Test status
Simulation time 26391447 ps
CPU time 0.77 seconds
Started Jul 24 05:06:30 PM PDT 24
Finished Jul 24 05:06:31 PM PDT 24
Peak memory 197796 kb
Host smart-0d07e2b1-0a8c-461b-902b-9c68835351f6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419650585 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_aliasing.419650585
Directory /workspace/3.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.971981941
Short name T124
Test name
Test status
Simulation time 169482767 ps
CPU time 2.11 seconds
Started Jul 24 05:06:41 PM PDT 24
Finished Jul 24 05:06:44 PM PDT 24
Peak memory 195604 kb
Host smart-0287a344-88a3-458d-b0f1-bb94174272bf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971981941 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_bit_bash.971981941
Directory /workspace/3.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.2629400280
Short name T634
Test name
Test status
Simulation time 23912629 ps
CPU time 0.62 seconds
Started Jul 24 05:06:49 PM PDT 24
Finished Jul 24 05:06:55 PM PDT 24
Peak memory 195428 kb
Host smart-b72df8d0-8121-4bbf-b516-de7dea7cbf27
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629400280 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_hw_reset.2
629400280
Directory /workspace/3.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.3397308933
Short name T656
Test name
Test status
Simulation time 61401333 ps
CPU time 0.93 seconds
Started Jul 24 05:06:47 PM PDT 24
Finished Jul 24 05:06:49 PM PDT 24
Peak memory 196560 kb
Host smart-4777008f-5e9e-45a2-aacd-303c81310b72
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397308933 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.pwrmgr_csr_mem_rw_with_rand_reset.3397308933
Directory /workspace/3.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_rw.2062107261
Short name T684
Test name
Test status
Simulation time 60676672 ps
CPU time 0.63 seconds
Started Jul 24 05:07:04 PM PDT 24
Finished Jul 24 05:07:05 PM PDT 24
Peak memory 197608 kb
Host smart-7401728e-eeb9-4139-864e-5021e0308c24
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062107261 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_rw.2062107261
Directory /workspace/3.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_intr_test.3783957288
Short name T653
Test name
Test status
Simulation time 39466639 ps
CPU time 0.59 seconds
Started Jul 24 05:06:48 PM PDT 24
Finished Jul 24 05:06:49 PM PDT 24
Peak memory 195452 kb
Host smart-0aacff18-9bac-458c-a0da-a2db56247aa3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783957288 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_intr_test.3783957288
Directory /workspace/3.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.4085922628
Short name T639
Test name
Test status
Simulation time 30838509 ps
CPU time 0.79 seconds
Started Jul 24 05:07:04 PM PDT 24
Finished Jul 24 05:07:05 PM PDT 24
Peak memory 195500 kb
Host smart-6588871d-3de8-4261-9608-c79f0103523a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085922628 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sa
me_csr_outstanding.4085922628
Directory /workspace/3.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_tl_errors.2507847435
Short name T99
Test name
Test status
Simulation time 196946370 ps
CPU time 1.26 seconds
Started Jul 24 05:06:45 PM PDT 24
Finished Jul 24 05:06:47 PM PDT 24
Peak memory 196828 kb
Host smart-cb94390d-a6e8-4ccb-994b-c670273be0fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507847435 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_errors.2507847435
Directory /workspace/3.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.1735466962
Short name T89
Test name
Test status
Simulation time 263735749 ps
CPU time 1.75 seconds
Started Jul 24 05:06:37 PM PDT 24
Finished Jul 24 05:06:39 PM PDT 24
Peak memory 195808 kb
Host smart-0b1acb65-4171-48d2-8e06-0e435e1ebc1b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735466962 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_intg_err
.1735466962
Directory /workspace/3.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.pwrmgr_intr_test.879948741
Short name T658
Test name
Test status
Simulation time 32776470 ps
CPU time 0.58 seconds
Started Jul 24 05:07:05 PM PDT 24
Finished Jul 24 05:07:06 PM PDT 24
Peak memory 195480 kb
Host smart-80c6dc77-ca71-486c-bb7d-b75813135cc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879948741 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.pwrmgr_intr_test.879948741
Directory /workspace/30.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.pwrmgr_intr_test.1597018339
Short name T727
Test name
Test status
Simulation time 20787118 ps
CPU time 0.66 seconds
Started Jul 24 05:06:57 PM PDT 24
Finished Jul 24 05:06:58 PM PDT 24
Peak memory 195708 kb
Host smart-7a0a9e5d-7877-4f46-b9e0-c7300cf7a6a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597018339 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.pwrmgr_intr_test.1597018339
Directory /workspace/31.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.pwrmgr_intr_test.3140459506
Short name T677
Test name
Test status
Simulation time 18613444 ps
CPU time 0.65 seconds
Started Jul 24 05:06:59 PM PDT 24
Finished Jul 24 05:07:00 PM PDT 24
Peak memory 195476 kb
Host smart-e71512b0-0349-43e6-a123-bfefa1940a84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140459506 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.pwrmgr_intr_test.3140459506
Directory /workspace/32.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.pwrmgr_intr_test.1514142305
Short name T714
Test name
Test status
Simulation time 17597584 ps
CPU time 0.61 seconds
Started Jul 24 05:06:55 PM PDT 24
Finished Jul 24 05:06:56 PM PDT 24
Peak memory 195528 kb
Host smart-f5e04261-2f3c-4b36-84af-d489b26072dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514142305 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.pwrmgr_intr_test.1514142305
Directory /workspace/33.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.pwrmgr_intr_test.1965885721
Short name T80
Test name
Test status
Simulation time 17130562 ps
CPU time 0.63 seconds
Started Jul 24 05:07:02 PM PDT 24
Finished Jul 24 05:07:03 PM PDT 24
Peak memory 195476 kb
Host smart-21559ab4-8562-46bd-9074-c6ff7783be5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965885721 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.pwrmgr_intr_test.1965885721
Directory /workspace/34.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.pwrmgr_intr_test.145353239
Short name T184
Test name
Test status
Simulation time 19443926 ps
CPU time 0.63 seconds
Started Jul 24 05:07:06 PM PDT 24
Finished Jul 24 05:07:07 PM PDT 24
Peak memory 195516 kb
Host smart-3cb266a2-6b5e-4804-9b96-8af5e1f263de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145353239 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.pwrmgr_intr_test.145353239
Directory /workspace/35.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.pwrmgr_intr_test.810207917
Short name T186
Test name
Test status
Simulation time 43537103 ps
CPU time 0.61 seconds
Started Jul 24 05:07:01 PM PDT 24
Finished Jul 24 05:07:02 PM PDT 24
Peak memory 195452 kb
Host smart-12ef7913-a393-4081-a8da-71006dc527d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810207917 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.pwrmgr_intr_test.810207917
Directory /workspace/36.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.pwrmgr_intr_test.3690578151
Short name T78
Test name
Test status
Simulation time 45139734 ps
CPU time 0.62 seconds
Started Jul 24 05:07:04 PM PDT 24
Finished Jul 24 05:07:04 PM PDT 24
Peak memory 195536 kb
Host smart-9fa81ad4-a53c-429a-b204-cb715a759be7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690578151 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.pwrmgr_intr_test.3690578151
Directory /workspace/37.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.pwrmgr_intr_test.2132885255
Short name T633
Test name
Test status
Simulation time 19629163 ps
CPU time 0.67 seconds
Started Jul 24 05:07:07 PM PDT 24
Finished Jul 24 05:07:08 PM PDT 24
Peak memory 195512 kb
Host smart-96c4ac20-082f-4f5b-ad22-4183e68df88c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132885255 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.pwrmgr_intr_test.2132885255
Directory /workspace/38.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.pwrmgr_intr_test.940572088
Short name T185
Test name
Test status
Simulation time 42382568 ps
CPU time 0.63 seconds
Started Jul 24 05:06:53 PM PDT 24
Finished Jul 24 05:06:54 PM PDT 24
Peak memory 195400 kb
Host smart-c445dbcf-38b8-4279-8776-d1862a8de68a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940572088 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.pwrmgr_intr_test.940572088
Directory /workspace/39.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.925492466
Short name T642
Test name
Test status
Simulation time 33938193 ps
CPU time 0.8 seconds
Started Jul 24 05:06:50 PM PDT 24
Finished Jul 24 05:06:51 PM PDT 24
Peak memory 197744 kb
Host smart-82b61eda-7fb1-48ba-ad6b-8fc7d6e0ce3d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925492466 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_aliasing.925492466
Directory /workspace/4.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.110785170
Short name T646
Test name
Test status
Simulation time 173941476 ps
CPU time 1.68 seconds
Started Jul 24 05:06:56 PM PDT 24
Finished Jul 24 05:06:58 PM PDT 24
Peak memory 195696 kb
Host smart-52b775b1-3f05-4017-ae14-c6407651f3a1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110785170 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_bit_bash.110785170
Directory /workspace/4.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.1969806062
Short name T113
Test name
Test status
Simulation time 28741154 ps
CPU time 0.74 seconds
Started Jul 24 05:07:06 PM PDT 24
Finished Jul 24 05:07:07 PM PDT 24
Peak memory 198184 kb
Host smart-1bc466cd-932b-4384-a5f1-85858049a239
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969806062 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_hw_reset.1
969806062
Directory /workspace/4.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_rw.3386949572
Short name T675
Test name
Test status
Simulation time 48549803 ps
CPU time 0.63 seconds
Started Jul 24 05:06:53 PM PDT 24
Finished Jul 24 05:06:53 PM PDT 24
Peak memory 197764 kb
Host smart-c50e5ac9-eb53-4317-a9c5-84115746ef4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386949572 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_rw.3386949572
Directory /workspace/4.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_intr_test.1203764245
Short name T724
Test name
Test status
Simulation time 23676063 ps
CPU time 0.58 seconds
Started Jul 24 05:06:44 PM PDT 24
Finished Jul 24 05:06:44 PM PDT 24
Peak memory 195396 kb
Host smart-5e560267-247e-4ec8-94d8-66c87fd38532
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203764245 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_intr_test.1203764245
Directory /workspace/4.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.3729655928
Short name T676
Test name
Test status
Simulation time 51364797 ps
CPU time 0.7 seconds
Started Jul 24 05:06:44 PM PDT 24
Finished Jul 24 05:06:45 PM PDT 24
Peak memory 197948 kb
Host smart-75f675f5-936b-4016-b043-bfb7502b4fcc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729655928 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sa
me_csr_outstanding.3729655928
Directory /workspace/4.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_tl_errors.3441797522
Short name T23
Test name
Test status
Simulation time 110962930 ps
CPU time 2.06 seconds
Started Jul 24 05:06:44 PM PDT 24
Finished Jul 24 05:06:46 PM PDT 24
Peak memory 197848 kb
Host smart-68cf66cd-bab4-48bb-8743-9a0ebd91e4db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441797522 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_errors.3441797522
Directory /workspace/4.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.2378618836
Short name T144
Test name
Test status
Simulation time 236855534 ps
CPU time 1 seconds
Started Jul 24 05:06:48 PM PDT 24
Finished Jul 24 05:06:50 PM PDT 24
Peak memory 200752 kb
Host smart-1216f627-bbf9-482a-9a12-5d3f58485506
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378618836 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_intg_err
.2378618836
Directory /workspace/4.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.pwrmgr_intr_test.1831683960
Short name T689
Test name
Test status
Simulation time 16600732 ps
CPU time 0.6 seconds
Started Jul 24 05:07:25 PM PDT 24
Finished Jul 24 05:07:26 PM PDT 24
Peak memory 195480 kb
Host smart-70984b96-e015-43b7-89db-d81c3a3a00f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831683960 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.pwrmgr_intr_test.1831683960
Directory /workspace/40.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.pwrmgr_intr_test.792619858
Short name T725
Test name
Test status
Simulation time 19810872 ps
CPU time 0.61 seconds
Started Jul 24 05:07:20 PM PDT 24
Finished Jul 24 05:07:21 PM PDT 24
Peak memory 195476 kb
Host smart-46aa8a9f-359c-4a55-8b68-7fcb08ff8f73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792619858 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.pwrmgr_intr_test.792619858
Directory /workspace/41.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.pwrmgr_intr_test.1394344060
Short name T638
Test name
Test status
Simulation time 17093875 ps
CPU time 0.59 seconds
Started Jul 24 05:07:16 PM PDT 24
Finished Jul 24 05:07:17 PM PDT 24
Peak memory 195512 kb
Host smart-daddb7a0-3f0e-4010-8478-6763d66d52b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394344060 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.pwrmgr_intr_test.1394344060
Directory /workspace/42.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.pwrmgr_intr_test.2142499313
Short name T632
Test name
Test status
Simulation time 16704055 ps
CPU time 0.64 seconds
Started Jul 24 05:07:01 PM PDT 24
Finished Jul 24 05:07:02 PM PDT 24
Peak memory 195372 kb
Host smart-de72dbe7-d12c-4928-b996-0cb4814a15a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142499313 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.pwrmgr_intr_test.2142499313
Directory /workspace/43.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.pwrmgr_intr_test.3085437302
Short name T733
Test name
Test status
Simulation time 18310686 ps
CPU time 0.63 seconds
Started Jul 24 05:06:59 PM PDT 24
Finished Jul 24 05:07:00 PM PDT 24
Peak memory 195508 kb
Host smart-52cb679d-a6b2-4975-a244-8fcc3e7be45d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085437302 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.pwrmgr_intr_test.3085437302
Directory /workspace/44.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.pwrmgr_intr_test.1583385197
Short name T629
Test name
Test status
Simulation time 32874588 ps
CPU time 0.61 seconds
Started Jul 24 05:07:05 PM PDT 24
Finished Jul 24 05:07:06 PM PDT 24
Peak memory 195476 kb
Host smart-b411bf79-6e4a-4bbb-a6e7-b06fcf4848e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583385197 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.pwrmgr_intr_test.1583385197
Directory /workspace/45.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.pwrmgr_intr_test.662947829
Short name T732
Test name
Test status
Simulation time 91717102 ps
CPU time 0.65 seconds
Started Jul 24 05:07:03 PM PDT 24
Finished Jul 24 05:07:04 PM PDT 24
Peak memory 195516 kb
Host smart-c3e31729-23af-46f4-b547-d740768396f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662947829 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.pwrmgr_intr_test.662947829
Directory /workspace/46.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.pwrmgr_intr_test.789248711
Short name T649
Test name
Test status
Simulation time 19454164 ps
CPU time 0.65 seconds
Started Jul 24 05:06:56 PM PDT 24
Finished Jul 24 05:06:57 PM PDT 24
Peak memory 195708 kb
Host smart-2405e54f-dbb3-4428-800c-ad510a55548f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789248711 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.pwrmgr_intr_test.789248711
Directory /workspace/47.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.pwrmgr_intr_test.3017678292
Short name T661
Test name
Test status
Simulation time 18530174 ps
CPU time 0.62 seconds
Started Jul 24 05:07:08 PM PDT 24
Finished Jul 24 05:07:09 PM PDT 24
Peak memory 195452 kb
Host smart-ad2f4d5a-e46a-49c5-ae99-747fb28940c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017678292 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.pwrmgr_intr_test.3017678292
Directory /workspace/48.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.pwrmgr_intr_test.3653585950
Short name T700
Test name
Test status
Simulation time 30858360 ps
CPU time 0.62 seconds
Started Jul 24 05:07:28 PM PDT 24
Finished Jul 24 05:07:28 PM PDT 24
Peak memory 195352 kb
Host smart-737f98ba-6968-4a95-a3e5-2ebe2b075619
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653585950 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.pwrmgr_intr_test.3653585950
Directory /workspace/49.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.1874773242
Short name T702
Test name
Test status
Simulation time 57800775 ps
CPU time 0.94 seconds
Started Jul 24 05:06:50 PM PDT 24
Finished Jul 24 05:06:51 PM PDT 24
Peak memory 200976 kb
Host smart-4b75c3a1-4ce8-43f7-bc7c-7cdf66dbc981
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874773242 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.pwrmgr_csr_mem_rw_with_rand_reset.1874773242
Directory /workspace/5.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_csr_rw.1446212245
Short name T657
Test name
Test status
Simulation time 18484381 ps
CPU time 0.64 seconds
Started Jul 24 05:07:01 PM PDT 24
Finished Jul 24 05:07:02 PM PDT 24
Peak memory 198772 kb
Host smart-7c494c09-19a9-45c9-b369-3d3494092b05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446212245 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_csr_rw.1446212245
Directory /workspace/5.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_intr_test.2480382934
Short name T703
Test name
Test status
Simulation time 38213637 ps
CPU time 0.58 seconds
Started Jul 24 05:06:53 PM PDT 24
Finished Jul 24 05:06:54 PM PDT 24
Peak memory 195528 kb
Host smart-14654428-40a6-4d34-88df-36c6e2304ffb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480382934 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_intr_test.2480382934
Directory /workspace/5.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.2174481152
Short name T716
Test name
Test status
Simulation time 168045915 ps
CPU time 0.77 seconds
Started Jul 24 05:06:55 PM PDT 24
Finished Jul 24 05:06:56 PM PDT 24
Peak memory 198760 kb
Host smart-f91da4e4-e70b-4d63-b43a-80c0fe1a26e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174481152 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sa
me_csr_outstanding.2174481152
Directory /workspace/5.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_tl_errors.599992876
Short name T61
Test name
Test status
Simulation time 110250211 ps
CPU time 2.02 seconds
Started Jul 24 05:06:58 PM PDT 24
Finished Jul 24 05:07:00 PM PDT 24
Peak memory 201152 kb
Host smart-9cbb0a0e-bc19-4546-8651-1adb1e5fba56
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599992876 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_errors.599992876
Directory /workspace/5.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.1044503820
Short name T64
Test name
Test status
Simulation time 283222111 ps
CPU time 1.67 seconds
Started Jul 24 05:06:47 PM PDT 24
Finished Jul 24 05:06:49 PM PDT 24
Peak memory 201120 kb
Host smart-c9d0fb40-4162-497c-a88b-97ffea82c682
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044503820 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_intg_err
.1044503820
Directory /workspace/5.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.2633439613
Short name T731
Test name
Test status
Simulation time 60531799 ps
CPU time 0.83 seconds
Started Jul 24 05:06:46 PM PDT 24
Finished Jul 24 05:06:47 PM PDT 24
Peak memory 200960 kb
Host smart-587f463c-89e6-45f7-b2fe-dcd3e1c14f14
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633439613 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.pwrmgr_csr_mem_rw_with_rand_reset.2633439613
Directory /workspace/6.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_csr_rw.433029127
Short name T105
Test name
Test status
Simulation time 17899926 ps
CPU time 0.65 seconds
Started Jul 24 05:06:52 PM PDT 24
Finished Jul 24 05:06:53 PM PDT 24
Peak memory 196788 kb
Host smart-c5be16d6-f43d-4373-8904-0ec27886f16e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433029127 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_csr_rw.433029127
Directory /workspace/6.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_intr_test.3211410073
Short name T652
Test name
Test status
Simulation time 18858343 ps
CPU time 0.61 seconds
Started Jul 24 05:06:47 PM PDT 24
Finished Jul 24 05:06:49 PM PDT 24
Peak memory 195404 kb
Host smart-4e70252c-0c40-401a-b5ec-be13019e5f85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211410073 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_intr_test.3211410073
Directory /workspace/6.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.346360786
Short name T663
Test name
Test status
Simulation time 64737441 ps
CPU time 0.74 seconds
Started Jul 24 05:06:53 PM PDT 24
Finished Jul 24 05:06:54 PM PDT 24
Peak memory 197840 kb
Host smart-3def71a5-5f6e-4ffe-ad20-2c2685e57d80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346360786 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sam
e_csr_outstanding.346360786
Directory /workspace/6.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_tl_errors.3517357818
Short name T687
Test name
Test status
Simulation time 771847261 ps
CPU time 2.18 seconds
Started Jul 24 05:06:57 PM PDT 24
Finished Jul 24 05:06:59 PM PDT 24
Peak memory 196812 kb
Host smart-3e16bb06-24b4-44d5-b9cd-faa2484e8ab9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517357818 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_errors.3517357818
Directory /workspace/6.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.664863909
Short name T734
Test name
Test status
Simulation time 1162113988 ps
CPU time 1.61 seconds
Started Jul 24 05:06:45 PM PDT 24
Finished Jul 24 05:06:47 PM PDT 24
Peak memory 195792 kb
Host smart-f26c54cd-9918-4249-b0a4-e11f64381928
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664863909 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_intg_err.
664863909
Directory /workspace/6.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.4076601321
Short name T86
Test name
Test status
Simulation time 40364286 ps
CPU time 0.83 seconds
Started Jul 24 05:06:44 PM PDT 24
Finished Jul 24 05:06:45 PM PDT 24
Peak memory 195548 kb
Host smart-f913e829-14c0-4a1c-a1ac-8ead3e3a99a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076601321 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.pwrmgr_csr_mem_rw_with_rand_reset.4076601321
Directory /workspace/7.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_csr_rw.657992189
Short name T108
Test name
Test status
Simulation time 44442420 ps
CPU time 0.65 seconds
Started Jul 24 05:06:49 PM PDT 24
Finished Jul 24 05:06:50 PM PDT 24
Peak memory 195568 kb
Host smart-df6621d8-9846-4aee-bc18-a7ba0eae99ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657992189 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_csr_rw.657992189
Directory /workspace/7.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_intr_test.3916757168
Short name T635
Test name
Test status
Simulation time 19614307 ps
CPU time 0.6 seconds
Started Jul 24 05:06:57 PM PDT 24
Finished Jul 24 05:06:58 PM PDT 24
Peak memory 195476 kb
Host smart-ccd3b33e-ceb4-4f40-bbd2-834f1f5cbc13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916757168 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_intr_test.3916757168
Directory /workspace/7.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.253746841
Short name T680
Test name
Test status
Simulation time 24279596 ps
CPU time 0.68 seconds
Started Jul 24 05:07:14 PM PDT 24
Finished Jul 24 05:07:15 PM PDT 24
Peak memory 198580 kb
Host smart-b4200915-fd25-4a60-aac5-12321d64c633
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253746841 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sam
e_csr_outstanding.253746841
Directory /workspace/7.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_tl_errors.2361425294
Short name T709
Test name
Test status
Simulation time 81745091 ps
CPU time 2.09 seconds
Started Jul 24 05:06:48 PM PDT 24
Finished Jul 24 05:06:51 PM PDT 24
Peak memory 196972 kb
Host smart-3ec46c1f-6c36-4800-95ee-069517fa7917
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361425294 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_errors.2361425294
Directory /workspace/7.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.1488236274
Short name T63
Test name
Test status
Simulation time 432246556 ps
CPU time 1.6 seconds
Started Jul 24 05:06:58 PM PDT 24
Finished Jul 24 05:07:00 PM PDT 24
Peak memory 201104 kb
Host smart-1ea9cf7f-968c-40b9-8e7e-ea6dedad7f4e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488236274 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_intg_err
.1488236274
Directory /workspace/7.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.906179184
Short name T123
Test name
Test status
Simulation time 67593954 ps
CPU time 0.86 seconds
Started Jul 24 05:06:52 PM PDT 24
Finished Jul 24 05:06:53 PM PDT 24
Peak memory 195580 kb
Host smart-3237cf54-44ba-4ba1-934f-f128ce02adce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906179184 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.pwrmgr_csr_mem_rw_with_rand_reset.906179184
Directory /workspace/8.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_csr_rw.895719985
Short name T112
Test name
Test status
Simulation time 29884616 ps
CPU time 0.61 seconds
Started Jul 24 05:06:43 PM PDT 24
Finished Jul 24 05:06:44 PM PDT 24
Peak memory 195400 kb
Host smart-fac3c786-245e-42f6-9918-1cb80e1c580f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895719985 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_csr_rw.895719985
Directory /workspace/8.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_intr_test.2057116993
Short name T654
Test name
Test status
Simulation time 22078658 ps
CPU time 0.63 seconds
Started Jul 24 05:06:54 PM PDT 24
Finished Jul 24 05:06:55 PM PDT 24
Peak memory 195360 kb
Host smart-a7fc2b34-25e2-4bfa-b6dc-dff7c1b5e9ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057116993 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_intr_test.2057116993
Directory /workspace/8.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.2138979679
Short name T650
Test name
Test status
Simulation time 71022653 ps
CPU time 0.81 seconds
Started Jul 24 05:06:51 PM PDT 24
Finished Jul 24 05:06:52 PM PDT 24
Peak memory 198768 kb
Host smart-b609239a-7863-4c5b-82c3-3ec3f4e5531f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138979679 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sa
me_csr_outstanding.2138979679
Directory /workspace/8.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_tl_errors.4293701286
Short name T674
Test name
Test status
Simulation time 47397646 ps
CPU time 1.16 seconds
Started Jul 24 05:06:50 PM PDT 24
Finished Jul 24 05:06:52 PM PDT 24
Peak memory 197000 kb
Host smart-093ff44a-ce27-4810-a2b9-8405abaa611b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293701286 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_errors.4293701286
Directory /workspace/8.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.2124678852
Short name T90
Test name
Test status
Simulation time 156573279 ps
CPU time 1.11 seconds
Started Jul 24 05:06:53 PM PDT 24
Finished Jul 24 05:06:59 PM PDT 24
Peak memory 200832 kb
Host smart-34fc8d9b-b5d9-402d-8c48-c137140639b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124678852 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_intg_err
.2124678852
Directory /workspace/8.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.1875801667
Short name T688
Test name
Test status
Simulation time 212757017 ps
CPU time 1.64 seconds
Started Jul 24 05:06:56 PM PDT 24
Finished Jul 24 05:06:58 PM PDT 24
Peak memory 199504 kb
Host smart-8f47c172-9fe9-46df-9a4f-a8fa7cce0e36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875801667 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.pwrmgr_csr_mem_rw_with_rand_reset.1875801667
Directory /workspace/9.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_csr_rw.4225558257
Short name T735
Test name
Test status
Simulation time 27727249 ps
CPU time 0.64 seconds
Started Jul 24 05:06:57 PM PDT 24
Finished Jul 24 05:06:58 PM PDT 24
Peak memory 195464 kb
Host smart-e7192ea3-5e45-4254-80e7-b0f2025a225e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225558257 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_csr_rw.4225558257
Directory /workspace/9.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_intr_test.4182804057
Short name T710
Test name
Test status
Simulation time 53598976 ps
CPU time 0.67 seconds
Started Jul 24 05:06:48 PM PDT 24
Finished Jul 24 05:06:49 PM PDT 24
Peak memory 195452 kb
Host smart-4d36d237-21bf-489b-8fb2-8dbe6ce056f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182804057 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_intr_test.4182804057
Directory /workspace/9.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.2340576877
Short name T125
Test name
Test status
Simulation time 543296823 ps
CPU time 0.95 seconds
Started Jul 24 05:06:47 PM PDT 24
Finished Jul 24 05:06:48 PM PDT 24
Peak memory 199100 kb
Host smart-380af829-6814-4015-a0f3-6b400666772f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340576877 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sa
me_csr_outstanding.2340576877
Directory /workspace/9.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_tl_errors.1002869184
Short name T718
Test name
Test status
Simulation time 48410431 ps
CPU time 2.16 seconds
Started Jul 24 05:06:48 PM PDT 24
Finished Jul 24 05:06:51 PM PDT 24
Peak memory 197188 kb
Host smart-1ec8600e-f2b5-4c4a-b68e-b7e6f38f6402
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002869184 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_errors.1002869184
Directory /workspace/9.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.184867300
Short name T145
Test name
Test status
Simulation time 172555536 ps
CPU time 1.62 seconds
Started Jul 24 05:06:48 PM PDT 24
Finished Jul 24 05:06:50 PM PDT 24
Peak memory 200892 kb
Host smart-8da4523e-1c0e-4efc-80bb-30d6b5f8a01c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184867300 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_intg_err.
184867300
Directory /workspace/9.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.pwrmgr_disable_rom_integrity_check.2160404087
Short name T514
Test name
Test status
Simulation time 66948369 ps
CPU time 0.83 seconds
Started Jul 24 05:07:00 PM PDT 24
Finished Jul 24 05:07:01 PM PDT 24
Peak memory 199000 kb
Host smart-26a4487e-193a-4602-a0c2-383a1f046cd1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160404087 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_disa
ble_rom_integrity_check.2160404087
Directory /workspace/0.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/0.pwrmgr_esc_clk_rst_malfunc.1528221131
Short name T541
Test name
Test status
Simulation time 29500157 ps
CPU time 0.61 seconds
Started Jul 24 05:07:03 PM PDT 24
Finished Jul 24 05:07:04 PM PDT 24
Peak memory 197872 kb
Host smart-e4e783ff-fdf6-4028-9216-b83e843e826e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528221131 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_esc_clk_rst_
malfunc.1528221131
Directory /workspace/0.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/0.pwrmgr_escalation_timeout.2694017312
Short name T355
Test name
Test status
Simulation time 1162828587 ps
CPU time 0.98 seconds
Started Jul 24 05:07:17 PM PDT 24
Finished Jul 24 05:07:19 PM PDT 24
Peak memory 198596 kb
Host smart-c2a55942-cf8f-46d8-9133-7e023bc1e2d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694017312 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_escalation_timeout.2694017312
Directory /workspace/0.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/0.pwrmgr_global_esc.3474657040
Short name T324
Test name
Test status
Simulation time 115416470 ps
CPU time 0.62 seconds
Started Jul 24 05:07:01 PM PDT 24
Finished Jul 24 05:07:01 PM PDT 24
Peak memory 198644 kb
Host smart-7adca558-6fd6-45a0-9f8d-9892bd4a751c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474657040 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_global_esc.3474657040
Directory /workspace/0.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/0.pwrmgr_reset.446731767
Short name T404
Test name
Test status
Simulation time 62576987 ps
CPU time 0.67 seconds
Started Jul 24 05:07:00 PM PDT 24
Finished Jul 24 05:07:01 PM PDT 24
Peak memory 198752 kb
Host smart-65e30013-4a26-4ff5-9b7a-790037e5a0f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446731767 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset.446731767
Directory /workspace/0.pwrmgr_reset/latest

Test location /workspace/coverage/default/0.pwrmgr_reset_invalid.1996527686
Short name T348
Test name
Test status
Simulation time 120253869 ps
CPU time 0.88 seconds
Started Jul 24 05:07:14 PM PDT 24
Finished Jul 24 05:07:16 PM PDT 24
Peak memory 209928 kb
Host smart-6497ca7f-2506-4912-a80a-dd84c3cb59f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996527686 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset_invalid.1996527686
Directory /workspace/0.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm_ctrl_config_regwen.1588523330
Short name T620
Test name
Test status
Simulation time 38870816 ps
CPU time 0.73 seconds
Started Jul 24 05:07:22 PM PDT 24
Finished Jul 24 05:07:23 PM PDT 24
Peak memory 199140 kb
Host smart-4ffc2947-d3c0-4e43-9b9a-1b7e42f3dc1a
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588523330 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_c
m_ctrl_config_regwen.1588523330
Directory /workspace/0.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm_rstmgr_intersig_mubi.3749277256
Short name T437
Test name
Test status
Simulation time 58876880 ps
CPU time 0.75 seconds
Started Jul 24 05:07:07 PM PDT 24
Finished Jul 24 05:07:12 PM PDT 24
Peak memory 198552 kb
Host smart-abddb20b-3887-46c7-a546-21ffea12eeab
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749277256 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_rstmgr_intersig_
mubi.3749277256
Directory /workspace/0.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/0.pwrmgr_wakeup.3232553029
Short name T208
Test name
Test status
Simulation time 57977046 ps
CPU time 0.62 seconds
Started Jul 24 05:07:04 PM PDT 24
Finished Jul 24 05:07:05 PM PDT 24
Peak memory 198748 kb
Host smart-f18e0f36-915c-423c-99a8-574ba1f89741
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232553029 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_wakeup.3232553029
Directory /workspace/0.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/1.pwrmgr_aborted_low_power.3492356195
Short name T516
Test name
Test status
Simulation time 23391398 ps
CPU time 0.66 seconds
Started Jul 24 05:07:00 PM PDT 24
Finished Jul 24 05:07:01 PM PDT 24
Peak memory 199216 kb
Host smart-efa5d77b-7c30-40c1-b58e-9b2d6b414ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492356195 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_aborted_low_power.3492356195
Directory /workspace/1.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/1.pwrmgr_disable_rom_integrity_check.367535452
Short name T139
Test name
Test status
Simulation time 90041352 ps
CPU time 0.66 seconds
Started Jul 24 05:07:06 PM PDT 24
Finished Jul 24 05:07:07 PM PDT 24
Peak memory 198748 kb
Host smart-1b1a1319-8ea3-45e3-8391-16d76679cb55
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367535452 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_disab
le_rom_integrity_check.367535452
Directory /workspace/1.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/1.pwrmgr_esc_clk_rst_malfunc.1017519938
Short name T488
Test name
Test status
Simulation time 31840537 ps
CPU time 0.6 seconds
Started Jul 24 05:07:20 PM PDT 24
Finished Jul 24 05:07:21 PM PDT 24
Peak memory 198556 kb
Host smart-bcd892da-c36f-4242-bbaf-b5ffc9f0a2b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017519938 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_esc_clk_rst_
malfunc.1017519938
Directory /workspace/1.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/1.pwrmgr_escalation_timeout.1771976476
Short name T464
Test name
Test status
Simulation time 891219320 ps
CPU time 0.95 seconds
Started Jul 24 05:07:26 PM PDT 24
Finished Jul 24 05:07:27 PM PDT 24
Peak memory 198608 kb
Host smart-1edbc8c6-bf8e-49c0-92c0-fcc938e4fa63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771976476 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_escalation_timeout.1771976476
Directory /workspace/1.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/1.pwrmgr_glitch.4251783249
Short name T387
Test name
Test status
Simulation time 52646769 ps
CPU time 0.63 seconds
Started Jul 24 05:07:22 PM PDT 24
Finished Jul 24 05:07:23 PM PDT 24
Peak memory 198708 kb
Host smart-dbf4e787-b91a-47c7-b68c-0df0ffa480ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251783249 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_glitch.4251783249
Directory /workspace/1.pwrmgr_glitch/latest

Test location /workspace/coverage/default/1.pwrmgr_global_esc.4187882190
Short name T613
Test name
Test status
Simulation time 49447682 ps
CPU time 0.69 seconds
Started Jul 24 05:07:07 PM PDT 24
Finished Jul 24 05:07:08 PM PDT 24
Peak memory 198936 kb
Host smart-9b993215-cfbb-41cb-b687-32f9b6ff2125
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187882190 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_global_esc.4187882190
Directory /workspace/1.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/1.pwrmgr_reset.7528045
Short name T372
Test name
Test status
Simulation time 44168707 ps
CPU time 0.72 seconds
Started Jul 24 05:07:02 PM PDT 24
Finished Jul 24 05:07:03 PM PDT 24
Peak memory 198912 kb
Host smart-f42b8233-0158-4627-b8a5-3db2e4841f57
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7528045 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset.7528045
Directory /workspace/1.pwrmgr_reset/latest

Test location /workspace/coverage/default/1.pwrmgr_reset_invalid.468210214
Short name T41
Test name
Test status
Simulation time 174496976 ps
CPU time 0.75 seconds
Started Jul 24 05:07:29 PM PDT 24
Finished Jul 24 05:07:29 PM PDT 24
Peak memory 209896 kb
Host smart-86be140b-9af2-4891-b9a6-e6d9c45c93aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468210214 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset_invalid.468210214
Directory /workspace/1.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm_rstmgr_intersig_mubi.2568138525
Short name T247
Test name
Test status
Simulation time 133479163 ps
CPU time 0.82 seconds
Started Jul 24 05:07:18 PM PDT 24
Finished Jul 24 05:07:19 PM PDT 24
Peak memory 199424 kb
Host smart-ebbc7a8c-d5ef-4466-a2a8-36d16d399af7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568138525 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2568138525
Directory /workspace/1.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/1.pwrmgr_smoke.2537257900
Short name T282
Test name
Test status
Simulation time 41308913 ps
CPU time 0.64 seconds
Started Jul 24 05:07:23 PM PDT 24
Finished Jul 24 05:07:24 PM PDT 24
Peak memory 199092 kb
Host smart-1a698c4d-e709-4592-aeb5-f036eaeaa7fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537257900 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_smoke.2537257900
Directory /workspace/1.pwrmgr_smoke/latest

Test location /workspace/coverage/default/10.pwrmgr_aborted_low_power.3228334634
Short name T527
Test name
Test status
Simulation time 59053590 ps
CPU time 0.83 seconds
Started Jul 24 05:07:31 PM PDT 24
Finished Jul 24 05:07:32 PM PDT 24
Peak memory 200588 kb
Host smart-32e5ae59-604f-43ec-adb1-74c9c99be0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228334634 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_aborted_low_power.3228334634
Directory /workspace/10.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/10.pwrmgr_escalation_timeout.3220466511
Short name T445
Test name
Test status
Simulation time 337622099 ps
CPU time 0.97 seconds
Started Jul 24 05:07:55 PM PDT 24
Finished Jul 24 05:08:01 PM PDT 24
Peak memory 198672 kb
Host smart-432364c1-b6ed-4b4f-9db7-32032bb742bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220466511 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_escalation_timeout.3220466511
Directory /workspace/10.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/10.pwrmgr_glitch.3302615151
Short name T474
Test name
Test status
Simulation time 60300578 ps
CPU time 0.66 seconds
Started Jul 24 05:07:42 PM PDT 24
Finished Jul 24 05:07:44 PM PDT 24
Peak memory 198588 kb
Host smart-a953dfe7-23e6-4e11-baa6-65a85a8078b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302615151 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_glitch.3302615151
Directory /workspace/10.pwrmgr_glitch/latest

Test location /workspace/coverage/default/10.pwrmgr_global_esc.2688615564
Short name T375
Test name
Test status
Simulation time 75933290 ps
CPU time 0.58 seconds
Started Jul 24 05:07:32 PM PDT 24
Finished Jul 24 05:07:33 PM PDT 24
Peak memory 198660 kb
Host smart-78fd25e1-3d52-449e-b41b-0f2dc150d238
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688615564 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_global_esc.2688615564
Directory /workspace/10.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/10.pwrmgr_lowpower_invalid.3287620549
Short name T51
Test name
Test status
Simulation time 37725937 ps
CPU time 0.71 seconds
Started Jul 24 05:07:42 PM PDT 24
Finished Jul 24 05:07:48 PM PDT 24
Peak memory 201892 kb
Host smart-51dccd37-ec76-42e1-b09a-15da93a425c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287620549 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_lowpower_inval
id.3287620549
Directory /workspace/10.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/10.pwrmgr_lowpower_wakeup_race.526989167
Short name T207
Test name
Test status
Simulation time 91608327 ps
CPU time 0.67 seconds
Started Jul 24 05:07:44 PM PDT 24
Finished Jul 24 05:07:45 PM PDT 24
Peak memory 198800 kb
Host smart-f3b5f0db-d4b8-437b-bcce-8f805b44f514
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526989167 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_lowpower_wa
keup_race.526989167
Directory /workspace/10.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/10.pwrmgr_reset.1402910194
Short name T37
Test name
Test status
Simulation time 54048404 ps
CPU time 0.77 seconds
Started Jul 24 05:07:36 PM PDT 24
Finished Jul 24 05:07:37 PM PDT 24
Peak memory 198948 kb
Host smart-a029c0cd-fe56-4b14-bd73-2e6fc0abd48b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402910194 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset.1402910194
Directory /workspace/10.pwrmgr_reset/latest

Test location /workspace/coverage/default/10.pwrmgr_reset_invalid.3370488549
Short name T44
Test name
Test status
Simulation time 155594605 ps
CPU time 0.81 seconds
Started Jul 24 05:07:39 PM PDT 24
Finished Jul 24 05:07:40 PM PDT 24
Peak memory 210036 kb
Host smart-2d23dc0e-2b56-450e-a9cb-af02bdc3762b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370488549 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset_invalid.3370488549
Directory /workspace/10.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/10.pwrmgr_sec_cm_rstmgr_intersig_mubi.3487483719
Short name T399
Test name
Test status
Simulation time 63201610 ps
CPU time 0.68 seconds
Started Jul 24 05:07:48 PM PDT 24
Finished Jul 24 05:07:49 PM PDT 24
Peak memory 198656 kb
Host smart-058404e4-87ad-489e-a4ae-9485acf6272d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487483719 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3487483719
Directory /workspace/10.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/10.pwrmgr_smoke.2249966234
Short name T227
Test name
Test status
Simulation time 28450819 ps
CPU time 0.69 seconds
Started Jul 24 05:07:35 PM PDT 24
Finished Jul 24 05:07:36 PM PDT 24
Peak memory 199920 kb
Host smart-44e3d043-dc75-4354-880d-34b0aae31098
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249966234 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_smoke.2249966234
Directory /workspace/10.pwrmgr_smoke/latest

Test location /workspace/coverage/default/11.pwrmgr_aborted_low_power.3386908877
Short name T444
Test name
Test status
Simulation time 65768871 ps
CPU time 0.78 seconds
Started Jul 24 05:07:41 PM PDT 24
Finished Jul 24 05:07:42 PM PDT 24
Peak memory 200624 kb
Host smart-22680864-3358-454b-83db-40963f3d7ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386908877 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_aborted_low_power.3386908877
Directory /workspace/11.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/11.pwrmgr_disable_rom_integrity_check.665020358
Short name T195
Test name
Test status
Simulation time 66643684 ps
CPU time 0.79 seconds
Started Jul 24 05:07:42 PM PDT 24
Finished Jul 24 05:07:44 PM PDT 24
Peak memory 198908 kb
Host smart-c3940b01-c7e8-4173-8516-d3c19b0b3b59
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665020358 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_disa
ble_rom_integrity_check.665020358
Directory /workspace/11.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/11.pwrmgr_escalation_timeout.4190073142
Short name T428
Test name
Test status
Simulation time 163658863 ps
CPU time 0.99 seconds
Started Jul 24 05:07:41 PM PDT 24
Finished Jul 24 05:07:43 PM PDT 24
Peak memory 198676 kb
Host smart-2136d00e-521b-4db2-b5b3-6f72e6055376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190073142 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_escalation_timeout.4190073142
Directory /workspace/11.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/11.pwrmgr_glitch.2259205269
Short name T454
Test name
Test status
Simulation time 45430302 ps
CPU time 0.61 seconds
Started Jul 24 05:07:41 PM PDT 24
Finished Jul 24 05:07:42 PM PDT 24
Peak memory 198624 kb
Host smart-4595a885-7fc0-4033-9e48-f858332f8ee3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259205269 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_glitch.2259205269
Directory /workspace/11.pwrmgr_glitch/latest

Test location /workspace/coverage/default/11.pwrmgr_global_esc.4023514940
Short name T320
Test name
Test status
Simulation time 32236283 ps
CPU time 0.62 seconds
Started Jul 24 05:07:35 PM PDT 24
Finished Jul 24 05:07:36 PM PDT 24
Peak memory 198488 kb
Host smart-1b84b486-8667-4aaf-a3b6-7b8507cc72ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023514940 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_global_esc.4023514940
Directory /workspace/11.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/11.pwrmgr_reset.2801745661
Short name T269
Test name
Test status
Simulation time 47130394 ps
CPU time 0.78 seconds
Started Jul 24 05:07:50 PM PDT 24
Finished Jul 24 05:07:51 PM PDT 24
Peak memory 199620 kb
Host smart-25419117-e934-4fdf-bc9d-fade6999aab3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801745661 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset.2801745661
Directory /workspace/11.pwrmgr_reset/latest

Test location /workspace/coverage/default/11.pwrmgr_reset_invalid.3420770823
Short name T459
Test name
Test status
Simulation time 124550642 ps
CPU time 0.87 seconds
Started Jul 24 05:07:54 PM PDT 24
Finished Jul 24 05:07:56 PM PDT 24
Peak memory 210072 kb
Host smart-9738b779-41e7-49a4-a137-bb0ad170d91e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420770823 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset_invalid.3420770823
Directory /workspace/11.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/11.pwrmgr_sec_cm_rstmgr_intersig_mubi.1454790541
Short name T458
Test name
Test status
Simulation time 55094715 ps
CPU time 0.78 seconds
Started Jul 24 05:07:39 PM PDT 24
Finished Jul 24 05:07:40 PM PDT 24
Peak memory 198552 kb
Host smart-f23da781-10cf-479d-b9f6-00b2e9dafce9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454790541 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1454790541
Directory /workspace/11.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/11.pwrmgr_smoke.2948666696
Short name T609
Test name
Test status
Simulation time 33121188 ps
CPU time 0.68 seconds
Started Jul 24 05:07:39 PM PDT 24
Finished Jul 24 05:07:40 PM PDT 24
Peak memory 199844 kb
Host smart-c0ecf2e5-121e-4413-b051-72ecac646087
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948666696 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_smoke.2948666696
Directory /workspace/11.pwrmgr_smoke/latest

Test location /workspace/coverage/default/12.pwrmgr_aborted_low_power.3052966120
Short name T16
Test name
Test status
Simulation time 489220314 ps
CPU time 0.81 seconds
Started Jul 24 05:07:41 PM PDT 24
Finished Jul 24 05:07:42 PM PDT 24
Peak memory 200520 kb
Host smart-d1a14b1c-0ee4-45b0-b520-2e17465abffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052966120 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_aborted_low_power.3052966120
Directory /workspace/12.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/12.pwrmgr_disable_rom_integrity_check.1764835370
Short name T194
Test name
Test status
Simulation time 61003478 ps
CPU time 0.81 seconds
Started Jul 24 05:08:05 PM PDT 24
Finished Jul 24 05:08:06 PM PDT 24
Peak memory 199044 kb
Host smart-aa34800a-3c37-49a2-9b40-1c5260013361
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764835370 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_dis
able_rom_integrity_check.1764835370
Directory /workspace/12.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/12.pwrmgr_esc_clk_rst_malfunc.3130696350
Short name T468
Test name
Test status
Simulation time 56057971 ps
CPU time 0.63 seconds
Started Jul 24 05:07:43 PM PDT 24
Finished Jul 24 05:07:44 PM PDT 24
Peak memory 198428 kb
Host smart-13824fb6-35f1-4c5f-a05a-5c69ceafb00a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130696350 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_esc_clk_rst
_malfunc.3130696350
Directory /workspace/12.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/12.pwrmgr_escalation_timeout.3576905614
Short name T535
Test name
Test status
Simulation time 539396596 ps
CPU time 0.99 seconds
Started Jul 24 05:07:55 PM PDT 24
Finished Jul 24 05:07:56 PM PDT 24
Peak memory 198580 kb
Host smart-f008b9d7-37f1-48a4-bf06-8fa5136a6947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576905614 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_escalation_timeout.3576905614
Directory /workspace/12.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/12.pwrmgr_glitch.803473921
Short name T520
Test name
Test status
Simulation time 39870672 ps
CPU time 0.58 seconds
Started Jul 24 05:08:28 PM PDT 24
Finished Jul 24 05:08:29 PM PDT 24
Peak memory 198568 kb
Host smart-c7e4d3fe-2683-4ce9-adb7-15240dadf10b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803473921 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_glitch.803473921
Directory /workspace/12.pwrmgr_glitch/latest

Test location /workspace/coverage/default/12.pwrmgr_global_esc.3909858316
Short name T450
Test name
Test status
Simulation time 24402688 ps
CPU time 0.61 seconds
Started Jul 24 05:07:40 PM PDT 24
Finished Jul 24 05:07:40 PM PDT 24
Peak memory 198936 kb
Host smart-911e5752-0b15-4982-a29f-843a9e6259b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909858316 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_global_esc.3909858316
Directory /workspace/12.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/12.pwrmgr_reset.1030897193
Short name T351
Test name
Test status
Simulation time 40418379 ps
CPU time 0.68 seconds
Started Jul 24 05:07:54 PM PDT 24
Finished Jul 24 05:07:54 PM PDT 24
Peak memory 199668 kb
Host smart-2a020030-e27d-483f-8756-8ed042247383
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030897193 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset.1030897193
Directory /workspace/12.pwrmgr_reset/latest

Test location /workspace/coverage/default/12.pwrmgr_reset_invalid.2915436573
Short name T625
Test name
Test status
Simulation time 95187250 ps
CPU time 1.01 seconds
Started Jul 24 05:07:42 PM PDT 24
Finished Jul 24 05:07:43 PM PDT 24
Peak memory 209612 kb
Host smart-c648e4dd-8882-49cb-a4cb-06f18a3b47b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915436573 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset_invalid.2915436573
Directory /workspace/12.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/12.pwrmgr_sec_cm_rstmgr_intersig_mubi.1392613039
Short name T522
Test name
Test status
Simulation time 53478573 ps
CPU time 0.76 seconds
Started Jul 24 05:08:04 PM PDT 24
Finished Jul 24 05:08:05 PM PDT 24
Peak memory 198548 kb
Host smart-a1d00d19-08e0-426d-b9e5-16a66668cb50
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392613039 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1392613039
Directory /workspace/12.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/12.pwrmgr_smoke.3315552118
Short name T494
Test name
Test status
Simulation time 86156171 ps
CPU time 0.61 seconds
Started Jul 24 05:07:51 PM PDT 24
Finished Jul 24 05:07:51 PM PDT 24
Peak memory 199072 kb
Host smart-517bb704-9419-453f-9a21-40c11c371635
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315552118 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_smoke.3315552118
Directory /workspace/12.pwrmgr_smoke/latest

Test location /workspace/coverage/default/13.pwrmgr_aborted_low_power.420189750
Short name T439
Test name
Test status
Simulation time 111195175 ps
CPU time 0.8 seconds
Started Jul 24 05:07:52 PM PDT 24
Finished Jul 24 05:07:53 PM PDT 24
Peak memory 200684 kb
Host smart-bc69a541-5caa-4b15-9e59-c83591cdf41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420189750 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_aborted_low_power.420189750
Directory /workspace/13.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/13.pwrmgr_disable_rom_integrity_check.592893580
Short name T205
Test name
Test status
Simulation time 225691062 ps
CPU time 0.67 seconds
Started Jul 24 05:07:45 PM PDT 24
Finished Jul 24 05:07:46 PM PDT 24
Peak memory 198856 kb
Host smart-68cc0c90-68e1-45eb-a6ea-f2eb628791f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592893580 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_disa
ble_rom_integrity_check.592893580
Directory /workspace/13.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/13.pwrmgr_esc_clk_rst_malfunc.41456628
Short name T564
Test name
Test status
Simulation time 38213528 ps
CPU time 0.59 seconds
Started Jul 24 05:07:55 PM PDT 24
Finished Jul 24 05:08:01 PM PDT 24
Peak memory 198576 kb
Host smart-767cf299-5cbb-4a5a-a69c-bdaacac256b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41456628 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_mal
func_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_esc_clk_rst_m
alfunc.41456628
Directory /workspace/13.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/13.pwrmgr_escalation_timeout.2515771408
Short name T274
Test name
Test status
Simulation time 169323941 ps
CPU time 0.97 seconds
Started Jul 24 05:07:52 PM PDT 24
Finished Jul 24 05:07:53 PM PDT 24
Peak memory 198676 kb
Host smart-6b6645be-9887-4eb7-9f19-422660cbcbfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515771408 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_escalation_timeout.2515771408
Directory /workspace/13.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/13.pwrmgr_glitch.2153315226
Short name T407
Test name
Test status
Simulation time 54861112 ps
CPU time 0.63 seconds
Started Jul 24 05:07:57 PM PDT 24
Finished Jul 24 05:08:03 PM PDT 24
Peak memory 198536 kb
Host smart-2c930d9c-888b-422b-9c9e-31c29923eb97
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153315226 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_glitch.2153315226
Directory /workspace/13.pwrmgr_glitch/latest

Test location /workspace/coverage/default/13.pwrmgr_global_esc.3769100467
Short name T578
Test name
Test status
Simulation time 64263267 ps
CPU time 0.62 seconds
Started Jul 24 05:07:44 PM PDT 24
Finished Jul 24 05:07:45 PM PDT 24
Peak memory 198628 kb
Host smart-504519e1-a47f-4051-92bb-5432cd242ddd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769100467 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_global_esc.3769100467
Directory /workspace/13.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/13.pwrmgr_reset.3783643207
Short name T225
Test name
Test status
Simulation time 118585622 ps
CPU time 0.66 seconds
Started Jul 24 05:07:41 PM PDT 24
Finished Jul 24 05:07:41 PM PDT 24
Peak memory 198768 kb
Host smart-285a52d1-bb53-44e8-b132-89cc56bfdc31
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783643207 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset.3783643207
Directory /workspace/13.pwrmgr_reset/latest

Test location /workspace/coverage/default/13.pwrmgr_reset_invalid.2549262728
Short name T367
Test name
Test status
Simulation time 101939645 ps
CPU time 0.9 seconds
Started Jul 24 05:07:40 PM PDT 24
Finished Jul 24 05:07:41 PM PDT 24
Peak memory 210136 kb
Host smart-cb4ec9cb-e4e3-4576-a7e1-92bab39e989f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549262728 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset_invalid.2549262728
Directory /workspace/13.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/13.pwrmgr_sec_cm_rstmgr_intersig_mubi.470552996
Short name T40
Test name
Test status
Simulation time 119847983 ps
CPU time 0.72 seconds
Started Jul 24 05:07:39 PM PDT 24
Finished Jul 24 05:07:40 PM PDT 24
Peak memory 198788 kb
Host smart-fd5e5e80-c31f-4964-9d51-5719341876ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470552996 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_rstmgr_intersig_
mubi.470552996
Directory /workspace/13.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/13.pwrmgr_smoke.786796386
Short name T226
Test name
Test status
Simulation time 98423737 ps
CPU time 0.62 seconds
Started Jul 24 05:07:43 PM PDT 24
Finished Jul 24 05:07:44 PM PDT 24
Peak memory 198968 kb
Host smart-b042ebc8-07b3-476a-b0a3-d07c02f62f95
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786796386 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_smoke.786796386
Directory /workspace/13.pwrmgr_smoke/latest

Test location /workspace/coverage/default/14.pwrmgr_aborted_low_power.2343016541
Short name T408
Test name
Test status
Simulation time 46247914 ps
CPU time 0.87 seconds
Started Jul 24 05:07:42 PM PDT 24
Finished Jul 24 05:07:44 PM PDT 24
Peak memory 200560 kb
Host smart-f4de7657-97f2-45c5-9038-fd0584080f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343016541 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_aborted_low_power.2343016541
Directory /workspace/14.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/14.pwrmgr_disable_rom_integrity_check.1252043682
Short name T379
Test name
Test status
Simulation time 70414364 ps
CPU time 0.66 seconds
Started Jul 24 05:07:47 PM PDT 24
Finished Jul 24 05:07:48 PM PDT 24
Peak memory 198828 kb
Host smart-f7006516-1aee-4115-9287-e04a8627921c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252043682 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_dis
able_rom_integrity_check.1252043682
Directory /workspace/14.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/14.pwrmgr_esc_clk_rst_malfunc.2118142192
Short name T349
Test name
Test status
Simulation time 31017127 ps
CPU time 0.62 seconds
Started Jul 24 05:07:55 PM PDT 24
Finished Jul 24 05:07:56 PM PDT 24
Peak memory 197848 kb
Host smart-b9bf0025-c990-4487-9c68-2c755c374c3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118142192 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_esc_clk_rst
_malfunc.2118142192
Directory /workspace/14.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/14.pwrmgr_escalation_timeout.2116092757
Short name T48
Test name
Test status
Simulation time 728828639 ps
CPU time 0.95 seconds
Started Jul 24 05:07:49 PM PDT 24
Finished Jul 24 05:07:50 PM PDT 24
Peak memory 198632 kb
Host smart-8eeda196-04c2-4c44-a953-96f829d7419e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116092757 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_escalation_timeout.2116092757
Directory /workspace/14.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/14.pwrmgr_glitch.2380864049
Short name T72
Test name
Test status
Simulation time 40108831 ps
CPU time 0.58 seconds
Started Jul 24 05:07:53 PM PDT 24
Finished Jul 24 05:07:53 PM PDT 24
Peak memory 197804 kb
Host smart-c75ee33d-a22a-4221-872e-9eca510457a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380864049 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_glitch.2380864049
Directory /workspace/14.pwrmgr_glitch/latest

Test location /workspace/coverage/default/14.pwrmgr_global_esc.1503832645
Short name T495
Test name
Test status
Simulation time 24128174 ps
CPU time 0.6 seconds
Started Jul 24 05:07:47 PM PDT 24
Finished Jul 24 05:07:48 PM PDT 24
Peak memory 198644 kb
Host smart-4390aa63-00c2-4e38-81cb-0fcd474c2da3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503832645 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_global_esc.1503832645
Directory /workspace/14.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/14.pwrmgr_lowpower_invalid.2714960885
Short name T598
Test name
Test status
Simulation time 45405059 ps
CPU time 0.7 seconds
Started Jul 24 05:07:59 PM PDT 24
Finished Jul 24 05:08:00 PM PDT 24
Peak memory 201932 kb
Host smart-51aadca6-73b5-4396-9b82-261586339bca
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714960885 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_lowpower_inval
id.2714960885
Directory /workspace/14.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/14.pwrmgr_reset.2493561555
Short name T258
Test name
Test status
Simulation time 68782321 ps
CPU time 0.82 seconds
Started Jul 24 05:07:35 PM PDT 24
Finished Jul 24 05:07:36 PM PDT 24
Peak memory 199552 kb
Host smart-4d7f5efe-055d-4d2b-8d00-04cae5637ea0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493561555 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset.2493561555
Directory /workspace/14.pwrmgr_reset/latest

Test location /workspace/coverage/default/14.pwrmgr_reset_invalid.3048495519
Short name T592
Test name
Test status
Simulation time 296555860 ps
CPU time 0.77 seconds
Started Jul 24 05:07:41 PM PDT 24
Finished Jul 24 05:07:42 PM PDT 24
Peak memory 210096 kb
Host smart-5e3f486b-ede8-41e3-b8b9-7fb484accb88
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048495519 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset_invalid.3048495519
Directory /workspace/14.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/14.pwrmgr_sec_cm_rstmgr_intersig_mubi.1798769902
Short name T569
Test name
Test status
Simulation time 120500326 ps
CPU time 0.78 seconds
Started Jul 24 05:08:12 PM PDT 24
Finished Jul 24 05:08:14 PM PDT 24
Peak memory 198636 kb
Host smart-9a13af1d-4997-42a9-ab3b-4011077637af
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798769902 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1798769902
Directory /workspace/14.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/14.pwrmgr_smoke.709493183
Short name T602
Test name
Test status
Simulation time 31574907 ps
CPU time 0.74 seconds
Started Jul 24 05:08:22 PM PDT 24
Finished Jul 24 05:08:23 PM PDT 24
Peak memory 199900 kb
Host smart-a9baf26a-beab-4e8b-b5bf-6776cb799aac
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709493183 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_smoke.709493183
Directory /workspace/14.pwrmgr_smoke/latest

Test location /workspace/coverage/default/14.pwrmgr_stress_all.3334728187
Short name T575
Test name
Test status
Simulation time 145773006 ps
CPU time 1.1 seconds
Started Jul 24 05:07:57 PM PDT 24
Finished Jul 24 05:07:58 PM PDT 24
Peak memory 200148 kb
Host smart-9f1ce8d0-1104-4a8c-88a0-a113d72f6cae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334728187 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_stress_all.3334728187
Directory /workspace/14.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/15.pwrmgr_aborted_low_power.4170819849
Short name T255
Test name
Test status
Simulation time 44564544 ps
CPU time 0.88 seconds
Started Jul 24 05:07:45 PM PDT 24
Finished Jul 24 05:07:46 PM PDT 24
Peak memory 200840 kb
Host smart-4cda48ca-fe96-4765-ae03-d7d20acfdfb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170819849 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_aborted_low_power.4170819849
Directory /workspace/15.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/15.pwrmgr_disable_rom_integrity_check.867512222
Short name T201
Test name
Test status
Simulation time 66532520 ps
CPU time 0.77 seconds
Started Jul 24 05:07:48 PM PDT 24
Finished Jul 24 05:07:49 PM PDT 24
Peak memory 199652 kb
Host smart-cd1198cb-ff62-40b5-9b24-d42617f6aac6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867512222 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_disa
ble_rom_integrity_check.867512222
Directory /workspace/15.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/15.pwrmgr_esc_clk_rst_malfunc.2016238402
Short name T370
Test name
Test status
Simulation time 30786152 ps
CPU time 0.65 seconds
Started Jul 24 05:07:59 PM PDT 24
Finished Jul 24 05:08:00 PM PDT 24
Peak memory 197524 kb
Host smart-e026205c-eb50-4c59-a882-4d0cba259b6a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016238402 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_esc_clk_rst
_malfunc.2016238402
Directory /workspace/15.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/15.pwrmgr_escalation_timeout.1290671841
Short name T443
Test name
Test status
Simulation time 607353780 ps
CPU time 0.93 seconds
Started Jul 24 05:07:44 PM PDT 24
Finished Jul 24 05:07:45 PM PDT 24
Peak memory 198672 kb
Host smart-5c313985-d25d-4eca-bbfd-8bfe39c244e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290671841 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_escalation_timeout.1290671841
Directory /workspace/15.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/15.pwrmgr_glitch.3767745093
Short name T478
Test name
Test status
Simulation time 50678685 ps
CPU time 0.61 seconds
Started Jul 24 05:07:49 PM PDT 24
Finished Jul 24 05:07:50 PM PDT 24
Peak memory 198580 kb
Host smart-5d17f607-2566-48b2-ab3c-630004b61950
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767745093 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_glitch.3767745093
Directory /workspace/15.pwrmgr_glitch/latest

Test location /workspace/coverage/default/15.pwrmgr_global_esc.1276758975
Short name T484
Test name
Test status
Simulation time 45348448 ps
CPU time 0.67 seconds
Started Jul 24 05:07:57 PM PDT 24
Finished Jul 24 05:07:58 PM PDT 24
Peak memory 198640 kb
Host smart-ac203e33-4fdf-497a-9503-9fbd03bc8c24
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276758975 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_global_esc.1276758975
Directory /workspace/15.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/15.pwrmgr_lowpower_invalid.2514317425
Short name T171
Test name
Test status
Simulation time 43538866 ps
CPU time 0.73 seconds
Started Jul 24 05:07:45 PM PDT 24
Finished Jul 24 05:07:46 PM PDT 24
Peak memory 201952 kb
Host smart-9a6d2603-2c9c-40e0-bfc7-3440bebafdc4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514317425 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_lowpower_inval
id.2514317425
Directory /workspace/15.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/15.pwrmgr_reset.1190142755
Short name T356
Test name
Test status
Simulation time 48128826 ps
CPU time 0.65 seconds
Started Jul 24 05:08:01 PM PDT 24
Finished Jul 24 05:08:02 PM PDT 24
Peak memory 199660 kb
Host smart-428af08f-e128-471b-9759-39c00f53d6af
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190142755 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset.1190142755
Directory /workspace/15.pwrmgr_reset/latest

Test location /workspace/coverage/default/15.pwrmgr_reset_invalid.2525450270
Short name T452
Test name
Test status
Simulation time 100863020 ps
CPU time 0.9 seconds
Started Jul 24 05:07:56 PM PDT 24
Finished Jul 24 05:07:57 PM PDT 24
Peak memory 210068 kb
Host smart-92292a51-ba61-4eec-8589-73ec04f3870b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525450270 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset_invalid.2525450270
Directory /workspace/15.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/15.pwrmgr_sec_cm_rstmgr_intersig_mubi.1071168957
Short name T614
Test name
Test status
Simulation time 75783689 ps
CPU time 0.8 seconds
Started Jul 24 05:07:58 PM PDT 24
Finished Jul 24 05:07:59 PM PDT 24
Peak memory 198588 kb
Host smart-dac3cf6f-3b8c-43ed-8bd8-7b0de7752089
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071168957 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1071168957
Directory /workspace/15.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/15.pwrmgr_wakeup.1041808742
Short name T57
Test name
Test status
Simulation time 61513989 ps
CPU time 0.74 seconds
Started Jul 24 05:07:53 PM PDT 24
Finished Jul 24 05:07:54 PM PDT 24
Peak memory 198848 kb
Host smart-70341c52-543e-4835-90e5-3e12db911c9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041808742 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_wakeup.1041808742
Directory /workspace/15.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/16.pwrmgr_aborted_low_power.2964006266
Short name T476
Test name
Test status
Simulation time 72054410 ps
CPU time 0.86 seconds
Started Jul 24 05:07:55 PM PDT 24
Finished Jul 24 05:07:56 PM PDT 24
Peak memory 200660 kb
Host smart-a4346cc1-9d8b-4ec2-8e55-ae31d087c08c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964006266 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_aborted_low_power.2964006266
Directory /workspace/16.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/16.pwrmgr_esc_clk_rst_malfunc.635935043
Short name T328
Test name
Test status
Simulation time 28453016 ps
CPU time 0.64 seconds
Started Jul 24 05:08:17 PM PDT 24
Finished Jul 24 05:08:18 PM PDT 24
Peak memory 198564 kb
Host smart-df54431f-e7da-4799-8a37-af4c617f76e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635935043 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_esc_clk_rst_
malfunc.635935043
Directory /workspace/16.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/16.pwrmgr_escalation_timeout.748443839
Short name T93
Test name
Test status
Simulation time 678471295 ps
CPU time 0.94 seconds
Started Jul 24 05:07:44 PM PDT 24
Finished Jul 24 05:07:50 PM PDT 24
Peak memory 198476 kb
Host smart-31d0d151-e89c-4869-aeb5-36b3b5f85c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748443839 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_escalation_timeout.748443839
Directory /workspace/16.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/16.pwrmgr_glitch.2879240271
Short name T377
Test name
Test status
Simulation time 23926847 ps
CPU time 0.62 seconds
Started Jul 24 05:07:55 PM PDT 24
Finished Jul 24 05:07:56 PM PDT 24
Peak memory 198552 kb
Host smart-bce85d4e-e105-43e0-9980-bdd8a2e74db0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879240271 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_glitch.2879240271
Directory /workspace/16.pwrmgr_glitch/latest

Test location /workspace/coverage/default/16.pwrmgr_global_esc.1725713869
Short name T10
Test name
Test status
Simulation time 35644105 ps
CPU time 0.61 seconds
Started Jul 24 05:08:09 PM PDT 24
Finished Jul 24 05:08:10 PM PDT 24
Peak memory 198504 kb
Host smart-b7620e00-4550-46d4-89be-9f434c66599d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725713869 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_global_esc.1725713869
Directory /workspace/16.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/16.pwrmgr_lowpower_invalid.3877488503
Short name T172
Test name
Test status
Simulation time 111879424 ps
CPU time 0.67 seconds
Started Jul 24 05:08:00 PM PDT 24
Finished Jul 24 05:08:01 PM PDT 24
Peak memory 201936 kb
Host smart-5a9ba047-a913-4635-afee-a0e93d5cfee2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877488503 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_lowpower_inval
id.3877488503
Directory /workspace/16.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/16.pwrmgr_reset.2294930695
Short name T607
Test name
Test status
Simulation time 104449655 ps
CPU time 0.77 seconds
Started Jul 24 05:07:46 PM PDT 24
Finished Jul 24 05:07:47 PM PDT 24
Peak memory 199068 kb
Host smart-b1822be0-568f-4002-acb9-c3daa2fdf6ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294930695 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset.2294930695
Directory /workspace/16.pwrmgr_reset/latest

Test location /workspace/coverage/default/16.pwrmgr_reset_invalid.3731497711
Short name T42
Test name
Test status
Simulation time 546274353 ps
CPU time 0.76 seconds
Started Jul 24 05:07:58 PM PDT 24
Finished Jul 24 05:07:59 PM PDT 24
Peak memory 210068 kb
Host smart-b0f5f867-3ad6-4268-bd48-f9c255b889a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731497711 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset_invalid.3731497711
Directory /workspace/16.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/16.pwrmgr_sec_cm_rstmgr_intersig_mubi.267035489
Short name T462
Test name
Test status
Simulation time 100060944 ps
CPU time 0.7 seconds
Started Jul 24 05:08:19 PM PDT 24
Finished Jul 24 05:08:20 PM PDT 24
Peak memory 198152 kb
Host smart-2606e140-2fc5-4296-a644-e4b23fdc1e5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267035489 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_cm_rstmgr_intersig_
mubi.267035489
Directory /workspace/16.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/16.pwrmgr_smoke.4206279884
Short name T278
Test name
Test status
Simulation time 31980743 ps
CPU time 0.69 seconds
Started Jul 24 05:07:46 PM PDT 24
Finished Jul 24 05:07:47 PM PDT 24
Peak memory 200100 kb
Host smart-047e679c-11e2-4251-9509-0bbfaf3c9a65
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206279884 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_smoke.4206279884
Directory /workspace/16.pwrmgr_smoke/latest

Test location /workspace/coverage/default/17.pwrmgr_aborted_low_power.3410185451
Short name T101
Test name
Test status
Simulation time 93893094 ps
CPU time 0.69 seconds
Started Jul 24 05:08:11 PM PDT 24
Finished Jul 24 05:08:12 PM PDT 24
Peak memory 199272 kb
Host smart-ac95a9e3-2c6b-49d1-be00-44cea3c07753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410185451 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_aborted_low_power.3410185451
Directory /workspace/17.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/17.pwrmgr_disable_rom_integrity_check.1487432080
Short name T359
Test name
Test status
Simulation time 188468927 ps
CPU time 0.65 seconds
Started Jul 24 05:07:51 PM PDT 24
Finished Jul 24 05:07:52 PM PDT 24
Peak memory 198892 kb
Host smart-d7b6ebe7-6944-4b09-a09e-7fd00157297e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487432080 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_dis
able_rom_integrity_check.1487432080
Directory /workspace/17.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/17.pwrmgr_esc_clk_rst_malfunc.3377636560
Short name T2
Test name
Test status
Simulation time 29091295 ps
CPU time 0.62 seconds
Started Jul 24 05:08:05 PM PDT 24
Finished Jul 24 05:08:06 PM PDT 24
Peak memory 198516 kb
Host smart-9a1180a2-d126-457d-8821-627ad70417b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377636560 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_esc_clk_rst
_malfunc.3377636560
Directory /workspace/17.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/17.pwrmgr_escalation_timeout.3358961340
Short name T128
Test name
Test status
Simulation time 825251894 ps
CPU time 0.95 seconds
Started Jul 24 05:07:50 PM PDT 24
Finished Jul 24 05:07:51 PM PDT 24
Peak memory 198684 kb
Host smart-67d59fa5-541e-4294-a0c5-d3a211d6955f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358961340 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_escalation_timeout.3358961340
Directory /workspace/17.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/17.pwrmgr_glitch.641059771
Short name T442
Test name
Test status
Simulation time 47825095 ps
CPU time 0.65 seconds
Started Jul 24 05:07:52 PM PDT 24
Finished Jul 24 05:07:53 PM PDT 24
Peak memory 198456 kb
Host smart-f27afc71-27dc-479c-b978-f0b4a5c5d4ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641059771 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_glitch.641059771
Directory /workspace/17.pwrmgr_glitch/latest

Test location /workspace/coverage/default/17.pwrmgr_global_esc.2460145885
Short name T240
Test name
Test status
Simulation time 39417894 ps
CPU time 0.6 seconds
Started Jul 24 05:08:16 PM PDT 24
Finished Jul 24 05:08:17 PM PDT 24
Peak memory 198928 kb
Host smart-9e2a8759-8b59-4bb8-875f-6094ca29d12b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460145885 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_global_esc.2460145885
Directory /workspace/17.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/17.pwrmgr_lowpower_invalid.2540750847
Short name T156
Test name
Test status
Simulation time 51492826 ps
CPU time 0.72 seconds
Started Jul 24 05:08:04 PM PDT 24
Finished Jul 24 05:08:05 PM PDT 24
Peak memory 201676 kb
Host smart-14060fea-dcfa-409e-9336-130d562a5744
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540750847 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_lowpower_inval
id.2540750847
Directory /workspace/17.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/17.pwrmgr_reset.3781676795
Short name T330
Test name
Test status
Simulation time 51141921 ps
CPU time 0.83 seconds
Started Jul 24 05:07:50 PM PDT 24
Finished Jul 24 05:07:51 PM PDT 24
Peak memory 199240 kb
Host smart-0a758679-b793-49a6-8049-ef5df3157d1c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781676795 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset.3781676795
Directory /workspace/17.pwrmgr_reset/latest

Test location /workspace/coverage/default/17.pwrmgr_reset_invalid.2910225922
Short name T567
Test name
Test status
Simulation time 105591092 ps
CPU time 0.86 seconds
Started Jul 24 05:07:51 PM PDT 24
Finished Jul 24 05:07:52 PM PDT 24
Peak memory 209912 kb
Host smart-f11edf2f-18fa-4571-b29b-063f3c6641ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910225922 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset_invalid.2910225922
Directory /workspace/17.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/17.pwrmgr_sec_cm_rstmgr_intersig_mubi.3595336452
Short name T211
Test name
Test status
Simulation time 175567971 ps
CPU time 0.82 seconds
Started Jul 24 05:07:58 PM PDT 24
Finished Jul 24 05:07:59 PM PDT 24
Peak memory 200116 kb
Host smart-5e1f2ee0-152a-470e-a5dd-980e7da3b4ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595336452 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3595336452
Directory /workspace/17.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/17.pwrmgr_smoke.959822893
Short name T289
Test name
Test status
Simulation time 30196032 ps
CPU time 0.64 seconds
Started Jul 24 05:07:59 PM PDT 24
Finished Jul 24 05:08:00 PM PDT 24
Peak memory 199848 kb
Host smart-08513b48-8894-49ef-8392-6e00a571e59a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959822893 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_smoke.959822893
Directory /workspace/17.pwrmgr_smoke/latest

Test location /workspace/coverage/default/18.pwrmgr_aborted_low_power.1402065756
Short name T96
Test name
Test status
Simulation time 76009105 ps
CPU time 0.75 seconds
Started Jul 24 05:07:54 PM PDT 24
Finished Jul 24 05:07:55 PM PDT 24
Peak memory 200516 kb
Host smart-50888d4a-1930-413d-be2a-3e82edd88044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402065756 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_aborted_low_power.1402065756
Directory /workspace/18.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/18.pwrmgr_disable_rom_integrity_check.876823305
Short name T137
Test name
Test status
Simulation time 56619234 ps
CPU time 0.78 seconds
Started Jul 24 05:07:56 PM PDT 24
Finished Jul 24 05:07:57 PM PDT 24
Peak memory 199640 kb
Host smart-0732ef0e-2bb5-429f-8dd7-44b48bd387f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876823305 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_disa
ble_rom_integrity_check.876823305
Directory /workspace/18.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/18.pwrmgr_esc_clk_rst_malfunc.583958436
Short name T383
Test name
Test status
Simulation time 42368789 ps
CPU time 0.6 seconds
Started Jul 24 05:07:43 PM PDT 24
Finished Jul 24 05:07:44 PM PDT 24
Peak memory 198500 kb
Host smart-d4727041-29dc-4c44-8317-dad1db07279d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583958436 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_esc_clk_rst_
malfunc.583958436
Directory /workspace/18.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/18.pwrmgr_escalation_timeout.1818953724
Short name T371
Test name
Test status
Simulation time 168455657 ps
CPU time 0.95 seconds
Started Jul 24 05:07:54 PM PDT 24
Finished Jul 24 05:07:55 PM PDT 24
Peak memory 198664 kb
Host smart-17bee8b5-a129-41da-b334-c76caeafafdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818953724 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_escalation_timeout.1818953724
Directory /workspace/18.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/18.pwrmgr_glitch.1785184831
Short name T4
Test name
Test status
Simulation time 78868116 ps
CPU time 0.59 seconds
Started Jul 24 05:08:12 PM PDT 24
Finished Jul 24 05:08:13 PM PDT 24
Peak memory 198600 kb
Host smart-30f6b40b-9d32-4588-92c6-36997108f397
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785184831 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_glitch.1785184831
Directory /workspace/18.pwrmgr_glitch/latest

Test location /workspace/coverage/default/18.pwrmgr_global_esc.1927919537
Short name T571
Test name
Test status
Simulation time 72200465 ps
CPU time 0.59 seconds
Started Jul 24 05:08:03 PM PDT 24
Finished Jul 24 05:08:03 PM PDT 24
Peak memory 198560 kb
Host smart-38feafb5-ef0f-4167-82e0-8f4509386807
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927919537 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_global_esc.1927919537
Directory /workspace/18.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/18.pwrmgr_lowpower_invalid.869645689
Short name T426
Test name
Test status
Simulation time 138155938 ps
CPU time 0.67 seconds
Started Jul 24 05:07:59 PM PDT 24
Finished Jul 24 05:07:59 PM PDT 24
Peak memory 201964 kb
Host smart-efad2ad2-bac3-40c4-baad-b8e3c7858ac2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869645689 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_lowpower_invali
d.869645689
Directory /workspace/18.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/18.pwrmgr_lowpower_wakeup_race.2848620588
Short name T53
Test name
Test status
Simulation time 42282848 ps
CPU time 0.59 seconds
Started Jul 24 05:07:55 PM PDT 24
Finished Jul 24 05:07:56 PM PDT 24
Peak memory 199580 kb
Host smart-10ed776a-5d6d-4631-bba9-7f75c01ead74
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848620588 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_lowpower_w
akeup_race.2848620588
Directory /workspace/18.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/18.pwrmgr_reset.3778445814
Short name T394
Test name
Test status
Simulation time 47851950 ps
CPU time 0.79 seconds
Started Jul 24 05:07:49 PM PDT 24
Finished Jul 24 05:07:50 PM PDT 24
Peak memory 199604 kb
Host smart-57023bbb-6c20-4af4-8a20-f2a7acee7781
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778445814 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset.3778445814
Directory /workspace/18.pwrmgr_reset/latest

Test location /workspace/coverage/default/18.pwrmgr_reset_invalid.2498232688
Short name T427
Test name
Test status
Simulation time 106653184 ps
CPU time 0.93 seconds
Started Jul 24 05:07:50 PM PDT 24
Finished Jul 24 05:07:56 PM PDT 24
Peak memory 210032 kb
Host smart-e1ed96ec-394a-4ac5-8893-ae0b4e40905f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498232688 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset_invalid.2498232688
Directory /workspace/18.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/18.pwrmgr_sec_cm_rstmgr_intersig_mubi.1852946559
Short name T252
Test name
Test status
Simulation time 97444966 ps
CPU time 0.73 seconds
Started Jul 24 05:08:05 PM PDT 24
Finished Jul 24 05:08:06 PM PDT 24
Peak memory 198676 kb
Host smart-2358ff11-102c-4eac-addf-1b18455f089e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852946559 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1852946559
Directory /workspace/18.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/18.pwrmgr_smoke.402593194
Short name T624
Test name
Test status
Simulation time 64832202 ps
CPU time 0.61 seconds
Started Jul 24 05:07:59 PM PDT 24
Finished Jul 24 05:08:00 PM PDT 24
Peak memory 199084 kb
Host smart-0206b7cc-fd88-4fca-85be-fb538402c34d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402593194 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_smoke.402593194
Directory /workspace/18.pwrmgr_smoke/latest

Test location /workspace/coverage/default/19.pwrmgr_aborted_low_power.132028413
Short name T103
Test name
Test status
Simulation time 36531423 ps
CPU time 0.95 seconds
Started Jul 24 05:07:54 PM PDT 24
Finished Jul 24 05:07:55 PM PDT 24
Peak memory 201244 kb
Host smart-24af5a6f-c807-47e7-b006-6db3a28d10d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132028413 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_aborted_low_power.132028413
Directory /workspace/19.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/19.pwrmgr_disable_rom_integrity_check.1168945460
Short name T203
Test name
Test status
Simulation time 63514803 ps
CPU time 0.67 seconds
Started Jul 24 05:08:05 PM PDT 24
Finished Jul 24 05:08:06 PM PDT 24
Peak memory 199672 kb
Host smart-bc4038b4-ec70-4ce0-8820-e042d4b26c8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168945460 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_dis
able_rom_integrity_check.1168945460
Directory /workspace/19.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/19.pwrmgr_esc_clk_rst_malfunc.2439502762
Short name T536
Test name
Test status
Simulation time 103194390 ps
CPU time 0.6 seconds
Started Jul 24 05:08:01 PM PDT 24
Finished Jul 24 05:08:02 PM PDT 24
Peak memory 198584 kb
Host smart-1b4cdb2b-4ac3-476a-8eb8-cbb3c2bb9253
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439502762 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_esc_clk_rst
_malfunc.2439502762
Directory /workspace/19.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/19.pwrmgr_escalation_timeout.1575335308
Short name T354
Test name
Test status
Simulation time 164898027 ps
CPU time 0.91 seconds
Started Jul 24 05:07:44 PM PDT 24
Finished Jul 24 05:07:45 PM PDT 24
Peak memory 198820 kb
Host smart-8512b82f-af44-4003-a6c2-db3adb26cb1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575335308 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_escalation_timeout.1575335308
Directory /workspace/19.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/19.pwrmgr_glitch.1687653182
Short name T70
Test name
Test status
Simulation time 37886408 ps
CPU time 0.63 seconds
Started Jul 24 05:07:43 PM PDT 24
Finished Jul 24 05:07:44 PM PDT 24
Peak memory 197788 kb
Host smart-bc8e2a7c-dca9-43ca-8e8a-d3d84d0f08d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687653182 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_glitch.1687653182
Directory /workspace/19.pwrmgr_glitch/latest

Test location /workspace/coverage/default/19.pwrmgr_global_esc.2368619228
Short name T436
Test name
Test status
Simulation time 54666545 ps
CPU time 0.61 seconds
Started Jul 24 05:07:42 PM PDT 24
Finished Jul 24 05:07:43 PM PDT 24
Peak memory 198568 kb
Host smart-c7e1111e-5837-46e2-bb12-f0074950c468
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368619228 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_global_esc.2368619228
Directory /workspace/19.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/19.pwrmgr_lowpower_invalid.1739499951
Short name T155
Test name
Test status
Simulation time 44572000 ps
CPU time 0.71 seconds
Started Jul 24 05:08:16 PM PDT 24
Finished Jul 24 05:08:17 PM PDT 24
Peak memory 201960 kb
Host smart-3888cb44-4f5b-4afc-887d-e515790eef45
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739499951 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_lowpower_inval
id.1739499951
Directory /workspace/19.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/19.pwrmgr_reset.833104560
Short name T288
Test name
Test status
Simulation time 93371420 ps
CPU time 0.73 seconds
Started Jul 24 05:07:52 PM PDT 24
Finished Jul 24 05:07:53 PM PDT 24
Peak memory 199504 kb
Host smart-9a101579-1739-432d-b026-a5d35ee786d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833104560 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset.833104560
Directory /workspace/19.pwrmgr_reset/latest

Test location /workspace/coverage/default/19.pwrmgr_reset_invalid.1070506635
Short name T411
Test name
Test status
Simulation time 108573021 ps
CPU time 0.99 seconds
Started Jul 24 05:08:02 PM PDT 24
Finished Jul 24 05:08:08 PM PDT 24
Peak memory 209996 kb
Host smart-f0383ab3-cdb0-4a8f-aacc-28ea2a297d4c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070506635 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset_invalid.1070506635
Directory /workspace/19.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/19.pwrmgr_sec_cm_rstmgr_intersig_mubi.790317070
Short name T340
Test name
Test status
Simulation time 84767461 ps
CPU time 0.67 seconds
Started Jul 24 05:07:42 PM PDT 24
Finished Jul 24 05:07:42 PM PDT 24
Peak memory 198632 kb
Host smart-2eef2185-7b40-46a3-9c32-3d8f3feb43bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790317070 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_cm_rstmgr_intersig_
mubi.790317070
Directory /workspace/19.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/19.pwrmgr_smoke.2136854008
Short name T32
Test name
Test status
Simulation time 28426078 ps
CPU time 0.68 seconds
Started Jul 24 05:08:18 PM PDT 24
Finished Jul 24 05:08:18 PM PDT 24
Peak memory 199756 kb
Host smart-c65ff017-c162-4b5a-a8a6-f6999e43b6c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136854008 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_smoke.2136854008
Directory /workspace/19.pwrmgr_smoke/latest

Test location /workspace/coverage/default/2.pwrmgr_aborted_low_power.1521372301
Short name T417
Test name
Test status
Simulation time 94510674 ps
CPU time 0.79 seconds
Started Jul 24 05:07:08 PM PDT 24
Finished Jul 24 05:07:09 PM PDT 24
Peak memory 199448 kb
Host smart-e7050256-720e-46a1-b01c-de139271805f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521372301 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_aborted_low_power.1521372301
Directory /workspace/2.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/2.pwrmgr_disable_rom_integrity_check.1072172540
Short name T197
Test name
Test status
Simulation time 79937503 ps
CPU time 0.67 seconds
Started Jul 24 05:07:16 PM PDT 24
Finished Jul 24 05:07:16 PM PDT 24
Peak memory 198824 kb
Host smart-221eec1e-96dc-42b5-aa17-6fd899131d9d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072172540 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_disa
ble_rom_integrity_check.1072172540
Directory /workspace/2.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/2.pwrmgr_esc_clk_rst_malfunc.1025945909
Short name T312
Test name
Test status
Simulation time 41156141 ps
CPU time 0.6 seconds
Started Jul 24 05:07:00 PM PDT 24
Finished Jul 24 05:07:01 PM PDT 24
Peak memory 197708 kb
Host smart-79e6054f-83c6-4abd-87ca-e9ead8f35157
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025945909 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_esc_clk_rst_
malfunc.1025945909
Directory /workspace/2.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/2.pwrmgr_escalation_timeout.2284575881
Short name T131
Test name
Test status
Simulation time 622004969 ps
CPU time 0.92 seconds
Started Jul 24 05:07:09 PM PDT 24
Finished Jul 24 05:07:10 PM PDT 24
Peak memory 198572 kb
Host smart-427a8f19-08e0-43c3-9e5d-bd4d54a0bba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284575881 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_escalation_timeout.2284575881
Directory /workspace/2.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/2.pwrmgr_glitch.1868139840
Short name T547
Test name
Test status
Simulation time 61561046 ps
CPU time 0.71 seconds
Started Jul 24 05:07:24 PM PDT 24
Finished Jul 24 05:07:24 PM PDT 24
Peak memory 198544 kb
Host smart-ec96c6e4-9aeb-4253-a6e3-e65449e4b403
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868139840 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_glitch.1868139840
Directory /workspace/2.pwrmgr_glitch/latest

Test location /workspace/coverage/default/2.pwrmgr_global_esc.468653314
Short name T480
Test name
Test status
Simulation time 41573074 ps
CPU time 0.61 seconds
Started Jul 24 05:07:10 PM PDT 24
Finished Jul 24 05:07:11 PM PDT 24
Peak memory 198620 kb
Host smart-16235f66-e4da-4964-b1bb-0bc3cf1c3ffd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468653314 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_global_esc.468653314
Directory /workspace/2.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/2.pwrmgr_reset.3586495030
Short name T412
Test name
Test status
Simulation time 74014531 ps
CPU time 0.83 seconds
Started Jul 24 05:06:56 PM PDT 24
Finished Jul 24 05:06:57 PM PDT 24
Peak memory 198932 kb
Host smart-e8855786-5c6a-4754-9efe-486d442715a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586495030 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset.3586495030
Directory /workspace/2.pwrmgr_reset/latest

Test location /workspace/coverage/default/2.pwrmgr_reset_invalid.2031208786
Short name T424
Test name
Test status
Simulation time 100486090 ps
CPU time 0.85 seconds
Started Jul 24 05:07:06 PM PDT 24
Finished Jul 24 05:07:08 PM PDT 24
Peak memory 210124 kb
Host smart-db30337c-82c8-4d3e-a142-2a14b8715973
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031208786 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset_invalid.2031208786
Directory /workspace/2.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm.1705093249
Short name T21
Test name
Test status
Simulation time 386155899 ps
CPU time 1.1 seconds
Started Jul 24 05:07:27 PM PDT 24
Finished Jul 24 05:07:29 PM PDT 24
Peak memory 217952 kb
Host smart-5e5c7437-0805-4d71-b4de-8d8f7b0eb17e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705093249 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm.1705093249
Directory /workspace/2.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm_rstmgr_intersig_mubi.922071274
Short name T556
Test name
Test status
Simulation time 86383270 ps
CPU time 0.67 seconds
Started Jul 24 05:07:18 PM PDT 24
Finished Jul 24 05:07:19 PM PDT 24
Peak memory 198480 kb
Host smart-fc018582-8aaa-4f89-b8ff-37b36f2ce861
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922071274 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.922071274
Directory /workspace/2.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/2.pwrmgr_smoke.2238337114
Short name T502
Test name
Test status
Simulation time 30526632 ps
CPU time 0.68 seconds
Started Jul 24 05:06:57 PM PDT 24
Finished Jul 24 05:06:58 PM PDT 24
Peak memory 199916 kb
Host smart-83b7cc66-0055-48ce-b791-3d31e3b3e056
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238337114 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_smoke.2238337114
Directory /workspace/2.pwrmgr_smoke/latest

Test location /workspace/coverage/default/20.pwrmgr_disable_rom_integrity_check.3342137955
Short name T140
Test name
Test status
Simulation time 65401985 ps
CPU time 0.66 seconds
Started Jul 24 05:07:52 PM PDT 24
Finished Jul 24 05:07:53 PM PDT 24
Peak memory 199508 kb
Host smart-d5296c90-7f61-47e7-b984-a6d179acc9dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342137955 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_dis
able_rom_integrity_check.3342137955
Directory /workspace/20.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/20.pwrmgr_esc_clk_rst_malfunc.1558840261
Short name T497
Test name
Test status
Simulation time 32163915 ps
CPU time 0.58 seconds
Started Jul 24 05:08:04 PM PDT 24
Finished Jul 24 05:08:05 PM PDT 24
Peak memory 198568 kb
Host smart-75159d95-41cd-4295-8dc7-43a353db3480
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558840261 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_esc_clk_rst
_malfunc.1558840261
Directory /workspace/20.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/20.pwrmgr_escalation_timeout.2586125425
Short name T612
Test name
Test status
Simulation time 1259832243 ps
CPU time 1 seconds
Started Jul 24 05:08:00 PM PDT 24
Finished Jul 24 05:08:01 PM PDT 24
Peak memory 198672 kb
Host smart-cb348d7a-9340-475a-be6d-1e8b67cdd3d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586125425 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_escalation_timeout.2586125425
Directory /workspace/20.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/20.pwrmgr_glitch.1594624495
Short name T18
Test name
Test status
Simulation time 37219127 ps
CPU time 0.64 seconds
Started Jul 24 05:08:12 PM PDT 24
Finished Jul 24 05:08:14 PM PDT 24
Peak memory 198464 kb
Host smart-69805118-14df-42ef-bbe9-71e86c1dbfb9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594624495 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_glitch.1594624495
Directory /workspace/20.pwrmgr_glitch/latest

Test location /workspace/coverage/default/20.pwrmgr_global_esc.422701395
Short name T434
Test name
Test status
Simulation time 225716273 ps
CPU time 0.61 seconds
Started Jul 24 05:07:58 PM PDT 24
Finished Jul 24 05:07:58 PM PDT 24
Peak memory 198940 kb
Host smart-413a8f4a-d02d-4171-a28b-5f85a9553b92
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422701395 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_global_esc.422701395
Directory /workspace/20.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/20.pwrmgr_lowpower_invalid.900251222
Short name T577
Test name
Test status
Simulation time 152293800 ps
CPU time 0.66 seconds
Started Jul 24 05:07:58 PM PDT 24
Finished Jul 24 05:07:59 PM PDT 24
Peak memory 201932 kb
Host smart-a9509856-976f-470a-b350-04b61f166800
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900251222 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_lowpower_invali
d.900251222
Directory /workspace/20.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/20.pwrmgr_reset.3075072514
Short name T213
Test name
Test status
Simulation time 66913633 ps
CPU time 0.72 seconds
Started Jul 24 05:08:16 PM PDT 24
Finished Jul 24 05:08:17 PM PDT 24
Peak memory 199620 kb
Host smart-9739850f-b4b6-47f6-8150-4b3ecdacf5c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075072514 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset.3075072514
Directory /workspace/20.pwrmgr_reset/latest

Test location /workspace/coverage/default/20.pwrmgr_reset_invalid.4061625388
Short name T378
Test name
Test status
Simulation time 180055253 ps
CPU time 0.78 seconds
Started Jul 24 05:07:52 PM PDT 24
Finished Jul 24 05:07:53 PM PDT 24
Peak memory 209976 kb
Host smart-ac5ef440-7831-4823-89ed-fdad2246c234
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061625388 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset_invalid.4061625388
Directory /workspace/20.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/20.pwrmgr_sec_cm_rstmgr_intersig_mubi.3615715697
Short name T308
Test name
Test status
Simulation time 86875913 ps
CPU time 0.79 seconds
Started Jul 24 05:08:02 PM PDT 24
Finished Jul 24 05:08:08 PM PDT 24
Peak memory 199756 kb
Host smart-62660f50-b784-4c74-a336-3e0505460db6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615715697 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3615715697
Directory /workspace/20.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/20.pwrmgr_smoke.1525114634
Short name T472
Test name
Test status
Simulation time 56754728 ps
CPU time 0.62 seconds
Started Jul 24 05:08:04 PM PDT 24
Finished Jul 24 05:08:04 PM PDT 24
Peak memory 199852 kb
Host smart-cfc8caf5-4f64-4ed0-86f7-cf4a9e9e317c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525114634 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_smoke.1525114634
Directory /workspace/20.pwrmgr_smoke/latest

Test location /workspace/coverage/default/21.pwrmgr_aborted_low_power.406122805
Short name T590
Test name
Test status
Simulation time 20952867 ps
CPU time 0.63 seconds
Started Jul 24 05:08:04 PM PDT 24
Finished Jul 24 05:08:04 PM PDT 24
Peak memory 199112 kb
Host smart-b529f24b-3a46-4d21-a1a1-f1df861e4137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406122805 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_aborted_low_power.406122805
Directory /workspace/21.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/21.pwrmgr_disable_rom_integrity_check.246607625
Short name T429
Test name
Test status
Simulation time 81372356 ps
CPU time 0.64 seconds
Started Jul 24 05:07:57 PM PDT 24
Finished Jul 24 05:07:58 PM PDT 24
Peak memory 199488 kb
Host smart-fec37082-9171-4f56-b64b-15018aa6839f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246607625 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_disa
ble_rom_integrity_check.246607625
Directory /workspace/21.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/21.pwrmgr_esc_clk_rst_malfunc.1625453267
Short name T265
Test name
Test status
Simulation time 37403159 ps
CPU time 0.58 seconds
Started Jul 24 05:07:55 PM PDT 24
Finished Jul 24 05:07:56 PM PDT 24
Peak memory 198476 kb
Host smart-150b5d22-6065-4efc-a10f-3417350ff49b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625453267 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_esc_clk_rst
_malfunc.1625453267
Directory /workspace/21.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/21.pwrmgr_escalation_timeout.832222753
Short name T455
Test name
Test status
Simulation time 326490003 ps
CPU time 0.93 seconds
Started Jul 24 05:08:18 PM PDT 24
Finished Jul 24 05:08:19 PM PDT 24
Peak memory 198600 kb
Host smart-411546d2-a5dd-45e6-8049-7b7be1bb0421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832222753 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_escalation_timeout.832222753
Directory /workspace/21.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/21.pwrmgr_glitch.836239466
Short name T216
Test name
Test status
Simulation time 123152626 ps
CPU time 0.56 seconds
Started Jul 24 05:07:47 PM PDT 24
Finished Jul 24 05:07:48 PM PDT 24
Peak memory 198568 kb
Host smart-68d4252f-4775-4ef8-813f-434b1cb0f47e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836239466 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_glitch.836239466
Directory /workspace/21.pwrmgr_glitch/latest

Test location /workspace/coverage/default/21.pwrmgr_global_esc.3033058832
Short name T487
Test name
Test status
Simulation time 48154811 ps
CPU time 0.65 seconds
Started Jul 24 05:08:12 PM PDT 24
Finished Jul 24 05:08:13 PM PDT 24
Peak memory 197876 kb
Host smart-4563f674-f34d-4176-803a-5d9b46e19f18
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033058832 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_global_esc.3033058832
Directory /workspace/21.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/21.pwrmgr_lowpower_invalid.1275248348
Short name T181
Test name
Test status
Simulation time 57557933 ps
CPU time 0.7 seconds
Started Jul 24 05:07:50 PM PDT 24
Finished Jul 24 05:07:50 PM PDT 24
Peak memory 201968 kb
Host smart-2e4da906-fea8-4691-b664-11e5652bdfb1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275248348 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_lowpower_inval
id.1275248348
Directory /workspace/21.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/21.pwrmgr_reset.2331275340
Short name T292
Test name
Test status
Simulation time 257485022 ps
CPU time 0.71 seconds
Started Jul 24 05:08:14 PM PDT 24
Finished Jul 24 05:08:15 PM PDT 24
Peak memory 198820 kb
Host smart-71262a8c-347b-4961-a876-23dc67bf0708
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331275340 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset.2331275340
Directory /workspace/21.pwrmgr_reset/latest

Test location /workspace/coverage/default/21.pwrmgr_reset_invalid.4105389709
Short name T618
Test name
Test status
Simulation time 113192196 ps
CPU time 1.05 seconds
Started Jul 24 05:08:08 PM PDT 24
Finished Jul 24 05:08:10 PM PDT 24
Peak memory 210012 kb
Host smart-42456098-ebdb-4106-a510-4a348f2c6d05
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105389709 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset_invalid.4105389709
Directory /workspace/21.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/21.pwrmgr_sec_cm_rstmgr_intersig_mubi.3812751720
Short name T501
Test name
Test status
Simulation time 176997586 ps
CPU time 0.88 seconds
Started Jul 24 05:08:05 PM PDT 24
Finished Jul 24 05:08:06 PM PDT 24
Peak memory 199940 kb
Host smart-90f9eb5b-2d4a-42b4-9c0a-0ec61c4d07b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812751720 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3812751720
Directory /workspace/21.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/21.pwrmgr_smoke.3114068279
Short name T431
Test name
Test status
Simulation time 35604508 ps
CPU time 0.66 seconds
Started Jul 24 05:08:20 PM PDT 24
Finished Jul 24 05:08:21 PM PDT 24
Peak memory 199072 kb
Host smart-d5812ddf-b831-4c58-a3e3-4e167726929c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114068279 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_smoke.3114068279
Directory /workspace/21.pwrmgr_smoke/latest

Test location /workspace/coverage/default/22.pwrmgr_aborted_low_power.4282905249
Short name T523
Test name
Test status
Simulation time 75667140 ps
CPU time 0.88 seconds
Started Jul 24 05:08:04 PM PDT 24
Finished Jul 24 05:08:10 PM PDT 24
Peak memory 200528 kb
Host smart-baf295e3-2223-4900-b21f-3da119a5760c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282905249 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_aborted_low_power.4282905249
Directory /workspace/22.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/22.pwrmgr_esc_clk_rst_malfunc.1382468431
Short name T391
Test name
Test status
Simulation time 29859093 ps
CPU time 0.63 seconds
Started Jul 24 05:08:00 PM PDT 24
Finished Jul 24 05:08:01 PM PDT 24
Peak memory 198440 kb
Host smart-6e9b2e90-dd9d-4127-b6af-1ace87a29898
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382468431 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_esc_clk_rst
_malfunc.1382468431
Directory /workspace/22.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/22.pwrmgr_escalation_timeout.2193097493
Short name T369
Test name
Test status
Simulation time 627765680 ps
CPU time 0.93 seconds
Started Jul 24 05:08:15 PM PDT 24
Finished Jul 24 05:08:16 PM PDT 24
Peak memory 198664 kb
Host smart-2fdf37ff-94d0-452e-b48c-2163fea0ac53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193097493 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_escalation_timeout.2193097493
Directory /workspace/22.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/22.pwrmgr_glitch.2663073365
Short name T261
Test name
Test status
Simulation time 192972437 ps
CPU time 0.62 seconds
Started Jul 24 05:08:09 PM PDT 24
Finished Jul 24 05:08:10 PM PDT 24
Peak memory 198488 kb
Host smart-c93a4cc2-0264-466f-8228-a27d01b7158a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663073365 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_glitch.2663073365
Directory /workspace/22.pwrmgr_glitch/latest

Test location /workspace/coverage/default/22.pwrmgr_global_esc.1491936754
Short name T441
Test name
Test status
Simulation time 74061573 ps
CPU time 0.59 seconds
Started Jul 24 05:08:12 PM PDT 24
Finished Jul 24 05:08:13 PM PDT 24
Peak memory 198648 kb
Host smart-4d141565-3564-4712-8b5c-4a6d48ec7ee7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491936754 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_global_esc.1491936754
Directory /workspace/22.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/22.pwrmgr_reset.1456225867
Short name T230
Test name
Test status
Simulation time 42992028 ps
CPU time 0.66 seconds
Started Jul 24 05:08:11 PM PDT 24
Finished Jul 24 05:08:12 PM PDT 24
Peak memory 198944 kb
Host smart-6fda717c-c183-408a-85ce-2cb90973ad21
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456225867 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset.1456225867
Directory /workspace/22.pwrmgr_reset/latest

Test location /workspace/coverage/default/22.pwrmgr_reset_invalid.3086946887
Short name T483
Test name
Test status
Simulation time 120789226 ps
CPU time 0.83 seconds
Started Jul 24 05:08:02 PM PDT 24
Finished Jul 24 05:08:03 PM PDT 24
Peak memory 201872 kb
Host smart-b87c1f33-5904-413f-b0e8-29218f61ac18
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086946887 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset_invalid.3086946887
Directory /workspace/22.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/22.pwrmgr_sec_cm_rstmgr_intersig_mubi.1277898856
Short name T218
Test name
Test status
Simulation time 62190819 ps
CPU time 0.76 seconds
Started Jul 24 05:07:58 PM PDT 24
Finished Jul 24 05:07:59 PM PDT 24
Peak memory 198624 kb
Host smart-ac6200cd-b41b-4e1d-8199-ae22e8034784
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277898856 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1277898856
Directory /workspace/22.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/22.pwrmgr_smoke.644452677
Short name T537
Test name
Test status
Simulation time 65934452 ps
CPU time 0.68 seconds
Started Jul 24 05:07:43 PM PDT 24
Finished Jul 24 05:07:44 PM PDT 24
Peak memory 199080 kb
Host smart-d3175720-5ba0-4cc9-98cc-7f523c15ed3c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644452677 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_smoke.644452677
Directory /workspace/22.pwrmgr_smoke/latest

Test location /workspace/coverage/default/23.pwrmgr_disable_rom_integrity_check.2129322034
Short name T190
Test name
Test status
Simulation time 50026903 ps
CPU time 0.8 seconds
Started Jul 24 05:08:04 PM PDT 24
Finished Jul 24 05:08:05 PM PDT 24
Peak memory 199640 kb
Host smart-0537a2c1-2266-4dd6-b60f-f66c9002bd2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129322034 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_dis
able_rom_integrity_check.2129322034
Directory /workspace/23.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/23.pwrmgr_esc_clk_rst_malfunc.767847056
Short name T432
Test name
Test status
Simulation time 31487727 ps
CPU time 0.62 seconds
Started Jul 24 05:08:22 PM PDT 24
Finished Jul 24 05:08:22 PM PDT 24
Peak memory 198520 kb
Host smart-60db61d6-ad3e-44f2-8db9-0455e620a77f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767847056 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_esc_clk_rst_
malfunc.767847056
Directory /workspace/23.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/23.pwrmgr_glitch.2546426589
Short name T233
Test name
Test status
Simulation time 43669020 ps
CPU time 0.64 seconds
Started Jul 24 05:08:14 PM PDT 24
Finished Jul 24 05:08:15 PM PDT 24
Peak memory 198648 kb
Host smart-ad0a1f66-e1d6-4c06-8dc3-de85c1e15d84
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546426589 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_glitch.2546426589
Directory /workspace/23.pwrmgr_glitch/latest

Test location /workspace/coverage/default/23.pwrmgr_global_esc.120510465
Short name T215
Test name
Test status
Simulation time 44123805 ps
CPU time 0.61 seconds
Started Jul 24 05:07:55 PM PDT 24
Finished Jul 24 05:07:55 PM PDT 24
Peak memory 198636 kb
Host smart-1fe77e79-6e82-4a36-aef7-4e216693d12f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120510465 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_global_esc.120510465
Directory /workspace/23.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/23.pwrmgr_reset.3622265282
Short name T280
Test name
Test status
Simulation time 120193809 ps
CPU time 0.73 seconds
Started Jul 24 05:08:08 PM PDT 24
Finished Jul 24 05:08:14 PM PDT 24
Peak memory 198932 kb
Host smart-19a4f256-e577-4d68-adec-baca9d70e0a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622265282 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset.3622265282
Directory /workspace/23.pwrmgr_reset/latest

Test location /workspace/coverage/default/23.pwrmgr_reset_invalid.132282267
Short name T337
Test name
Test status
Simulation time 105706798 ps
CPU time 0.95 seconds
Started Jul 24 05:07:58 PM PDT 24
Finished Jul 24 05:08:00 PM PDT 24
Peak memory 209980 kb
Host smart-249a7d3d-20a6-4fa0-af2e-fb1eed44be7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132282267 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset_invalid.132282267
Directory /workspace/23.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/23.pwrmgr_sec_cm_rstmgr_intersig_mubi.3406581306
Short name T557
Test name
Test status
Simulation time 54797204 ps
CPU time 0.85 seconds
Started Jul 24 05:08:22 PM PDT 24
Finished Jul 24 05:08:23 PM PDT 24
Peak memory 198620 kb
Host smart-516cd63a-bbed-4cfc-aa57-1c07127c0c8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406581306 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3406581306
Directory /workspace/23.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/23.pwrmgr_smoke.798893347
Short name T94
Test name
Test status
Simulation time 29583528 ps
CPU time 0.66 seconds
Started Jul 24 05:07:59 PM PDT 24
Finished Jul 24 05:08:00 PM PDT 24
Peak memory 199912 kb
Host smart-0baf7a93-d41b-45ee-a009-baed27c922a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798893347 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_smoke.798893347
Directory /workspace/23.pwrmgr_smoke/latest

Test location /workspace/coverage/default/23.pwrmgr_stress_all.2428666105
Short name T325
Test name
Test status
Simulation time 122560766 ps
CPU time 1.03 seconds
Started Jul 24 05:07:56 PM PDT 24
Finished Jul 24 05:07:57 PM PDT 24
Peak memory 200976 kb
Host smart-fea625f8-eef8-4471-a2fa-a8157ebfed3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428666105 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_stress_all.2428666105
Directory /workspace/23.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/24.pwrmgr_aborted_low_power.475005590
Short name T430
Test name
Test status
Simulation time 59522317 ps
CPU time 0.63 seconds
Started Jul 24 05:08:03 PM PDT 24
Finished Jul 24 05:08:04 PM PDT 24
Peak memory 199732 kb
Host smart-3a74c159-912e-423c-8b7c-55b18751c590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475005590 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_aborted_low_power.475005590
Directory /workspace/24.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/24.pwrmgr_esc_clk_rst_malfunc.503298598
Short name T295
Test name
Test status
Simulation time 40781498 ps
CPU time 0.59 seconds
Started Jul 24 05:08:04 PM PDT 24
Finished Jul 24 05:08:05 PM PDT 24
Peak memory 197888 kb
Host smart-02386698-0c0b-4940-b6c7-a7946b074131
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503298598 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_esc_clk_rst_
malfunc.503298598
Directory /workspace/24.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/24.pwrmgr_escalation_timeout.3612904540
Short name T358
Test name
Test status
Simulation time 1251639060 ps
CPU time 0.97 seconds
Started Jul 24 05:08:19 PM PDT 24
Finished Jul 24 05:08:20 PM PDT 24
Peak memory 198180 kb
Host smart-74481ecc-c349-48ef-9e9e-d553778dc9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612904540 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_escalation_timeout.3612904540
Directory /workspace/24.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/24.pwrmgr_glitch.3122342673
Short name T446
Test name
Test status
Simulation time 30196725 ps
CPU time 0.62 seconds
Started Jul 24 05:08:05 PM PDT 24
Finished Jul 24 05:08:05 PM PDT 24
Peak memory 198656 kb
Host smart-0f1bcc1f-88ce-4eb2-b940-0a5cc3634cf4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122342673 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_glitch.3122342673
Directory /workspace/24.pwrmgr_glitch/latest

Test location /workspace/coverage/default/24.pwrmgr_global_esc.1278327470
Short name T475
Test name
Test status
Simulation time 59737768 ps
CPU time 0.59 seconds
Started Jul 24 05:08:00 PM PDT 24
Finished Jul 24 05:08:01 PM PDT 24
Peak memory 198952 kb
Host smart-37ed6781-0d5c-40ee-96e8-fd0b4c2aa517
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278327470 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_global_esc.1278327470
Directory /workspace/24.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/24.pwrmgr_lowpower_invalid.1548629359
Short name T146
Test name
Test status
Simulation time 43568419 ps
CPU time 0.73 seconds
Started Jul 24 05:08:27 PM PDT 24
Finished Jul 24 05:08:28 PM PDT 24
Peak memory 201908 kb
Host smart-37cf8c15-eadc-4c13-ac52-2c6d8ac67d81
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548629359 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_lowpower_inval
id.1548629359
Directory /workspace/24.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/24.pwrmgr_reset.2880928034
Short name T594
Test name
Test status
Simulation time 59740775 ps
CPU time 0.81 seconds
Started Jul 24 05:08:21 PM PDT 24
Finished Jul 24 05:08:22 PM PDT 24
Peak memory 198824 kb
Host smart-101205b0-07f0-4dff-a79a-ca848852495f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880928034 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset.2880928034
Directory /workspace/24.pwrmgr_reset/latest

Test location /workspace/coverage/default/24.pwrmgr_reset_invalid.3806909705
Short name T565
Test name
Test status
Simulation time 158964101 ps
CPU time 0.78 seconds
Started Jul 24 05:08:12 PM PDT 24
Finished Jul 24 05:08:14 PM PDT 24
Peak memory 209976 kb
Host smart-a87c7ad7-88af-4552-a770-b154f756e203
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806909705 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset_invalid.3806909705
Directory /workspace/24.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/24.pwrmgr_sec_cm_rstmgr_intersig_mubi.1576189631
Short name T3
Test name
Test status
Simulation time 64211685 ps
CPU time 0.85 seconds
Started Jul 24 05:08:14 PM PDT 24
Finished Jul 24 05:08:15 PM PDT 24
Peak memory 199764 kb
Host smart-0fa969d2-a540-495a-864c-fa5ca946b532
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576189631 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1576189631
Directory /workspace/24.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/24.pwrmgr_smoke.547678845
Short name T525
Test name
Test status
Simulation time 234939340 ps
CPU time 0.63 seconds
Started Jul 24 05:07:56 PM PDT 24
Finished Jul 24 05:07:57 PM PDT 24
Peak memory 199052 kb
Host smart-ffe41eaf-9c2d-439d-9ed5-77d7cd96e072
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547678845 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_smoke.547678845
Directory /workspace/24.pwrmgr_smoke/latest

Test location /workspace/coverage/default/25.pwrmgr_aborted_low_power.1855237035
Short name T363
Test name
Test status
Simulation time 172410898 ps
CPU time 0.82 seconds
Started Jul 24 05:08:16 PM PDT 24
Finished Jul 24 05:08:17 PM PDT 24
Peak memory 200588 kb
Host smart-94b23af5-9a0d-4a55-95d8-e333e4d02170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855237035 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_aborted_low_power.1855237035
Directory /workspace/25.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/25.pwrmgr_disable_rom_integrity_check.762881852
Short name T449
Test name
Test status
Simulation time 67577088 ps
CPU time 0.63 seconds
Started Jul 24 05:08:10 PM PDT 24
Finished Jul 24 05:08:11 PM PDT 24
Peak memory 198888 kb
Host smart-27d4494e-2582-4783-bbc4-2530a84019b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762881852 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_disa
ble_rom_integrity_check.762881852
Directory /workspace/25.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/25.pwrmgr_esc_clk_rst_malfunc.3094452033
Short name T479
Test name
Test status
Simulation time 33174628 ps
CPU time 0.6 seconds
Started Jul 24 05:08:01 PM PDT 24
Finished Jul 24 05:08:02 PM PDT 24
Peak memory 198464 kb
Host smart-0ced68cb-43e7-41c3-8912-1bc112793c75
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094452033 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_esc_clk_rst
_malfunc.3094452033
Directory /workspace/25.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/25.pwrmgr_escalation_timeout.62991977
Short name T583
Test name
Test status
Simulation time 231336587 ps
CPU time 0.94 seconds
Started Jul 24 05:08:19 PM PDT 24
Finished Jul 24 05:08:20 PM PDT 24
Peak memory 198200 kb
Host smart-92398a15-6e31-4a03-aa1b-62ddb711ba0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62991977 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_escalation_timeout.62991977
Directory /workspace/25.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/25.pwrmgr_glitch.1928049289
Short name T448
Test name
Test status
Simulation time 32377241 ps
CPU time 0.63 seconds
Started Jul 24 05:08:22 PM PDT 24
Finished Jul 24 05:08:23 PM PDT 24
Peak memory 198672 kb
Host smart-783a47b8-cefd-4d2b-8484-18bcfe2205c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928049289 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_glitch.1928049289
Directory /workspace/25.pwrmgr_glitch/latest

Test location /workspace/coverage/default/25.pwrmgr_global_esc.691231717
Short name T219
Test name
Test status
Simulation time 31288086 ps
CPU time 0.62 seconds
Started Jul 24 05:08:08 PM PDT 24
Finished Jul 24 05:08:09 PM PDT 24
Peak memory 198552 kb
Host smart-d4695335-5961-4bc2-a104-91bc14e8c49f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691231717 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_global_esc.691231717
Directory /workspace/25.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/25.pwrmgr_lowpower_invalid.3661253962
Short name T585
Test name
Test status
Simulation time 41641387 ps
CPU time 0.72 seconds
Started Jul 24 05:08:01 PM PDT 24
Finished Jul 24 05:08:02 PM PDT 24
Peak memory 201812 kb
Host smart-2208b0c8-256f-4473-92b0-3617e1862215
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661253962 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_lowpower_inval
id.3661253962
Directory /workspace/25.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/25.pwrmgr_reset.843870260
Short name T321
Test name
Test status
Simulation time 64921165 ps
CPU time 0.83 seconds
Started Jul 24 05:08:07 PM PDT 24
Finished Jul 24 05:08:08 PM PDT 24
Peak memory 199728 kb
Host smart-2664fcf2-3e75-47b9-a653-76dfb8881cca
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843870260 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset.843870260
Directory /workspace/25.pwrmgr_reset/latest

Test location /workspace/coverage/default/25.pwrmgr_reset_invalid.1855872479
Short name T570
Test name
Test status
Simulation time 111437518 ps
CPU time 0.94 seconds
Started Jul 24 05:08:31 PM PDT 24
Finished Jul 24 05:08:32 PM PDT 24
Peak memory 209956 kb
Host smart-27dfc007-a113-4ed2-8e6a-71f1c6c5046f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855872479 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset_invalid.1855872479
Directory /workspace/25.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/25.pwrmgr_sec_cm_rstmgr_intersig_mubi.930951561
Short name T315
Test name
Test status
Simulation time 112902657 ps
CPU time 0.75 seconds
Started Jul 24 05:08:12 PM PDT 24
Finished Jul 24 05:08:14 PM PDT 24
Peak memory 198556 kb
Host smart-bcd87a5c-9b4a-4e27-aa25-b77114a6dd24
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930951561 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_rstmgr_intersig_
mubi.930951561
Directory /workspace/25.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/25.pwrmgr_smoke.1201728265
Short name T388
Test name
Test status
Simulation time 46480179 ps
CPU time 0.63 seconds
Started Jul 24 05:08:10 PM PDT 24
Finished Jul 24 05:08:11 PM PDT 24
Peak memory 199876 kb
Host smart-c9f6fe0b-ba2c-44a6-bd69-7ee7fcd5bf21
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201728265 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_smoke.1201728265
Directory /workspace/25.pwrmgr_smoke/latest

Test location /workspace/coverage/default/25.pwrmgr_wakeup.48775610
Short name T209
Test name
Test status
Simulation time 74795152 ps
CPU time 0.61 seconds
Started Jul 24 05:08:12 PM PDT 24
Finished Jul 24 05:08:13 PM PDT 24
Peak memory 198768 kb
Host smart-f6160fd7-a7ef-47da-bfb3-0038ec62fe0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48775610 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_wakeup.48775610
Directory /workspace/25.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/26.pwrmgr_aborted_low_power.2960948608
Short name T13
Test name
Test status
Simulation time 37916660 ps
CPU time 0.78 seconds
Started Jul 24 05:08:16 PM PDT 24
Finished Jul 24 05:08:17 PM PDT 24
Peak memory 200628 kb
Host smart-5b89525c-f211-46ef-9cc7-2256e69f2634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960948608 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_aborted_low_power.2960948608
Directory /workspace/26.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/26.pwrmgr_disable_rom_integrity_check.3680811933
Short name T385
Test name
Test status
Simulation time 79292363 ps
CPU time 0.67 seconds
Started Jul 24 05:08:12 PM PDT 24
Finished Jul 24 05:08:13 PM PDT 24
Peak memory 198684 kb
Host smart-ab3d2938-79f0-4c2a-9016-884ed61e21fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680811933 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_dis
able_rom_integrity_check.3680811933
Directory /workspace/26.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/26.pwrmgr_esc_clk_rst_malfunc.1772886919
Short name T368
Test name
Test status
Simulation time 31934269 ps
CPU time 0.6 seconds
Started Jul 24 05:08:20 PM PDT 24
Finished Jul 24 05:08:20 PM PDT 24
Peak memory 197792 kb
Host smart-c172b0dd-e7d5-4cc9-83b0-b721b6b1e68e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772886919 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_esc_clk_rst
_malfunc.1772886919
Directory /workspace/26.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/26.pwrmgr_escalation_timeout.2790241038
Short name T415
Test name
Test status
Simulation time 897692185 ps
CPU time 0.96 seconds
Started Jul 24 05:08:19 PM PDT 24
Finished Jul 24 05:08:20 PM PDT 24
Peak memory 198948 kb
Host smart-70c516e8-a538-4dce-a293-96c5e2fa6275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790241038 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_escalation_timeout.2790241038
Directory /workspace/26.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/26.pwrmgr_glitch.2053327094
Short name T304
Test name
Test status
Simulation time 66559001 ps
CPU time 0.59 seconds
Started Jul 24 05:08:11 PM PDT 24
Finished Jul 24 05:08:12 PM PDT 24
Peak memory 198620 kb
Host smart-bb46ee8e-1240-4dc9-a784-97ab06175fb1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053327094 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_glitch.2053327094
Directory /workspace/26.pwrmgr_glitch/latest

Test location /workspace/coverage/default/26.pwrmgr_global_esc.4239585265
Short name T490
Test name
Test status
Simulation time 58502730 ps
CPU time 0.59 seconds
Started Jul 24 05:08:04 PM PDT 24
Finished Jul 24 05:08:05 PM PDT 24
Peak memory 198476 kb
Host smart-c37da916-9b2e-4a99-9980-41838d932937
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239585265 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_global_esc.4239585265
Directory /workspace/26.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/26.pwrmgr_lowpower_invalid.3311426099
Short name T405
Test name
Test status
Simulation time 69419077 ps
CPU time 0.66 seconds
Started Jul 24 05:08:29 PM PDT 24
Finished Jul 24 05:08:29 PM PDT 24
Peak memory 201876 kb
Host smart-17151a72-23da-4b54-b6a0-884d38b2942d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311426099 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_lowpower_inval
id.3311426099
Directory /workspace/26.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/26.pwrmgr_reset.3113175463
Short name T482
Test name
Test status
Simulation time 48047664 ps
CPU time 0.72 seconds
Started Jul 24 05:08:07 PM PDT 24
Finished Jul 24 05:08:08 PM PDT 24
Peak memory 198936 kb
Host smart-aa630a4b-59b0-46cb-be80-8e7fc880a5ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113175463 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset.3113175463
Directory /workspace/26.pwrmgr_reset/latest

Test location /workspace/coverage/default/26.pwrmgr_reset_invalid.312723123
Short name T338
Test name
Test status
Simulation time 156972951 ps
CPU time 0.81 seconds
Started Jul 24 05:08:29 PM PDT 24
Finished Jul 24 05:08:30 PM PDT 24
Peak memory 210152 kb
Host smart-57dc3464-1067-40e6-b14a-1060c7acfd40
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312723123 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset_invalid.312723123
Directory /workspace/26.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/26.pwrmgr_sec_cm_rstmgr_intersig_mubi.2605498403
Short name T223
Test name
Test status
Simulation time 75329003 ps
CPU time 0.71 seconds
Started Jul 24 05:08:15 PM PDT 24
Finished Jul 24 05:08:16 PM PDT 24
Peak memory 198512 kb
Host smart-4a1ad332-5b38-4ede-8b8e-ca9c6800a7f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605498403 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2605498403
Directory /workspace/26.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/26.pwrmgr_smoke.619328212
Short name T285
Test name
Test status
Simulation time 31479856 ps
CPU time 0.66 seconds
Started Jul 24 05:07:56 PM PDT 24
Finished Jul 24 05:07:57 PM PDT 24
Peak memory 199864 kb
Host smart-46220bd5-24d0-40d1-9dc3-2ac81d9e0a49
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619328212 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_smoke.619328212
Directory /workspace/26.pwrmgr_smoke/latest

Test location /workspace/coverage/default/27.pwrmgr_aborted_low_power.2338419282
Short name T562
Test name
Test status
Simulation time 27282216 ps
CPU time 0.71 seconds
Started Jul 24 05:08:27 PM PDT 24
Finished Jul 24 05:08:28 PM PDT 24
Peak memory 199124 kb
Host smart-71ba4a42-50b5-4849-b71e-4d42ce895cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338419282 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_aborted_low_power.2338419282
Directory /workspace/27.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/27.pwrmgr_disable_rom_integrity_check.1154285930
Short name T193
Test name
Test status
Simulation time 60960349 ps
CPU time 0.69 seconds
Started Jul 24 05:08:26 PM PDT 24
Finished Jul 24 05:08:27 PM PDT 24
Peak memory 199592 kb
Host smart-67d94e96-75e0-4b9d-9f4b-a7a699fe82a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154285930 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_dis
able_rom_integrity_check.1154285930
Directory /workspace/27.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/27.pwrmgr_esc_clk_rst_malfunc.1056272631
Short name T284
Test name
Test status
Simulation time 31173039 ps
CPU time 0.59 seconds
Started Jul 24 05:08:27 PM PDT 24
Finished Jul 24 05:08:28 PM PDT 24
Peak memory 198592 kb
Host smart-4172180f-9cb2-45b4-9bc8-3f522371bead
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056272631 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_esc_clk_rst
_malfunc.1056272631
Directory /workspace/27.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/27.pwrmgr_escalation_timeout.1222943363
Short name T421
Test name
Test status
Simulation time 319187632 ps
CPU time 0.94 seconds
Started Jul 24 05:08:08 PM PDT 24
Finished Jul 24 05:08:09 PM PDT 24
Peak memory 198548 kb
Host smart-626e6fac-23a1-46b6-80b2-8c91edc6d80c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222943363 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_escalation_timeout.1222943363
Directory /workspace/27.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/27.pwrmgr_glitch.2120088731
Short name T266
Test name
Test status
Simulation time 59149768 ps
CPU time 0.62 seconds
Started Jul 24 05:08:32 PM PDT 24
Finished Jul 24 05:08:32 PM PDT 24
Peak memory 198552 kb
Host smart-21e3ba10-71ce-4792-b20b-d49c05186767
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120088731 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_glitch.2120088731
Directory /workspace/27.pwrmgr_glitch/latest

Test location /workspace/coverage/default/27.pwrmgr_global_esc.2957744059
Short name T400
Test name
Test status
Simulation time 45418659 ps
CPU time 0.63 seconds
Started Jul 24 05:08:25 PM PDT 24
Finished Jul 24 05:08:26 PM PDT 24
Peak memory 198580 kb
Host smart-25a11ea9-8b99-4578-bab6-542ea6544ba8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957744059 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_global_esc.2957744059
Directory /workspace/27.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/27.pwrmgr_lowpower_invalid.849379886
Short name T546
Test name
Test status
Simulation time 70729733 ps
CPU time 0.64 seconds
Started Jul 24 05:08:21 PM PDT 24
Finished Jul 24 05:08:22 PM PDT 24
Peak memory 201964 kb
Host smart-e0da21be-1ba7-4263-87ef-c5f20864e5e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849379886 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_lowpower_invali
d.849379886
Directory /workspace/27.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/27.pwrmgr_reset.2592164883
Short name T251
Test name
Test status
Simulation time 34516293 ps
CPU time 0.61 seconds
Started Jul 24 05:08:07 PM PDT 24
Finished Jul 24 05:08:09 PM PDT 24
Peak memory 198696 kb
Host smart-f7ad112a-c463-463c-a658-2b0077c2f5e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592164883 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset.2592164883
Directory /workspace/27.pwrmgr_reset/latest

Test location /workspace/coverage/default/27.pwrmgr_reset_invalid.338508961
Short name T234
Test name
Test status
Simulation time 193621440 ps
CPU time 0.77 seconds
Started Jul 24 05:08:28 PM PDT 24
Finished Jul 24 05:08:29 PM PDT 24
Peak memory 209936 kb
Host smart-1ce9f262-82ea-4b6b-aabf-a26013ce9316
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338508961 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset_invalid.338508961
Directory /workspace/27.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/27.pwrmgr_sec_cm_rstmgr_intersig_mubi.1035858760
Short name T336
Test name
Test status
Simulation time 107840036 ps
CPU time 0.81 seconds
Started Jul 24 05:08:07 PM PDT 24
Finished Jul 24 05:08:08 PM PDT 24
Peak memory 199800 kb
Host smart-9d2e5002-50e4-47de-bc05-46f37aea696e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035858760 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1035858760
Directory /workspace/27.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/27.pwrmgr_smoke.2692407604
Short name T332
Test name
Test status
Simulation time 77797396 ps
CPU time 0.65 seconds
Started Jul 24 05:08:32 PM PDT 24
Finished Jul 24 05:08:33 PM PDT 24
Peak memory 198888 kb
Host smart-e821337d-911a-476e-a168-e2186a887cb3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692407604 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_smoke.2692407604
Directory /workspace/27.pwrmgr_smoke/latest

Test location /workspace/coverage/default/28.pwrmgr_aborted_low_power.3803766997
Short name T529
Test name
Test status
Simulation time 46817304 ps
CPU time 0.66 seconds
Started Jul 24 05:08:32 PM PDT 24
Finished Jul 24 05:08:33 PM PDT 24
Peak memory 199056 kb
Host smart-c605113e-e2aa-4432-8b3e-43589dd8111b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803766997 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_aborted_low_power.3803766997
Directory /workspace/28.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/28.pwrmgr_esc_clk_rst_malfunc.1774826239
Short name T362
Test name
Test status
Simulation time 39082346 ps
CPU time 0.59 seconds
Started Jul 24 05:08:26 PM PDT 24
Finished Jul 24 05:08:26 PM PDT 24
Peak memory 198496 kb
Host smart-397a495b-0a41-41da-b403-236f019acb77
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774826239 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_esc_clk_rst
_malfunc.1774826239
Directory /workspace/28.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/28.pwrmgr_escalation_timeout.1048292452
Short name T544
Test name
Test status
Simulation time 326798157 ps
CPU time 0.98 seconds
Started Jul 24 05:08:39 PM PDT 24
Finished Jul 24 05:08:40 PM PDT 24
Peak memory 198560 kb
Host smart-dbead3d5-0b83-40fc-895d-ccdc97d57777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048292452 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_escalation_timeout.1048292452
Directory /workspace/28.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/28.pwrmgr_glitch.626403605
Short name T548
Test name
Test status
Simulation time 78656769 ps
CPU time 0.6 seconds
Started Jul 24 05:08:46 PM PDT 24
Finished Jul 24 05:08:47 PM PDT 24
Peak memory 197960 kb
Host smart-8a536e93-d94a-4557-9206-f3ec0c5d76e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626403605 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_glitch.626403605
Directory /workspace/28.pwrmgr_glitch/latest

Test location /workspace/coverage/default/28.pwrmgr_global_esc.664108965
Short name T419
Test name
Test status
Simulation time 84991380 ps
CPU time 0.59 seconds
Started Jul 24 05:08:26 PM PDT 24
Finished Jul 24 05:08:27 PM PDT 24
Peak memory 198896 kb
Host smart-8d41cac8-d5e2-46b5-a533-89a857365202
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664108965 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_global_esc.664108965
Directory /workspace/28.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/28.pwrmgr_lowpower_invalid.1652029305
Short name T167
Test name
Test status
Simulation time 46928977 ps
CPU time 0.7 seconds
Started Jul 24 05:08:31 PM PDT 24
Finished Jul 24 05:08:32 PM PDT 24
Peak memory 201944 kb
Host smart-a9e5518e-c6b3-4851-8f8c-59cd32aacc4e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652029305 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_lowpower_inval
id.1652029305
Directory /workspace/28.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/28.pwrmgr_reset.344688383
Short name T461
Test name
Test status
Simulation time 79454110 ps
CPU time 0.89 seconds
Started Jul 24 05:08:26 PM PDT 24
Finished Jul 24 05:08:28 PM PDT 24
Peak memory 198992 kb
Host smart-935334cb-15a8-4871-a8f6-21b9e2f2596c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344688383 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset.344688383
Directory /workspace/28.pwrmgr_reset/latest

Test location /workspace/coverage/default/28.pwrmgr_reset_invalid.545746783
Short name T373
Test name
Test status
Simulation time 114984327 ps
CPU time 0.86 seconds
Started Jul 24 05:08:28 PM PDT 24
Finished Jul 24 05:08:30 PM PDT 24
Peak memory 210064 kb
Host smart-b0d85990-b91e-4d05-a797-35020308bb78
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545746783 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset_invalid.545746783
Directory /workspace/28.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/28.pwrmgr_sec_cm_rstmgr_intersig_mubi.1858539877
Short name T314
Test name
Test status
Simulation time 105723161 ps
CPU time 0.67 seconds
Started Jul 24 05:08:31 PM PDT 24
Finished Jul 24 05:08:32 PM PDT 24
Peak memory 198796 kb
Host smart-a22088d6-a707-498d-a3d0-6104777795a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858539877 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1858539877
Directory /workspace/28.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/28.pwrmgr_smoke.2881823929
Short name T250
Test name
Test status
Simulation time 29318339 ps
CPU time 0.71 seconds
Started Jul 24 05:08:25 PM PDT 24
Finished Jul 24 05:08:25 PM PDT 24
Peak memory 199876 kb
Host smart-d1dff2ae-d8dc-4855-be60-f40d009a1dd1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881823929 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_smoke.2881823929
Directory /workspace/28.pwrmgr_smoke/latest

Test location /workspace/coverage/default/29.pwrmgr_aborted_low_power.4003754897
Short name T500
Test name
Test status
Simulation time 35649720 ps
CPU time 0.79 seconds
Started Jul 24 05:08:36 PM PDT 24
Finished Jul 24 05:08:37 PM PDT 24
Peak memory 200476 kb
Host smart-b1df0f0e-bba2-45e6-94ff-dc8df72c1cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003754897 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_aborted_low_power.4003754897
Directory /workspace/29.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/29.pwrmgr_disable_rom_integrity_check.3631503512
Short name T196
Test name
Test status
Simulation time 43199259 ps
CPU time 0.71 seconds
Started Jul 24 05:08:54 PM PDT 24
Finished Jul 24 05:08:55 PM PDT 24
Peak memory 198936 kb
Host smart-5ba06ae1-924f-4c10-a5e7-de505a455c7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631503512 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_dis
able_rom_integrity_check.3631503512
Directory /workspace/29.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/29.pwrmgr_esc_clk_rst_malfunc.50957751
Short name T341
Test name
Test status
Simulation time 30892696 ps
CPU time 0.65 seconds
Started Jul 24 05:08:35 PM PDT 24
Finished Jul 24 05:08:36 PM PDT 24
Peak memory 198576 kb
Host smart-e4d89904-1654-464b-be5f-5c0622130c2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50957751 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_mal
func_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_esc_clk_rst_m
alfunc.50957751
Directory /workspace/29.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/29.pwrmgr_escalation_timeout.1349099843
Short name T327
Test name
Test status
Simulation time 316382605 ps
CPU time 0.98 seconds
Started Jul 24 05:08:40 PM PDT 24
Finished Jul 24 05:08:41 PM PDT 24
Peak memory 198664 kb
Host smart-16d8fd50-afd6-474f-826b-fc75861cc2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349099843 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_escalation_timeout.1349099843
Directory /workspace/29.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/29.pwrmgr_glitch.1380843293
Short name T582
Test name
Test status
Simulation time 72233074 ps
CPU time 0.63 seconds
Started Jul 24 05:08:42 PM PDT 24
Finished Jul 24 05:08:43 PM PDT 24
Peak memory 198552 kb
Host smart-01db5c37-755a-4ad4-8729-7435ca0af9e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380843293 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_glitch.1380843293
Directory /workspace/29.pwrmgr_glitch/latest

Test location /workspace/coverage/default/29.pwrmgr_global_esc.373774999
Short name T460
Test name
Test status
Simulation time 29067496 ps
CPU time 0.6 seconds
Started Jul 24 05:08:25 PM PDT 24
Finished Jul 24 05:08:26 PM PDT 24
Peak memory 198640 kb
Host smart-9882c818-5f47-4c5e-9c5d-db15a5965614
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373774999 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_global_esc.373774999
Directory /workspace/29.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/29.pwrmgr_lowpower_invalid.1330909386
Short name T179
Test name
Test status
Simulation time 57046112 ps
CPU time 0.67 seconds
Started Jul 24 05:08:34 PM PDT 24
Finished Jul 24 05:08:35 PM PDT 24
Peak memory 201992 kb
Host smart-0f841d11-1af0-4299-bcab-0f553194698f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330909386 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_lowpower_inval
id.1330909386
Directory /workspace/29.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/29.pwrmgr_reset.1114297659
Short name T616
Test name
Test status
Simulation time 53751611 ps
CPU time 0.66 seconds
Started Jul 24 05:08:26 PM PDT 24
Finished Jul 24 05:08:32 PM PDT 24
Peak memory 198780 kb
Host smart-01a602d3-1a98-4596-bac7-e97e4a23a8a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114297659 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset.1114297659
Directory /workspace/29.pwrmgr_reset/latest

Test location /workspace/coverage/default/29.pwrmgr_reset_invalid.3750994721
Short name T45
Test name
Test status
Simulation time 170055934 ps
CPU time 0.78 seconds
Started Jul 24 05:09:04 PM PDT 24
Finished Jul 24 05:09:05 PM PDT 24
Peak memory 209940 kb
Host smart-6b72a2ee-178d-439f-88e8-5d5067f3b550
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750994721 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset_invalid.3750994721
Directory /workspace/29.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/29.pwrmgr_sec_cm_rstmgr_intersig_mubi.71820753
Short name T214
Test name
Test status
Simulation time 82073473 ps
CPU time 0.8 seconds
Started Jul 24 05:08:30 PM PDT 24
Finished Jul 24 05:08:31 PM PDT 24
Peak memory 198728 kb
Host smart-3870a2f5-e106-4a9d-9754-70fcdbdad166
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71820753 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.71820753
Directory /workspace/29.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/29.pwrmgr_smoke.1502813639
Short name T386
Test name
Test status
Simulation time 28909930 ps
CPU time 0.65 seconds
Started Jul 24 05:08:22 PM PDT 24
Finished Jul 24 05:08:23 PM PDT 24
Peak memory 199248 kb
Host smart-ca06fc30-0b26-43c7-89f9-990b502cc27f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502813639 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_smoke.1502813639
Directory /workspace/29.pwrmgr_smoke/latest

Test location /workspace/coverage/default/3.pwrmgr_aborted_low_power.3172060044
Short name T36
Test name
Test status
Simulation time 20374166 ps
CPU time 0.63 seconds
Started Jul 24 05:07:33 PM PDT 24
Finished Jul 24 05:07:33 PM PDT 24
Peak memory 199672 kb
Host smart-d6918117-0f9f-45c3-a6f2-61242582fce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172060044 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_aborted_low_power.3172060044
Directory /workspace/3.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/3.pwrmgr_disable_rom_integrity_check.3385245720
Short name T414
Test name
Test status
Simulation time 79470802 ps
CPU time 0.66 seconds
Started Jul 24 05:07:19 PM PDT 24
Finished Jul 24 05:07:20 PM PDT 24
Peak memory 198948 kb
Host smart-34abcfa5-6052-431a-9ace-25bb30756616
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385245720 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_disa
ble_rom_integrity_check.3385245720
Directory /workspace/3.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/3.pwrmgr_esc_clk_rst_malfunc.510701612
Short name T457
Test name
Test status
Simulation time 31191726 ps
CPU time 0.63 seconds
Started Jul 24 05:07:15 PM PDT 24
Finished Jul 24 05:07:16 PM PDT 24
Peak memory 198540 kb
Host smart-ccfc48cb-c363-4d11-8579-b42ec2336b6f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510701612 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_esc_clk_rst_m
alfunc.510701612
Directory /workspace/3.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/3.pwrmgr_escalation_timeout.4159481221
Short name T130
Test name
Test status
Simulation time 626462843 ps
CPU time 0.92 seconds
Started Jul 24 05:07:20 PM PDT 24
Finished Jul 24 05:07:21 PM PDT 24
Peak memory 198596 kb
Host smart-707d88c5-525d-4e1d-b43e-92c3c178ba09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159481221 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_escalation_timeout.4159481221
Directory /workspace/3.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/3.pwrmgr_glitch.1908815219
Short name T395
Test name
Test status
Simulation time 49198423 ps
CPU time 0.62 seconds
Started Jul 24 05:07:25 PM PDT 24
Finished Jul 24 05:07:26 PM PDT 24
Peak memory 198616 kb
Host smart-9d539e84-fd63-40b8-8238-bd7a21a5ffe8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908815219 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_glitch.1908815219
Directory /workspace/3.pwrmgr_glitch/latest

Test location /workspace/coverage/default/3.pwrmgr_global_esc.3757097327
Short name T361
Test name
Test status
Simulation time 61069445 ps
CPU time 0.62 seconds
Started Jul 24 05:07:18 PM PDT 24
Finished Jul 24 05:07:18 PM PDT 24
Peak memory 198564 kb
Host smart-add24b43-936e-4b46-8979-92db22eed2c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757097327 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_global_esc.3757097327
Directory /workspace/3.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/3.pwrmgr_lowpower_invalid.1272526045
Short name T559
Test name
Test status
Simulation time 68619315 ps
CPU time 0.66 seconds
Started Jul 24 05:07:14 PM PDT 24
Finished Jul 24 05:07:15 PM PDT 24
Peak memory 201856 kb
Host smart-8f6e0d84-4824-4728-8e3e-5feb394c4f07
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272526045 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_lowpower_invali
d.1272526045
Directory /workspace/3.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/3.pwrmgr_reset.1808441763
Short name T210
Test name
Test status
Simulation time 86572536 ps
CPU time 0.69 seconds
Started Jul 24 05:07:19 PM PDT 24
Finished Jul 24 05:07:20 PM PDT 24
Peak memory 199496 kb
Host smart-ab4c6b6c-773d-4739-9ce4-bd0fad3d9ea1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808441763 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset.1808441763
Directory /workspace/3.pwrmgr_reset/latest

Test location /workspace/coverage/default/3.pwrmgr_reset_invalid.2556249277
Short name T588
Test name
Test status
Simulation time 104768966 ps
CPU time 0.9 seconds
Started Jul 24 05:07:05 PM PDT 24
Finished Jul 24 05:07:06 PM PDT 24
Peak memory 210052 kb
Host smart-0fa0366f-0298-4321-a633-3b8e1d0d5c86
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556249277 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset_invalid.2556249277
Directory /workspace/3.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm.2811625154
Short name T30
Test name
Test status
Simulation time 674543836 ps
CPU time 2.05 seconds
Started Jul 24 05:07:04 PM PDT 24
Finished Jul 24 05:07:07 PM PDT 24
Peak memory 218452 kb
Host smart-ad21e181-e3b3-4546-9f67-3dc59c3096bb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811625154 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm.2811625154
Directory /workspace/3.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm_rstmgr_intersig_mubi.926234958
Short name T313
Test name
Test status
Simulation time 76297005 ps
CPU time 0.72 seconds
Started Jul 24 05:07:07 PM PDT 24
Finished Jul 24 05:07:08 PM PDT 24
Peak memory 198592 kb
Host smart-d3773587-6fa8-4b18-8a5e-8d20de536af2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926234958 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.926234958
Directory /workspace/3.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/3.pwrmgr_smoke.2469548122
Short name T561
Test name
Test status
Simulation time 32080039 ps
CPU time 0.71 seconds
Started Jul 24 05:07:14 PM PDT 24
Finished Jul 24 05:07:15 PM PDT 24
Peak memory 199896 kb
Host smart-f1607e40-e204-4416-a836-60a0bf07e3a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469548122 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_smoke.2469548122
Directory /workspace/3.pwrmgr_smoke/latest

Test location /workspace/coverage/default/30.pwrmgr_aborted_low_power.1465499712
Short name T581
Test name
Test status
Simulation time 38778019 ps
CPU time 0.76 seconds
Started Jul 24 05:08:25 PM PDT 24
Finished Jul 24 05:08:26 PM PDT 24
Peak memory 199420 kb
Host smart-1398ff6a-6908-48db-a3a1-87fd77477d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465499712 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_aborted_low_power.1465499712
Directory /workspace/30.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/30.pwrmgr_disable_rom_integrity_check.517120344
Short name T471
Test name
Test status
Simulation time 53908637 ps
CPU time 0.74 seconds
Started Jul 24 05:08:37 PM PDT 24
Finished Jul 24 05:08:38 PM PDT 24
Peak memory 199700 kb
Host smart-a12e1c9c-12d4-4ba5-9049-2922741673d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517120344 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_disa
ble_rom_integrity_check.517120344
Directory /workspace/30.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/30.pwrmgr_esc_clk_rst_malfunc.4170826053
Short name T342
Test name
Test status
Simulation time 36369518 ps
CPU time 0.58 seconds
Started Jul 24 05:08:37 PM PDT 24
Finished Jul 24 05:08:38 PM PDT 24
Peak memory 198516 kb
Host smart-e7d33db9-3a1e-42ac-8c72-16df810c7a5b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170826053 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_esc_clk_rst
_malfunc.4170826053
Directory /workspace/30.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/30.pwrmgr_escalation_timeout.546401457
Short name T241
Test name
Test status
Simulation time 324527424 ps
CPU time 0.98 seconds
Started Jul 24 05:08:32 PM PDT 24
Finished Jul 24 05:08:34 PM PDT 24
Peak memory 198592 kb
Host smart-0a7232e8-7c27-4a36-b39e-1b733f5ec050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546401457 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_escalation_timeout.546401457
Directory /workspace/30.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/30.pwrmgr_glitch.3344585384
Short name T236
Test name
Test status
Simulation time 40688166 ps
CPU time 0.61 seconds
Started Jul 24 05:08:33 PM PDT 24
Finished Jul 24 05:08:34 PM PDT 24
Peak memory 198668 kb
Host smart-a092719d-e529-4ca9-8b6e-6ce6033733de
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344585384 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_glitch.3344585384
Directory /workspace/30.pwrmgr_glitch/latest

Test location /workspace/coverage/default/30.pwrmgr_global_esc.522815009
Short name T489
Test name
Test status
Simulation time 52523816 ps
CPU time 0.59 seconds
Started Jul 24 05:09:09 PM PDT 24
Finished Jul 24 05:09:10 PM PDT 24
Peak memory 198656 kb
Host smart-5e547e22-5979-4999-bf3c-4737fc877965
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522815009 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_global_esc.522815009
Directory /workspace/30.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/30.pwrmgr_lowpower_invalid.1672153203
Short name T175
Test name
Test status
Simulation time 43548967 ps
CPU time 0.7 seconds
Started Jul 24 05:08:32 PM PDT 24
Finished Jul 24 05:08:44 PM PDT 24
Peak memory 201904 kb
Host smart-32bbb360-9815-4099-800f-edcfb9aced1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672153203 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_lowpower_inval
id.1672153203
Directory /workspace/30.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/30.pwrmgr_reset.2182293251
Short name T580
Test name
Test status
Simulation time 95306506 ps
CPU time 0.68 seconds
Started Jul 24 05:08:27 PM PDT 24
Finished Jul 24 05:08:27 PM PDT 24
Peak memory 198820 kb
Host smart-e1009e65-c615-4f39-8e47-db8b68858154
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182293251 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset.2182293251
Directory /workspace/30.pwrmgr_reset/latest

Test location /workspace/coverage/default/30.pwrmgr_reset_invalid.3066155149
Short name T403
Test name
Test status
Simulation time 145324839 ps
CPU time 0.79 seconds
Started Jul 24 05:08:48 PM PDT 24
Finished Jul 24 05:08:49 PM PDT 24
Peak memory 209968 kb
Host smart-030e27d8-bbe8-4165-931d-f9e5b0e6e0f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066155149 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset_invalid.3066155149
Directory /workspace/30.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/30.pwrmgr_sec_cm_rstmgr_intersig_mubi.1344798884
Short name T477
Test name
Test status
Simulation time 70085608 ps
CPU time 0.68 seconds
Started Jul 24 05:08:37 PM PDT 24
Finished Jul 24 05:08:37 PM PDT 24
Peak memory 198552 kb
Host smart-ac865a15-86ca-4ff4-8bfc-93960deeda70
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344798884 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1344798884
Directory /workspace/30.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/30.pwrmgr_smoke.1391709353
Short name T406
Test name
Test status
Simulation time 57643357 ps
CPU time 0.68 seconds
Started Jul 24 05:08:31 PM PDT 24
Finished Jul 24 05:08:32 PM PDT 24
Peak memory 198960 kb
Host smart-44977bef-74c6-4164-bb16-5c906d334e5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391709353 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_smoke.1391709353
Directory /workspace/30.pwrmgr_smoke/latest

Test location /workspace/coverage/default/31.pwrmgr_aborted_low_power.2577803385
Short name T574
Test name
Test status
Simulation time 48001969 ps
CPU time 0.75 seconds
Started Jul 24 05:08:22 PM PDT 24
Finished Jul 24 05:08:23 PM PDT 24
Peak memory 199192 kb
Host smart-f174d571-816c-48fa-85a1-429217540675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577803385 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_aborted_low_power.2577803385
Directory /workspace/31.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/31.pwrmgr_disable_rom_integrity_check.895599041
Short name T138
Test name
Test status
Simulation time 76132819 ps
CPU time 0.64 seconds
Started Jul 24 05:08:50 PM PDT 24
Finished Jul 24 05:08:51 PM PDT 24
Peak memory 199676 kb
Host smart-78d42b4a-3a44-4ef8-8b57-5df41faa3a8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895599041 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_disa
ble_rom_integrity_check.895599041
Directory /workspace/31.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/31.pwrmgr_esc_clk_rst_malfunc.3925404513
Short name T515
Test name
Test status
Simulation time 37219842 ps
CPU time 0.57 seconds
Started Jul 24 05:08:46 PM PDT 24
Finished Jul 24 05:08:47 PM PDT 24
Peak memory 198452 kb
Host smart-92bc13ec-1d79-47bb-93d3-97e20a14feae
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925404513 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_esc_clk_rst
_malfunc.3925404513
Directory /workspace/31.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/31.pwrmgr_escalation_timeout.3425823818
Short name T621
Test name
Test status
Simulation time 634876248 ps
CPU time 0.98 seconds
Started Jul 24 05:08:40 PM PDT 24
Finished Jul 24 05:08:41 PM PDT 24
Peak memory 198528 kb
Host smart-0ca347b1-9821-4147-842f-9642324f3476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425823818 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_escalation_timeout.3425823818
Directory /workspace/31.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/31.pwrmgr_glitch.1670774223
Short name T353
Test name
Test status
Simulation time 55481731 ps
CPU time 0.62 seconds
Started Jul 24 05:08:47 PM PDT 24
Finished Jul 24 05:08:47 PM PDT 24
Peak memory 198680 kb
Host smart-eb2c20e0-a558-4aa1-b7a8-20d40d999930
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670774223 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_glitch.1670774223
Directory /workspace/31.pwrmgr_glitch/latest

Test location /workspace/coverage/default/31.pwrmgr_global_esc.2819501188
Short name T268
Test name
Test status
Simulation time 38189494 ps
CPU time 0.62 seconds
Started Jul 24 05:08:39 PM PDT 24
Finished Jul 24 05:08:39 PM PDT 24
Peak memory 198972 kb
Host smart-0eddc555-e3bf-4a4d-a9f3-7b4e10b4487f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819501188 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_global_esc.2819501188
Directory /workspace/31.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/31.pwrmgr_lowpower_invalid.3470317780
Short name T173
Test name
Test status
Simulation time 44343232 ps
CPU time 0.71 seconds
Started Jul 24 05:08:22 PM PDT 24
Finished Jul 24 05:08:22 PM PDT 24
Peak memory 201768 kb
Host smart-ae34a519-0c4f-4484-a856-edd98627ee3c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470317780 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_lowpower_inval
id.3470317780
Directory /workspace/31.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/31.pwrmgr_reset.1215256181
Short name T35
Test name
Test status
Simulation time 96822792 ps
CPU time 0.77 seconds
Started Jul 24 05:08:29 PM PDT 24
Finished Jul 24 05:08:30 PM PDT 24
Peak memory 198864 kb
Host smart-bdab8d76-942d-433f-818d-fbffdfe0079f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215256181 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset.1215256181
Directory /workspace/31.pwrmgr_reset/latest

Test location /workspace/coverage/default/31.pwrmgr_reset_invalid.570142514
Short name T463
Test name
Test status
Simulation time 149984941 ps
CPU time 0.8 seconds
Started Jul 24 05:08:37 PM PDT 24
Finished Jul 24 05:08:38 PM PDT 24
Peak memory 210028 kb
Host smart-b18eb724-b464-45a6-a847-98507bd8edc6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570142514 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset_invalid.570142514
Directory /workspace/31.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/31.pwrmgr_sec_cm_rstmgr_intersig_mubi.2426441212
Short name T481
Test name
Test status
Simulation time 151350937 ps
CPU time 0.86 seconds
Started Jul 24 05:08:40 PM PDT 24
Finished Jul 24 05:08:41 PM PDT 24
Peak memory 199620 kb
Host smart-0ae1cf30-4024-4cfa-82f6-1a1fabd38bf6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426441212 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2426441212
Directory /workspace/31.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/31.pwrmgr_smoke.4093971247
Short name T244
Test name
Test status
Simulation time 39059999 ps
CPU time 0.64 seconds
Started Jul 24 05:08:45 PM PDT 24
Finished Jul 24 05:08:46 PM PDT 24
Peak memory 199744 kb
Host smart-d0074fee-1f04-4ecb-8c93-8c444e60ec0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093971247 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_smoke.4093971247
Directory /workspace/31.pwrmgr_smoke/latest

Test location /workspace/coverage/default/32.pwrmgr_aborted_low_power.1320626900
Short name T100
Test name
Test status
Simulation time 70872856 ps
CPU time 0.62 seconds
Started Jul 24 05:08:44 PM PDT 24
Finished Jul 24 05:08:45 PM PDT 24
Peak memory 199136 kb
Host smart-a4bd738e-eeb4-4ed2-901d-dfe1f0ef2fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320626900 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_aborted_low_power.1320626900
Directory /workspace/32.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/32.pwrmgr_disable_rom_integrity_check.4106409589
Short name T200
Test name
Test status
Simulation time 52174777 ps
CPU time 0.77 seconds
Started Jul 24 05:08:26 PM PDT 24
Finished Jul 24 05:08:27 PM PDT 24
Peak memory 199716 kb
Host smart-9d9900db-7239-4d34-be4d-b75a832721b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106409589 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_dis
able_rom_integrity_check.4106409589
Directory /workspace/32.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/32.pwrmgr_esc_clk_rst_malfunc.2766387888
Short name T438
Test name
Test status
Simulation time 33566876 ps
CPU time 0.59 seconds
Started Jul 24 05:08:30 PM PDT 24
Finished Jul 24 05:08:31 PM PDT 24
Peak memory 197696 kb
Host smart-a28eb808-951d-4ea0-ba58-c6ec9409f837
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766387888 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_esc_clk_rst
_malfunc.2766387888
Directory /workspace/32.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/32.pwrmgr_escalation_timeout.3587522649
Short name T323
Test name
Test status
Simulation time 1255825598 ps
CPU time 0.95 seconds
Started Jul 24 05:08:33 PM PDT 24
Finished Jul 24 05:08:34 PM PDT 24
Peak memory 198504 kb
Host smart-4aa877ef-56b5-4672-8c3c-d97dbb454ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587522649 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_escalation_timeout.3587522649
Directory /workspace/32.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/32.pwrmgr_glitch.3567529274
Short name T526
Test name
Test status
Simulation time 57463707 ps
CPU time 0.63 seconds
Started Jul 24 05:08:34 PM PDT 24
Finished Jul 24 05:08:35 PM PDT 24
Peak memory 198628 kb
Host smart-1722d7d1-c948-4ebb-9508-d70106ed59d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567529274 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_glitch.3567529274
Directory /workspace/32.pwrmgr_glitch/latest

Test location /workspace/coverage/default/32.pwrmgr_global_esc.1367274695
Short name T511
Test name
Test status
Simulation time 36752430 ps
CPU time 0.62 seconds
Started Jul 24 05:08:35 PM PDT 24
Finished Jul 24 05:08:36 PM PDT 24
Peak memory 198512 kb
Host smart-dd642635-1536-4784-a2a1-b2050180eb1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367274695 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_global_esc.1367274695
Directory /workspace/32.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/32.pwrmgr_lowpower_invalid.3993987644
Short name T29
Test name
Test status
Simulation time 76316835 ps
CPU time 0.65 seconds
Started Jul 24 05:08:36 PM PDT 24
Finished Jul 24 05:08:37 PM PDT 24
Peak memory 201956 kb
Host smart-fd85ed7f-4f71-4d21-b8c7-8541fa0e6f5e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993987644 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_lowpower_inval
id.3993987644
Directory /workspace/32.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/32.pwrmgr_reset.2891757721
Short name T7
Test name
Test status
Simulation time 83992435 ps
CPU time 0.88 seconds
Started Jul 24 05:08:36 PM PDT 24
Finished Jul 24 05:08:37 PM PDT 24
Peak memory 199032 kb
Host smart-182a355c-491d-4654-8361-5e05e6ab4457
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891757721 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset.2891757721
Directory /workspace/32.pwrmgr_reset/latest

Test location /workspace/coverage/default/32.pwrmgr_reset_invalid.1857349793
Short name T599
Test name
Test status
Simulation time 111893354 ps
CPU time 1.08 seconds
Started Jul 24 05:08:35 PM PDT 24
Finished Jul 24 05:08:37 PM PDT 24
Peak memory 209932 kb
Host smart-bb89a5b7-0a63-4df3-8af3-48dd88093e4d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857349793 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset_invalid.1857349793
Directory /workspace/32.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/32.pwrmgr_sec_cm_rstmgr_intersig_mubi.2710137519
Short name T550
Test name
Test status
Simulation time 72758036 ps
CPU time 0.89 seconds
Started Jul 24 05:08:31 PM PDT 24
Finished Jul 24 05:08:32 PM PDT 24
Peak memory 199736 kb
Host smart-66d51d88-60eb-43ef-89c2-26367139363c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710137519 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2710137519
Directory /workspace/32.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/32.pwrmgr_smoke.1669725552
Short name T352
Test name
Test status
Simulation time 61739004 ps
CPU time 0.65 seconds
Started Jul 24 05:08:38 PM PDT 24
Finished Jul 24 05:08:39 PM PDT 24
Peak memory 199796 kb
Host smart-5350c7f3-31f1-4a0f-837b-425b778422dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669725552 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_smoke.1669725552
Directory /workspace/32.pwrmgr_smoke/latest

Test location /workspace/coverage/default/33.pwrmgr_aborted_low_power.3956923266
Short name T97
Test name
Test status
Simulation time 106525076 ps
CPU time 0.74 seconds
Started Jul 24 05:08:34 PM PDT 24
Finished Jul 24 05:08:35 PM PDT 24
Peak memory 199228 kb
Host smart-b4fd2021-dc95-4e12-a29d-a6c61df35839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956923266 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_aborted_low_power.3956923266
Directory /workspace/33.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/33.pwrmgr_disable_rom_integrity_check.3082764008
Short name T303
Test name
Test status
Simulation time 81377047 ps
CPU time 0.63 seconds
Started Jul 24 05:08:39 PM PDT 24
Finished Jul 24 05:08:39 PM PDT 24
Peak memory 198816 kb
Host smart-8c82c5fe-2aae-4c84-a40a-531538b544fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082764008 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_dis
able_rom_integrity_check.3082764008
Directory /workspace/33.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/33.pwrmgr_esc_clk_rst_malfunc.2684693030
Short name T456
Test name
Test status
Simulation time 32610309 ps
CPU time 0.59 seconds
Started Jul 24 05:08:52 PM PDT 24
Finished Jul 24 05:08:53 PM PDT 24
Peak memory 197852 kb
Host smart-efc6594e-153e-4320-95b5-a785f126435e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684693030 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_esc_clk_rst
_malfunc.2684693030
Directory /workspace/33.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/33.pwrmgr_escalation_timeout.130811964
Short name T390
Test name
Test status
Simulation time 316748833 ps
CPU time 1.01 seconds
Started Jul 24 05:08:33 PM PDT 24
Finished Jul 24 05:08:35 PM PDT 24
Peak memory 198524 kb
Host smart-40fc2fe7-6ac2-41dd-ba24-48eb993fdbb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130811964 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_escalation_timeout.130811964
Directory /workspace/33.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/33.pwrmgr_glitch.970637508
Short name T334
Test name
Test status
Simulation time 53018554 ps
CPU time 0.59 seconds
Started Jul 24 05:08:32 PM PDT 24
Finished Jul 24 05:08:33 PM PDT 24
Peak memory 198548 kb
Host smart-2fc557da-0b59-471f-b5fa-b37a26cdfc8e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970637508 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_glitch.970637508
Directory /workspace/33.pwrmgr_glitch/latest

Test location /workspace/coverage/default/33.pwrmgr_global_esc.1260062541
Short name T326
Test name
Test status
Simulation time 43208338 ps
CPU time 0.63 seconds
Started Jul 24 05:08:40 PM PDT 24
Finished Jul 24 05:08:40 PM PDT 24
Peak memory 198708 kb
Host smart-57c69705-f805-4f99-bba9-39cccde4dff8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260062541 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_global_esc.1260062541
Directory /workspace/33.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/33.pwrmgr_lowpower_invalid.1896049419
Short name T148
Test name
Test status
Simulation time 41986285 ps
CPU time 0.72 seconds
Started Jul 24 05:08:30 PM PDT 24
Finished Jul 24 05:08:31 PM PDT 24
Peak memory 201832 kb
Host smart-2755e8f6-75a2-4bbd-8505-36a6e9d09507
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896049419 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_lowpower_inval
id.1896049419
Directory /workspace/33.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/33.pwrmgr_reset.2860598382
Short name T467
Test name
Test status
Simulation time 56359017 ps
CPU time 0.62 seconds
Started Jul 24 05:08:23 PM PDT 24
Finished Jul 24 05:08:24 PM PDT 24
Peak memory 198712 kb
Host smart-3e0b467c-3967-47b8-b90c-aef109bf6e1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860598382 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset.2860598382
Directory /workspace/33.pwrmgr_reset/latest

Test location /workspace/coverage/default/33.pwrmgr_reset_invalid.1162823051
Short name T221
Test name
Test status
Simulation time 166333078 ps
CPU time 0.82 seconds
Started Jul 24 05:08:34 PM PDT 24
Finished Jul 24 05:08:36 PM PDT 24
Peak memory 210100 kb
Host smart-e7b6c5fd-faca-4c32-9a14-3f81c5823e11
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162823051 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset_invalid.1162823051
Directory /workspace/33.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/33.pwrmgr_sec_cm_rstmgr_intersig_mubi.3607380099
Short name T71
Test name
Test status
Simulation time 54768693 ps
CPU time 0.74 seconds
Started Jul 24 05:08:27 PM PDT 24
Finished Jul 24 05:08:28 PM PDT 24
Peak memory 198332 kb
Host smart-80d331e6-8020-4e4d-a352-df7e0429555c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607380099 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3607380099
Directory /workspace/33.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/33.pwrmgr_smoke.3317481581
Short name T55
Test name
Test status
Simulation time 61327329 ps
CPU time 0.64 seconds
Started Jul 24 05:08:34 PM PDT 24
Finished Jul 24 05:08:35 PM PDT 24
Peak memory 199864 kb
Host smart-b682cb28-60fc-4fe0-a570-ab319a2e7ea0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317481581 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_smoke.3317481581
Directory /workspace/33.pwrmgr_smoke/latest

Test location /workspace/coverage/default/34.pwrmgr_disable_rom_integrity_check.421860423
Short name T507
Test name
Test status
Simulation time 51408591 ps
CPU time 0.7 seconds
Started Jul 24 05:08:46 PM PDT 24
Finished Jul 24 05:08:46 PM PDT 24
Peak memory 199744 kb
Host smart-fd70961f-0eb7-4231-a239-bcc06e39e102
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421860423 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_disa
ble_rom_integrity_check.421860423
Directory /workspace/34.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/34.pwrmgr_esc_clk_rst_malfunc.3888869584
Short name T605
Test name
Test status
Simulation time 29400048 ps
CPU time 0.61 seconds
Started Jul 24 05:08:39 PM PDT 24
Finished Jul 24 05:08:39 PM PDT 24
Peak memory 197760 kb
Host smart-ac76f28a-b706-4bcd-b521-f16529cd0342
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888869584 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_esc_clk_rst
_malfunc.3888869584
Directory /workspace/34.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/34.pwrmgr_escalation_timeout.223403957
Short name T530
Test name
Test status
Simulation time 163891839 ps
CPU time 1 seconds
Started Jul 24 05:09:00 PM PDT 24
Finished Jul 24 05:09:02 PM PDT 24
Peak memory 198584 kb
Host smart-bba0e717-d4ee-4e30-bad8-e7e0d8620725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223403957 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_escalation_timeout.223403957
Directory /workspace/34.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/34.pwrmgr_glitch.4274555239
Short name T615
Test name
Test status
Simulation time 46092450 ps
CPU time 0.61 seconds
Started Jul 24 05:08:36 PM PDT 24
Finished Jul 24 05:08:37 PM PDT 24
Peak memory 197792 kb
Host smart-2ff94b71-d474-472c-869e-8bb75b88edce
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274555239 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_glitch.4274555239
Directory /workspace/34.pwrmgr_glitch/latest

Test location /workspace/coverage/default/34.pwrmgr_global_esc.2088233348
Short name T465
Test name
Test status
Simulation time 24471485 ps
CPU time 0.59 seconds
Started Jul 24 05:08:31 PM PDT 24
Finished Jul 24 05:08:32 PM PDT 24
Peak memory 198936 kb
Host smart-9bacc2c6-c710-43f5-8eaf-1ef4d5f137aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088233348 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_global_esc.2088233348
Directory /workspace/34.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/34.pwrmgr_lowpower_invalid.1879140759
Short name T98
Test name
Test status
Simulation time 46626888 ps
CPU time 0.72 seconds
Started Jul 24 05:08:48 PM PDT 24
Finished Jul 24 05:08:49 PM PDT 24
Peak memory 201940 kb
Host smart-85c77201-19c2-4db0-9d59-abab73ad1099
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879140759 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_lowpower_inval
id.1879140759
Directory /workspace/34.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/34.pwrmgr_reset.1193378804
Short name T224
Test name
Test status
Simulation time 44208217 ps
CPU time 0.58 seconds
Started Jul 24 05:08:38 PM PDT 24
Finished Jul 24 05:08:39 PM PDT 24
Peak memory 198596 kb
Host smart-fd38e262-0122-4570-b14c-6aa45458613e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193378804 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset.1193378804
Directory /workspace/34.pwrmgr_reset/latest

Test location /workspace/coverage/default/34.pwrmgr_reset_invalid.1989564798
Short name T347
Test name
Test status
Simulation time 162442165 ps
CPU time 0.78 seconds
Started Jul 24 05:08:55 PM PDT 24
Finished Jul 24 05:08:56 PM PDT 24
Peak memory 210008 kb
Host smart-95bb85fc-250e-4ca8-b799-f49766985d57
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989564798 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset_invalid.1989564798
Directory /workspace/34.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/34.pwrmgr_sec_cm_rstmgr_intersig_mubi.2713086766
Short name T392
Test name
Test status
Simulation time 140943763 ps
CPU time 0.78 seconds
Started Jul 24 05:08:25 PM PDT 24
Finished Jul 24 05:08:27 PM PDT 24
Peak memory 199808 kb
Host smart-bb877dbb-d9f2-460f-809c-af5fcfc53534
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713086766 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2713086766
Directory /workspace/34.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/34.pwrmgr_smoke.4128405005
Short name T242
Test name
Test status
Simulation time 31437977 ps
CPU time 0.68 seconds
Started Jul 24 05:08:29 PM PDT 24
Finished Jul 24 05:08:30 PM PDT 24
Peak memory 199788 kb
Host smart-7b2e29ea-32ff-4e01-95f0-b91943c6db8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128405005 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_smoke.4128405005
Directory /workspace/34.pwrmgr_smoke/latest

Test location /workspace/coverage/default/35.pwrmgr_aborted_low_power.595381082
Short name T298
Test name
Test status
Simulation time 32552609 ps
CPU time 0.8 seconds
Started Jul 24 05:08:34 PM PDT 24
Finished Jul 24 05:08:35 PM PDT 24
Peak memory 200624 kb
Host smart-e8fd0feb-90da-4bf9-a424-92a8a2793c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595381082 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_aborted_low_power.595381082
Directory /workspace/35.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/35.pwrmgr_disable_rom_integrity_check.3997184185
Short name T27
Test name
Test status
Simulation time 48388084 ps
CPU time 0.76 seconds
Started Jul 24 05:08:47 PM PDT 24
Finished Jul 24 05:08:47 PM PDT 24
Peak memory 199712 kb
Host smart-d82a803f-bfd6-46e8-9b4e-32c47e329833
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997184185 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_dis
able_rom_integrity_check.3997184185
Directory /workspace/35.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/35.pwrmgr_esc_clk_rst_malfunc.1243177763
Short name T329
Test name
Test status
Simulation time 30717687 ps
CPU time 0.62 seconds
Started Jul 24 05:08:47 PM PDT 24
Finished Jul 24 05:08:48 PM PDT 24
Peak memory 198584 kb
Host smart-4f33cca1-27af-4014-a8d9-5191c0c822fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243177763 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_esc_clk_rst
_malfunc.1243177763
Directory /workspace/35.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/35.pwrmgr_escalation_timeout.2184701960
Short name T604
Test name
Test status
Simulation time 164936400 ps
CPU time 0.93 seconds
Started Jul 24 05:08:33 PM PDT 24
Finished Jul 24 05:08:35 PM PDT 24
Peak memory 198956 kb
Host smart-f8372ab9-2a8b-4d36-ab00-da40d37144b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184701960 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_escalation_timeout.2184701960
Directory /workspace/35.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/35.pwrmgr_glitch.2477699897
Short name T469
Test name
Test status
Simulation time 75550732 ps
CPU time 0.6 seconds
Started Jul 24 05:08:43 PM PDT 24
Finished Jul 24 05:08:44 PM PDT 24
Peak memory 198548 kb
Host smart-4fbda43f-0f4d-4157-ae26-77b994504607
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477699897 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_glitch.2477699897
Directory /workspace/35.pwrmgr_glitch/latest

Test location /workspace/coverage/default/35.pwrmgr_global_esc.1820631800
Short name T553
Test name
Test status
Simulation time 20898729 ps
CPU time 0.61 seconds
Started Jul 24 05:08:40 PM PDT 24
Finished Jul 24 05:08:40 PM PDT 24
Peak memory 198588 kb
Host smart-9e8e2586-52fa-4e8b-9738-6a647cc0ce8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820631800 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_global_esc.1820631800
Directory /workspace/35.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/35.pwrmgr_lowpower_invalid.189968337
Short name T549
Test name
Test status
Simulation time 79084408 ps
CPU time 0.67 seconds
Started Jul 24 05:09:06 PM PDT 24
Finished Jul 24 05:09:07 PM PDT 24
Peak memory 201980 kb
Host smart-f0bb6d38-afe9-4e16-beb5-1239e42d1acd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189968337 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_lowpower_invali
d.189968337
Directory /workspace/35.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/35.pwrmgr_lowpower_wakeup_race.2660755860
Short name T12
Test name
Test status
Simulation time 89346409 ps
CPU time 0.6 seconds
Started Jul 24 05:08:33 PM PDT 24
Finished Jul 24 05:08:34 PM PDT 24
Peak memory 198836 kb
Host smart-183f9134-6b3a-4358-a8c6-02e1f96ba7c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660755860 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_lowpower_w
akeup_race.2660755860
Directory /workspace/35.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/35.pwrmgr_reset.27757241
Short name T333
Test name
Test status
Simulation time 167559946 ps
CPU time 0.63 seconds
Started Jul 24 05:08:32 PM PDT 24
Finished Jul 24 05:08:32 PM PDT 24
Peak memory 198936 kb
Host smart-ed044725-7b17-4b24-a1a9-6e203b9f5fe0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27757241 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset.27757241
Directory /workspace/35.pwrmgr_reset/latest

Test location /workspace/coverage/default/35.pwrmgr_reset_invalid.419710486
Short name T34
Test name
Test status
Simulation time 108831901 ps
CPU time 0.92 seconds
Started Jul 24 05:08:53 PM PDT 24
Finished Jul 24 05:08:54 PM PDT 24
Peak memory 209964 kb
Host smart-e186fa3d-5514-4a9d-b5ee-0a37cb18a22a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419710486 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset_invalid.419710486
Directory /workspace/35.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/35.pwrmgr_sec_cm_rstmgr_intersig_mubi.905879771
Short name T543
Test name
Test status
Simulation time 108643662 ps
CPU time 0.72 seconds
Started Jul 24 05:08:43 PM PDT 24
Finished Jul 24 05:08:44 PM PDT 24
Peak memory 198740 kb
Host smart-42997605-2179-40c7-b7f7-bff57c3a38b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905879771 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_rstmgr_intersig_
mubi.905879771
Directory /workspace/35.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/35.pwrmgr_smoke.1992547078
Short name T357
Test name
Test status
Simulation time 35629948 ps
CPU time 0.63 seconds
Started Jul 24 05:08:44 PM PDT 24
Finished Jul 24 05:08:45 PM PDT 24
Peak memory 199932 kb
Host smart-55612082-395d-49fe-9c48-ba32a840866d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992547078 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_smoke.1992547078
Directory /workspace/35.pwrmgr_smoke/latest

Test location /workspace/coverage/default/36.pwrmgr_aborted_low_power.811572035
Short name T238
Test name
Test status
Simulation time 32969218 ps
CPU time 1.06 seconds
Started Jul 24 05:08:40 PM PDT 24
Finished Jul 24 05:08:41 PM PDT 24
Peak memory 201564 kb
Host smart-0d7fb778-6159-4087-ae66-78b14acb3c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811572035 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_aborted_low_power.811572035
Directory /workspace/36.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/36.pwrmgr_disable_rom_integrity_check.548356493
Short name T420
Test name
Test status
Simulation time 108479350 ps
CPU time 0.67 seconds
Started Jul 24 05:08:43 PM PDT 24
Finished Jul 24 05:08:44 PM PDT 24
Peak memory 198884 kb
Host smart-7ba1314d-bb42-436f-b8e2-6c8021966155
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548356493 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_disa
ble_rom_integrity_check.548356493
Directory /workspace/36.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/36.pwrmgr_esc_clk_rst_malfunc.2631319475
Short name T587
Test name
Test status
Simulation time 64758608 ps
CPU time 0.59 seconds
Started Jul 24 05:08:47 PM PDT 24
Finished Jul 24 05:08:48 PM PDT 24
Peak memory 197768 kb
Host smart-604b8c53-e0ee-43d3-9678-8e1d4d383328
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631319475 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_esc_clk_rst
_malfunc.2631319475
Directory /workspace/36.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/36.pwrmgr_escalation_timeout.107937371
Short name T558
Test name
Test status
Simulation time 564171909 ps
CPU time 0.97 seconds
Started Jul 24 05:09:10 PM PDT 24
Finished Jul 24 05:09:11 PM PDT 24
Peak memory 198672 kb
Host smart-af6a7165-fd7a-410b-aebd-7659f1f46ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107937371 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_escalation_timeout.107937371
Directory /workspace/36.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/36.pwrmgr_glitch.3126223823
Short name T389
Test name
Test status
Simulation time 34963281 ps
CPU time 0.62 seconds
Started Jul 24 05:08:52 PM PDT 24
Finished Jul 24 05:08:53 PM PDT 24
Peak memory 198668 kb
Host smart-84ed777a-0399-4b51-a9ec-a4f3ea8e5d30
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126223823 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_glitch.3126223823
Directory /workspace/36.pwrmgr_glitch/latest

Test location /workspace/coverage/default/36.pwrmgr_global_esc.2929124371
Short name T551
Test name
Test status
Simulation time 41945685 ps
CPU time 0.58 seconds
Started Jul 24 05:08:32 PM PDT 24
Finished Jul 24 05:08:42 PM PDT 24
Peak memory 198472 kb
Host smart-ff8a3907-bf19-44f4-8b90-7e9688879725
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929124371 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_global_esc.2929124371
Directory /workspace/36.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/36.pwrmgr_lowpower_invalid.305491255
Short name T50
Test name
Test status
Simulation time 40199020 ps
CPU time 0.7 seconds
Started Jul 24 05:08:38 PM PDT 24
Finished Jul 24 05:08:39 PM PDT 24
Peak memory 201868 kb
Host smart-8b8e7eb6-6a07-4024-824c-46dfdc557b05
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305491255 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_lowpower_invali
d.305491255
Directory /workspace/36.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/36.pwrmgr_reset.2031177079
Short name T299
Test name
Test status
Simulation time 65511119 ps
CPU time 0.76 seconds
Started Jul 24 05:08:48 PM PDT 24
Finished Jul 24 05:08:49 PM PDT 24
Peak memory 198868 kb
Host smart-4b51de3f-3ba4-4fcb-ad48-f441a0f603a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031177079 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset.2031177079
Directory /workspace/36.pwrmgr_reset/latest

Test location /workspace/coverage/default/36.pwrmgr_reset_invalid.3881283150
Short name T418
Test name
Test status
Simulation time 151344308 ps
CPU time 0.75 seconds
Started Jul 24 05:08:42 PM PDT 24
Finished Jul 24 05:08:43 PM PDT 24
Peak memory 209956 kb
Host smart-ea20fd39-d904-4410-822e-a3d2e989e8b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881283150 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset_invalid.3881283150
Directory /workspace/36.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/36.pwrmgr_smoke.858003465
Short name T519
Test name
Test status
Simulation time 56464625 ps
CPU time 0.63 seconds
Started Jul 24 05:08:42 PM PDT 24
Finished Jul 24 05:08:43 PM PDT 24
Peak memory 198972 kb
Host smart-6bc52b48-d3ff-4899-bcf8-20ac9ad6cd86
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858003465 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_smoke.858003465
Directory /workspace/36.pwrmgr_smoke/latest

Test location /workspace/coverage/default/37.pwrmgr_aborted_low_power.582626101
Short name T122
Test name
Test status
Simulation time 133365589 ps
CPU time 0.74 seconds
Started Jul 24 05:08:33 PM PDT 24
Finished Jul 24 05:08:34 PM PDT 24
Peak memory 199332 kb
Host smart-18f2c640-7633-44b0-8471-40f86b3800d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582626101 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_aborted_low_power.582626101
Directory /workspace/37.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/37.pwrmgr_disable_rom_integrity_check.2351618219
Short name T393
Test name
Test status
Simulation time 59260544 ps
CPU time 0.7 seconds
Started Jul 24 05:08:39 PM PDT 24
Finished Jul 24 05:08:40 PM PDT 24
Peak memory 198964 kb
Host smart-9dea1ace-0a16-4d89-9345-92ea59a99cc9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351618219 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_dis
able_rom_integrity_check.2351618219
Directory /workspace/37.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/37.pwrmgr_esc_clk_rst_malfunc.2977466161
Short name T254
Test name
Test status
Simulation time 30631985 ps
CPU time 0.64 seconds
Started Jul 24 05:08:44 PM PDT 24
Finished Jul 24 05:08:45 PM PDT 24
Peak memory 198552 kb
Host smart-abc8408c-4b21-48fe-a6e2-ad341c8b30ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977466161 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_esc_clk_rst
_malfunc.2977466161
Directory /workspace/37.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/37.pwrmgr_escalation_timeout.4196301225
Short name T492
Test name
Test status
Simulation time 687007260 ps
CPU time 0.98 seconds
Started Jul 24 05:08:47 PM PDT 24
Finished Jul 24 05:08:48 PM PDT 24
Peak memory 198624 kb
Host smart-09cd9ef3-659d-4bd2-ad3c-4e6d9207ac6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196301225 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_escalation_timeout.4196301225
Directory /workspace/37.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/37.pwrmgr_glitch.4092079170
Short name T524
Test name
Test status
Simulation time 22304322 ps
CPU time 0.59 seconds
Started Jul 24 05:08:30 PM PDT 24
Finished Jul 24 05:08:31 PM PDT 24
Peak memory 197956 kb
Host smart-699c516c-5d8a-4673-bac9-ed96bd583b23
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092079170 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_glitch.4092079170
Directory /workspace/37.pwrmgr_glitch/latest

Test location /workspace/coverage/default/37.pwrmgr_global_esc.1933264619
Short name T339
Test name
Test status
Simulation time 120814473 ps
CPU time 0.63 seconds
Started Jul 24 05:08:32 PM PDT 24
Finished Jul 24 05:08:33 PM PDT 24
Peak memory 198652 kb
Host smart-fc9542ec-f78a-476f-b752-05f6cd44aeb0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933264619 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_global_esc.1933264619
Directory /workspace/37.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/37.pwrmgr_lowpower_invalid.152713660
Short name T498
Test name
Test status
Simulation time 41139284 ps
CPU time 0.72 seconds
Started Jul 24 05:08:38 PM PDT 24
Finished Jul 24 05:08:39 PM PDT 24
Peak memory 201988 kb
Host smart-d13d3ad8-477a-409c-84c3-a91c402d7cae
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152713660 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_lowpower_invali
d.152713660
Directory /workspace/37.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/37.pwrmgr_reset.834153922
Short name T470
Test name
Test status
Simulation time 70821760 ps
CPU time 0.84 seconds
Started Jul 24 05:08:34 PM PDT 24
Finished Jul 24 05:08:35 PM PDT 24
Peak memory 199664 kb
Host smart-d85d1db4-1802-487e-be41-071421e4b4b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834153922 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset.834153922
Directory /workspace/37.pwrmgr_reset/latest

Test location /workspace/coverage/default/37.pwrmgr_reset_invalid.2354305203
Short name T376
Test name
Test status
Simulation time 109860038 ps
CPU time 1.1 seconds
Started Jul 24 05:09:04 PM PDT 24
Finished Jul 24 05:09:06 PM PDT 24
Peak memory 210016 kb
Host smart-7c08f599-9029-4358-9539-6a7b247ec18b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354305203 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset_invalid.2354305203
Directory /workspace/37.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/37.pwrmgr_sec_cm_rstmgr_intersig_mubi.2072923230
Short name T622
Test name
Test status
Simulation time 95887066 ps
CPU time 0.79 seconds
Started Jul 24 05:08:48 PM PDT 24
Finished Jul 24 05:08:49 PM PDT 24
Peak memory 199848 kb
Host smart-7bd62619-7507-42ba-b548-ad9253b12fdc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072923230 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2072923230
Directory /workspace/37.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/37.pwrmgr_smoke.353689221
Short name T59
Test name
Test status
Simulation time 28309731 ps
CPU time 0.64 seconds
Started Jul 24 05:08:49 PM PDT 24
Finished Jul 24 05:08:50 PM PDT 24
Peak memory 199940 kb
Host smart-496a19f2-3a3e-4ff5-a5d8-de860be25a90
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353689221 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_smoke.353689221
Directory /workspace/37.pwrmgr_smoke/latest

Test location /workspace/coverage/default/38.pwrmgr_aborted_low_power.249816653
Short name T600
Test name
Test status
Simulation time 53346521 ps
CPU time 0.6 seconds
Started Jul 24 05:08:52 PM PDT 24
Finished Jul 24 05:08:53 PM PDT 24
Peak memory 199044 kb
Host smart-8ef2dca5-f832-46b2-91e6-cd52499aaad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249816653 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_aborted_low_power.249816653
Directory /workspace/38.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/38.pwrmgr_disable_rom_integrity_check.2963180299
Short name T573
Test name
Test status
Simulation time 89276916 ps
CPU time 0.66 seconds
Started Jul 24 05:08:33 PM PDT 24
Finished Jul 24 05:08:34 PM PDT 24
Peak memory 199100 kb
Host smart-c58d9c37-9a98-4ee9-a116-65172bea3267
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963180299 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_dis
able_rom_integrity_check.2963180299
Directory /workspace/38.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/38.pwrmgr_esc_clk_rst_malfunc.3048352710
Short name T248
Test name
Test status
Simulation time 35379446 ps
CPU time 0.61 seconds
Started Jul 24 05:09:05 PM PDT 24
Finished Jul 24 05:09:05 PM PDT 24
Peak memory 198596 kb
Host smart-b1a79001-7af7-416e-a04a-5214e5add6c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048352710 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_esc_clk_rst
_malfunc.3048352710
Directory /workspace/38.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/38.pwrmgr_escalation_timeout.880022420
Short name T129
Test name
Test status
Simulation time 169459226 ps
CPU time 0.91 seconds
Started Jul 24 05:08:44 PM PDT 24
Finished Jul 24 05:08:45 PM PDT 24
Peak memory 198624 kb
Host smart-fb4339c0-3b2f-48af-8b85-cf03c6247f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880022420 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_escalation_timeout.880022420
Directory /workspace/38.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/38.pwrmgr_glitch.2846199695
Short name T381
Test name
Test status
Simulation time 58168573 ps
CPU time 0.61 seconds
Started Jul 24 05:08:52 PM PDT 24
Finished Jul 24 05:08:53 PM PDT 24
Peak memory 198620 kb
Host smart-a11c3c29-d794-4674-b112-1a4cfdc5b84a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846199695 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_glitch.2846199695
Directory /workspace/38.pwrmgr_glitch/latest

Test location /workspace/coverage/default/38.pwrmgr_global_esc.2301937102
Short name T311
Test name
Test status
Simulation time 48216142 ps
CPU time 0.66 seconds
Started Jul 24 05:08:44 PM PDT 24
Finished Jul 24 05:08:45 PM PDT 24
Peak memory 198508 kb
Host smart-55eb1bad-cf9c-4adf-a5b0-9e5b0586b0f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301937102 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_global_esc.2301937102
Directory /workspace/38.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/38.pwrmgr_lowpower_invalid.2139331473
Short name T149
Test name
Test status
Simulation time 63902745 ps
CPU time 0.68 seconds
Started Jul 24 05:08:57 PM PDT 24
Finished Jul 24 05:08:57 PM PDT 24
Peak memory 201968 kb
Host smart-adc5944b-e65b-4c54-9a91-06944b4dd52c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139331473 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_lowpower_inval
id.2139331473
Directory /workspace/38.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/38.pwrmgr_reset.580388759
Short name T229
Test name
Test status
Simulation time 73166906 ps
CPU time 0.77 seconds
Started Jul 24 05:08:38 PM PDT 24
Finished Jul 24 05:08:39 PM PDT 24
Peak memory 199556 kb
Host smart-5feee313-18b9-465d-bfff-172550adfc25
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580388759 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset.580388759
Directory /workspace/38.pwrmgr_reset/latest

Test location /workspace/coverage/default/38.pwrmgr_sec_cm_rstmgr_intersig_mubi.3174153563
Short name T409
Test name
Test status
Simulation time 84332816 ps
CPU time 0.74 seconds
Started Jul 24 05:08:59 PM PDT 24
Finished Jul 24 05:09:00 PM PDT 24
Peak memory 198652 kb
Host smart-27043a7f-dd20-45ec-8958-df605db4cb2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174153563 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3174153563
Directory /workspace/38.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/38.pwrmgr_smoke.1352048909
Short name T396
Test name
Test status
Simulation time 208587332 ps
CPU time 0.63 seconds
Started Jul 24 05:08:58 PM PDT 24
Finished Jul 24 05:08:59 PM PDT 24
Peak memory 199036 kb
Host smart-079e24fe-34f2-4d6b-a2f3-0e8d7fa46534
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352048909 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_smoke.1352048909
Directory /workspace/38.pwrmgr_smoke/latest

Test location /workspace/coverage/default/39.pwrmgr_aborted_low_power.1788304693
Short name T617
Test name
Test status
Simulation time 44673913 ps
CPU time 0.72 seconds
Started Jul 24 05:08:56 PM PDT 24
Finished Jul 24 05:08:57 PM PDT 24
Peak memory 199452 kb
Host smart-a3e46a3c-9ef3-40f4-9098-c9281e57087c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788304693 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_aborted_low_power.1788304693
Directory /workspace/39.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/39.pwrmgr_disable_rom_integrity_check.4096168011
Short name T294
Test name
Test status
Simulation time 67956731 ps
CPU time 0.65 seconds
Started Jul 24 05:09:03 PM PDT 24
Finished Jul 24 05:09:03 PM PDT 24
Peak memory 199640 kb
Host smart-00960f66-59bd-4e76-88d5-e2147be30258
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096168011 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_dis
able_rom_integrity_check.4096168011
Directory /workspace/39.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/39.pwrmgr_esc_clk_rst_malfunc.928943094
Short name T532
Test name
Test status
Simulation time 40689560 ps
CPU time 0.61 seconds
Started Jul 24 05:08:45 PM PDT 24
Finished Jul 24 05:08:46 PM PDT 24
Peak memory 198576 kb
Host smart-a9be58dd-cb46-416a-97ce-dae9565c15af
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928943094 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_esc_clk_rst_
malfunc.928943094
Directory /workspace/39.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/39.pwrmgr_escalation_timeout.3651243815
Short name T318
Test name
Test status
Simulation time 602926455 ps
CPU time 0.92 seconds
Started Jul 24 05:08:38 PM PDT 24
Finished Jul 24 05:08:40 PM PDT 24
Peak memory 198512 kb
Host smart-bc936b82-0d56-4d84-bc49-ce67f1b0c9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651243815 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_escalation_timeout.3651243815
Directory /workspace/39.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/39.pwrmgr_glitch.2313119139
Short name T212
Test name
Test status
Simulation time 67007670 ps
CPU time 0.61 seconds
Started Jul 24 05:08:50 PM PDT 24
Finished Jul 24 05:08:50 PM PDT 24
Peak memory 198616 kb
Host smart-f56f506f-a033-4aa9-9d90-c6c3bcf4bc81
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313119139 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_glitch.2313119139
Directory /workspace/39.pwrmgr_glitch/latest

Test location /workspace/coverage/default/39.pwrmgr_global_esc.2487778388
Short name T5
Test name
Test status
Simulation time 74153145 ps
CPU time 0.58 seconds
Started Jul 24 05:08:50 PM PDT 24
Finished Jul 24 05:08:51 PM PDT 24
Peak memory 198620 kb
Host smart-87927a69-aded-4f9a-bfc8-370a91d49a9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487778388 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_global_esc.2487778388
Directory /workspace/39.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/39.pwrmgr_lowpower_invalid.1110057369
Short name T168
Test name
Test status
Simulation time 50762153 ps
CPU time 0.67 seconds
Started Jul 24 05:08:47 PM PDT 24
Finished Jul 24 05:08:48 PM PDT 24
Peak memory 202024 kb
Host smart-fb017ded-491a-4afa-93ea-a4382d1be5ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110057369 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_lowpower_inval
id.1110057369
Directory /workspace/39.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/39.pwrmgr_reset.2747393122
Short name T552
Test name
Test status
Simulation time 55301848 ps
CPU time 0.82 seconds
Started Jul 24 05:08:37 PM PDT 24
Finished Jul 24 05:08:38 PM PDT 24
Peak memory 199584 kb
Host smart-d37a83bf-684e-4ff9-a5e8-8b7a721cf12c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747393122 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset.2747393122
Directory /workspace/39.pwrmgr_reset/latest

Test location /workspace/coverage/default/39.pwrmgr_reset_invalid.2238781668
Short name T491
Test name
Test status
Simulation time 119318369 ps
CPU time 0.81 seconds
Started Jul 24 05:08:42 PM PDT 24
Finished Jul 24 05:08:43 PM PDT 24
Peak memory 210020 kb
Host smart-c3a719b4-37a9-4dc9-b7fc-917e8e94ae77
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238781668 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset_invalid.2238781668
Directory /workspace/39.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/39.pwrmgr_sec_cm_rstmgr_intersig_mubi.3773242464
Short name T512
Test name
Test status
Simulation time 54634062 ps
CPU time 0.73 seconds
Started Jul 24 05:08:53 PM PDT 24
Finished Jul 24 05:08:54 PM PDT 24
Peak memory 198604 kb
Host smart-e4dc6f3a-4a08-41f7-82b3-3b801e983409
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773242464 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3773242464
Directory /workspace/39.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/39.pwrmgr_smoke.88538159
Short name T505
Test name
Test status
Simulation time 36639601 ps
CPU time 0.64 seconds
Started Jul 24 05:09:02 PM PDT 24
Finished Jul 24 05:09:03 PM PDT 24
Peak memory 199044 kb
Host smart-923bb135-ed04-4462-9ada-6e622ce4db91
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88538159 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_smoke.88538159
Directory /workspace/39.pwrmgr_smoke/latest

Test location /workspace/coverage/default/4.pwrmgr_aborted_low_power.603837079
Short name T120
Test name
Test status
Simulation time 192191288 ps
CPU time 0.75 seconds
Started Jul 24 05:07:29 PM PDT 24
Finished Jul 24 05:07:30 PM PDT 24
Peak memory 199352 kb
Host smart-2c73a1a2-8d38-493b-b9e0-9c3492c267d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603837079 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_aborted_low_power.603837079
Directory /workspace/4.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/4.pwrmgr_disable_rom_integrity_check.3559224020
Short name T188
Test name
Test status
Simulation time 88915007 ps
CPU time 0.68 seconds
Started Jul 24 05:07:24 PM PDT 24
Finished Jul 24 05:07:25 PM PDT 24
Peak memory 199060 kb
Host smart-db5701a7-160d-4889-8176-ea31f810f47d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559224020 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_disa
ble_rom_integrity_check.3559224020
Directory /workspace/4.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/4.pwrmgr_esc_clk_rst_malfunc.1108523283
Short name T253
Test name
Test status
Simulation time 54279708 ps
CPU time 0.58 seconds
Started Jul 24 05:07:10 PM PDT 24
Finished Jul 24 05:07:11 PM PDT 24
Peak memory 197880 kb
Host smart-55462b45-d297-4384-b5c2-84793672362a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108523283 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_esc_clk_rst_
malfunc.1108523283
Directory /workspace/4.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/4.pwrmgr_escalation_timeout.2829632787
Short name T47
Test name
Test status
Simulation time 691964864 ps
CPU time 0.96 seconds
Started Jul 24 05:07:06 PM PDT 24
Finished Jul 24 05:07:08 PM PDT 24
Peak memory 198624 kb
Host smart-876d856f-a4f7-41f9-a263-8999667c2d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829632787 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_escalation_timeout.2829632787
Directory /workspace/4.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/4.pwrmgr_glitch.2321819530
Short name T513
Test name
Test status
Simulation time 51175639 ps
CPU time 0.71 seconds
Started Jul 24 05:07:27 PM PDT 24
Finished Jul 24 05:07:28 PM PDT 24
Peak memory 197940 kb
Host smart-451b51ce-c926-4e71-9825-085df9d32201
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321819530 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_glitch.2321819530
Directory /workspace/4.pwrmgr_glitch/latest

Test location /workspace/coverage/default/4.pwrmgr_global_esc.2769590344
Short name T540
Test name
Test status
Simulation time 28611917 ps
CPU time 0.62 seconds
Started Jul 24 05:07:19 PM PDT 24
Finished Jul 24 05:07:20 PM PDT 24
Peak memory 198644 kb
Host smart-da4862a8-eebc-417f-aa5d-d8c2879fdccd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769590344 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_global_esc.2769590344
Directory /workspace/4.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/4.pwrmgr_reset.1598138993
Short name T49
Test name
Test status
Simulation time 130659032 ps
CPU time 0.79 seconds
Started Jul 24 05:07:29 PM PDT 24
Finished Jul 24 05:07:30 PM PDT 24
Peak memory 198648 kb
Host smart-847a229d-e17c-4b76-a865-6e933b7cd320
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598138993 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset.1598138993
Directory /workspace/4.pwrmgr_reset/latest

Test location /workspace/coverage/default/4.pwrmgr_reset_invalid.2900952198
Short name T319
Test name
Test status
Simulation time 102302869 ps
CPU time 0.96 seconds
Started Jul 24 05:07:28 PM PDT 24
Finished Jul 24 05:07:30 PM PDT 24
Peak memory 210108 kb
Host smart-10c05bb3-f8a5-40b5-8e09-670e568abff3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900952198 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset_invalid.2900952198
Directory /workspace/4.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm.2355470605
Short name T31
Test name
Test status
Simulation time 627437654 ps
CPU time 1.97 seconds
Started Jul 24 05:07:31 PM PDT 24
Finished Jul 24 05:07:33 PM PDT 24
Peak memory 218364 kb
Host smart-0327d893-c016-4a33-8437-159893729b8c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355470605 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm.2355470605
Directory /workspace/4.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm_rstmgr_intersig_mubi.3820884413
Short name T608
Test name
Test status
Simulation time 186907710 ps
CPU time 0.73 seconds
Started Jul 24 05:07:20 PM PDT 24
Finished Jul 24 05:07:21 PM PDT 24
Peak memory 198644 kb
Host smart-c1655dcb-646a-4db1-95f0-d46ae2c1ae9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820884413 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_rstmgr_intersig_
mubi.3820884413
Directory /workspace/4.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/4.pwrmgr_smoke.2947620240
Short name T485
Test name
Test status
Simulation time 46585499 ps
CPU time 0.69 seconds
Started Jul 24 05:07:15 PM PDT 24
Finished Jul 24 05:07:16 PM PDT 24
Peak memory 199740 kb
Host smart-cd62ba25-a84f-4665-ae7d-b9cccafa9d9e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947620240 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_smoke.2947620240
Directory /workspace/4.pwrmgr_smoke/latest

Test location /workspace/coverage/default/40.pwrmgr_aborted_low_power.2102803785
Short name T102
Test name
Test status
Simulation time 46796973 ps
CPU time 0.76 seconds
Started Jul 24 05:08:47 PM PDT 24
Finished Jul 24 05:08:53 PM PDT 24
Peak memory 200572 kb
Host smart-79aa423d-0da6-4217-9f19-476157f5197b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102803785 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_aborted_low_power.2102803785
Directory /workspace/40.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/40.pwrmgr_disable_rom_integrity_check.400151877
Short name T398
Test name
Test status
Simulation time 49089273 ps
CPU time 0.68 seconds
Started Jul 24 05:08:51 PM PDT 24
Finished Jul 24 05:08:51 PM PDT 24
Peak memory 199720 kb
Host smart-fcccae13-0657-4e18-878f-1fdf8bfce92c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400151877 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_disa
ble_rom_integrity_check.400151877
Directory /workspace/40.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/40.pwrmgr_esc_clk_rst_malfunc.770688988
Short name T402
Test name
Test status
Simulation time 37519635 ps
CPU time 0.58 seconds
Started Jul 24 05:08:49 PM PDT 24
Finished Jul 24 05:08:50 PM PDT 24
Peak memory 197872 kb
Host smart-3df81d09-3330-41b7-b8ac-5827a1a3320e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770688988 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_esc_clk_rst_
malfunc.770688988
Directory /workspace/40.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/40.pwrmgr_escalation_timeout.1172743198
Short name T425
Test name
Test status
Simulation time 835959646 ps
CPU time 1 seconds
Started Jul 24 05:08:45 PM PDT 24
Finished Jul 24 05:08:46 PM PDT 24
Peak memory 198936 kb
Host smart-890792f1-fbb9-4fb4-a84c-45bdda9f5550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172743198 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_escalation_timeout.1172743198
Directory /workspace/40.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/40.pwrmgr_glitch.784468868
Short name T273
Test name
Test status
Simulation time 42513120 ps
CPU time 0.61 seconds
Started Jul 24 05:08:54 PM PDT 24
Finished Jul 24 05:08:55 PM PDT 24
Peak memory 198516 kb
Host smart-edd02250-9114-4e7f-8914-327e61f848f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784468868 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_glitch.784468868
Directory /workspace/40.pwrmgr_glitch/latest

Test location /workspace/coverage/default/40.pwrmgr_global_esc.2704477605
Short name T560
Test name
Test status
Simulation time 70384354 ps
CPU time 0.61 seconds
Started Jul 24 05:09:10 PM PDT 24
Finished Jul 24 05:09:11 PM PDT 24
Peak memory 198668 kb
Host smart-856f0f4c-f80b-424d-bc1e-d58896790deb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704477605 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_global_esc.2704477605
Directory /workspace/40.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/40.pwrmgr_reset.1398192647
Short name T568
Test name
Test status
Simulation time 77827803 ps
CPU time 0.9 seconds
Started Jul 24 05:08:47 PM PDT 24
Finished Jul 24 05:08:48 PM PDT 24
Peak memory 199696 kb
Host smart-512595ec-465a-4ea6-86ef-36a201eefaf8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398192647 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset.1398192647
Directory /workspace/40.pwrmgr_reset/latest

Test location /workspace/coverage/default/40.pwrmgr_reset_invalid.2596007239
Short name T343
Test name
Test status
Simulation time 170972698 ps
CPU time 0.79 seconds
Started Jul 24 05:08:43 PM PDT 24
Finished Jul 24 05:08:44 PM PDT 24
Peak memory 210100 kb
Host smart-6b825620-cb8c-4933-a4ac-56ed8f697b37
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596007239 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset_invalid.2596007239
Directory /workspace/40.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/40.pwrmgr_sec_cm_rstmgr_intersig_mubi.2050373059
Short name T279
Test name
Test status
Simulation time 136036752 ps
CPU time 0.86 seconds
Started Jul 24 05:08:48 PM PDT 24
Finished Jul 24 05:08:49 PM PDT 24
Peak memory 199808 kb
Host smart-7f6984a4-f93c-46b9-8366-ea67a6269855
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050373059 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2050373059
Directory /workspace/40.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/40.pwrmgr_smoke.63666665
Short name T451
Test name
Test status
Simulation time 55358300 ps
CPU time 0.63 seconds
Started Jul 24 05:09:07 PM PDT 24
Finished Jul 24 05:09:08 PM PDT 24
Peak memory 198944 kb
Host smart-89c77fc3-850b-43f1-8dad-10907d6a88a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63666665 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_smoke.63666665
Directory /workspace/40.pwrmgr_smoke/latest

Test location /workspace/coverage/default/41.pwrmgr_aborted_low_power.2307159613
Short name T628
Test name
Test status
Simulation time 37787470 ps
CPU time 0.83 seconds
Started Jul 24 05:08:58 PM PDT 24
Finished Jul 24 05:08:59 PM PDT 24
Peak memory 200748 kb
Host smart-d36c0cb1-3908-4ba6-96a6-a1ef2a6ba80c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307159613 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_aborted_low_power.2307159613
Directory /workspace/41.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/41.pwrmgr_disable_rom_integrity_check.1293735447
Short name T447
Test name
Test status
Simulation time 65170052 ps
CPU time 0.65 seconds
Started Jul 24 05:08:55 PM PDT 24
Finished Jul 24 05:08:56 PM PDT 24
Peak memory 199668 kb
Host smart-0c74e2ea-8f20-4529-8f29-3e4247cad49a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293735447 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_dis
able_rom_integrity_check.1293735447
Directory /workspace/41.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/41.pwrmgr_esc_clk_rst_malfunc.877241221
Short name T626
Test name
Test status
Simulation time 39080196 ps
CPU time 0.59 seconds
Started Jul 24 05:08:53 PM PDT 24
Finished Jul 24 05:08:54 PM PDT 24
Peak memory 198524 kb
Host smart-dc9a79fc-36fb-465a-827f-fa3763337357
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877241221 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_esc_clk_rst_
malfunc.877241221
Directory /workspace/41.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/41.pwrmgr_escalation_timeout.3550628111
Short name T301
Test name
Test status
Simulation time 163271818 ps
CPU time 0.96 seconds
Started Jul 24 05:09:08 PM PDT 24
Finished Jul 24 05:09:10 PM PDT 24
Peak memory 198588 kb
Host smart-f0fc0e70-d052-4d34-9c98-955fee736de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550628111 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_escalation_timeout.3550628111
Directory /workspace/41.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/41.pwrmgr_glitch.2988669487
Short name T322
Test name
Test status
Simulation time 35169847 ps
CPU time 0.58 seconds
Started Jul 24 05:08:52 PM PDT 24
Finished Jul 24 05:08:52 PM PDT 24
Peak memory 198476 kb
Host smart-8367bfc9-2cec-4709-963d-f05e758afec4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988669487 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_glitch.2988669487
Directory /workspace/41.pwrmgr_glitch/latest

Test location /workspace/coverage/default/41.pwrmgr_global_esc.1508392934
Short name T293
Test name
Test status
Simulation time 73087317 ps
CPU time 0.58 seconds
Started Jul 24 05:08:58 PM PDT 24
Finished Jul 24 05:08:58 PM PDT 24
Peak memory 198956 kb
Host smart-a4526287-3dbe-4fa1-89d9-87e388815f8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508392934 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_global_esc.1508392934
Directory /workspace/41.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/41.pwrmgr_lowpower_invalid.169984933
Short name T169
Test name
Test status
Simulation time 41711926 ps
CPU time 0.69 seconds
Started Jul 24 05:09:09 PM PDT 24
Finished Jul 24 05:09:10 PM PDT 24
Peak memory 201984 kb
Host smart-068f492a-973b-4ce3-9ab3-700697801b4e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169984933 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_lowpower_invali
d.169984933
Directory /workspace/41.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/41.pwrmgr_lowpower_wakeup_race.3771923454
Short name T206
Test name
Test status
Simulation time 59625282 ps
CPU time 0.59 seconds
Started Jul 24 05:08:50 PM PDT 24
Finished Jul 24 05:08:50 PM PDT 24
Peak memory 198612 kb
Host smart-e245ce3c-fab8-4cd4-a6d1-2869ec6fb30f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771923454 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_lowpower_w
akeup_race.3771923454
Directory /workspace/41.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/41.pwrmgr_reset.3218598180
Short name T346
Test name
Test status
Simulation time 115208435 ps
CPU time 0.7 seconds
Started Jul 24 05:08:52 PM PDT 24
Finished Jul 24 05:08:53 PM PDT 24
Peak memory 198868 kb
Host smart-47cfc3b9-7690-4eae-9441-9832475b5485
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218598180 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset.3218598180
Directory /workspace/41.pwrmgr_reset/latest

Test location /workspace/coverage/default/41.pwrmgr_reset_invalid.640738032
Short name T566
Test name
Test status
Simulation time 195080100 ps
CPU time 0.81 seconds
Started Jul 24 05:09:11 PM PDT 24
Finished Jul 24 05:09:12 PM PDT 24
Peak memory 209984 kb
Host smart-d0933a8d-f39e-423d-a373-68cd0892b2f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640738032 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset_invalid.640738032
Directory /workspace/41.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/41.pwrmgr_sec_cm_rstmgr_intersig_mubi.10714595
Short name T542
Test name
Test status
Simulation time 162205334 ps
CPU time 0.75 seconds
Started Jul 24 05:09:17 PM PDT 24
Finished Jul 24 05:09:18 PM PDT 24
Peak memory 199556 kb
Host smart-c7b97f22-4495-4f93-8126-3f91d95bed4a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10714595 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.10714595
Directory /workspace/41.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/41.pwrmgr_smoke.1106850339
Short name T521
Test name
Test status
Simulation time 35825449 ps
CPU time 0.64 seconds
Started Jul 24 05:08:44 PM PDT 24
Finished Jul 24 05:08:44 PM PDT 24
Peak memory 199952 kb
Host smart-1f1b6117-8f74-4d81-a1f3-e71718f2a3e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106850339 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_smoke.1106850339
Directory /workspace/41.pwrmgr_smoke/latest

Test location /workspace/coverage/default/41.pwrmgr_stress_all.242056206
Short name T345
Test name
Test status
Simulation time 82352998 ps
CPU time 0.9 seconds
Started Jul 24 05:09:12 PM PDT 24
Finished Jul 24 05:09:13 PM PDT 24
Peak memory 199624 kb
Host smart-78c0622b-0c11-41d7-b5ef-15b58bef36ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242056206 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_stress_all.242056206
Directory /workspace/41.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/42.pwrmgr_aborted_low_power.3410314191
Short name T119
Test name
Test status
Simulation time 24213599 ps
CPU time 0.78 seconds
Started Jul 24 05:08:52 PM PDT 24
Finished Jul 24 05:08:54 PM PDT 24
Peak memory 200744 kb
Host smart-18f549d1-ea3a-4900-ae06-6b0682dc9666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410314191 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_aborted_low_power.3410314191
Directory /workspace/42.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/42.pwrmgr_disable_rom_integrity_check.2604852414
Short name T554
Test name
Test status
Simulation time 71473241 ps
CPU time 0.69 seconds
Started Jul 24 05:08:47 PM PDT 24
Finished Jul 24 05:08:48 PM PDT 24
Peak memory 199532 kb
Host smart-1db3b267-f840-49d6-8049-bb634c789541
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604852414 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_dis
able_rom_integrity_check.2604852414
Directory /workspace/42.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/42.pwrmgr_esc_clk_rst_malfunc.2458843651
Short name T260
Test name
Test status
Simulation time 29985664 ps
CPU time 0.64 seconds
Started Jul 24 05:09:06 PM PDT 24
Finished Jul 24 05:09:07 PM PDT 24
Peak memory 198540 kb
Host smart-14e5a1a5-9c5b-4273-89b6-14b5bd565ed5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458843651 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_esc_clk_rst
_malfunc.2458843651
Directory /workspace/42.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/42.pwrmgr_escalation_timeout.1905151416
Short name T270
Test name
Test status
Simulation time 315285556 ps
CPU time 0.98 seconds
Started Jul 24 05:08:53 PM PDT 24
Finished Jul 24 05:08:54 PM PDT 24
Peak memory 198608 kb
Host smart-b88e10cd-4e65-4bcc-876c-3be9a75f14b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905151416 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_escalation_timeout.1905151416
Directory /workspace/42.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/42.pwrmgr_glitch.3068099682
Short name T597
Test name
Test status
Simulation time 45512469 ps
CPU time 0.64 seconds
Started Jul 24 05:09:08 PM PDT 24
Finished Jul 24 05:09:09 PM PDT 24
Peak memory 197912 kb
Host smart-9753e883-f14f-416f-aee7-f599ebb1fb3d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068099682 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_glitch.3068099682
Directory /workspace/42.pwrmgr_glitch/latest

Test location /workspace/coverage/default/42.pwrmgr_global_esc.1360189188
Short name T281
Test name
Test status
Simulation time 39840505 ps
CPU time 0.58 seconds
Started Jul 24 05:09:12 PM PDT 24
Finished Jul 24 05:09:13 PM PDT 24
Peak memory 198664 kb
Host smart-d23329a2-5737-4b3a-82d5-a48c4191fa0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360189188 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_global_esc.1360189188
Directory /workspace/42.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/42.pwrmgr_lowpower_invalid.393593633
Short name T164
Test name
Test status
Simulation time 44926247 ps
CPU time 0.67 seconds
Started Jul 24 05:08:35 PM PDT 24
Finished Jul 24 05:08:36 PM PDT 24
Peak memory 201992 kb
Host smart-33903901-1db1-4671-95fe-5d79f46ab03a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393593633 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_lowpower_invali
d.393593633
Directory /workspace/42.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/42.pwrmgr_lowpower_wakeup_race.147879918
Short name T141
Test name
Test status
Simulation time 81903312 ps
CPU time 0.62 seconds
Started Jul 24 05:09:10 PM PDT 24
Finished Jul 24 05:09:10 PM PDT 24
Peak memory 198764 kb
Host smart-2fda89a8-47bb-416f-890c-05e3c49fbc28
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147879918 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_lowpower_wa
keup_race.147879918
Directory /workspace/42.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/42.pwrmgr_reset.3130793778
Short name T563
Test name
Test status
Simulation time 158082070 ps
CPU time 0.67 seconds
Started Jul 24 05:09:11 PM PDT 24
Finished Jul 24 05:09:12 PM PDT 24
Peak memory 198880 kb
Host smart-e3f8f876-17fd-45e4-ba08-c7419de7878f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130793778 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset.3130793778
Directory /workspace/42.pwrmgr_reset/latest

Test location /workspace/coverage/default/42.pwrmgr_reset_invalid.3153171329
Short name T366
Test name
Test status
Simulation time 251092909 ps
CPU time 0.78 seconds
Started Jul 24 05:08:48 PM PDT 24
Finished Jul 24 05:08:49 PM PDT 24
Peak memory 209924 kb
Host smart-4c3b2e15-4125-4b06-ae2f-b6bfc1486b80
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153171329 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset_invalid.3153171329
Directory /workspace/42.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/42.pwrmgr_sec_cm_rstmgr_intersig_mubi.761860715
Short name T603
Test name
Test status
Simulation time 146288875 ps
CPU time 0.88 seconds
Started Jul 24 05:08:53 PM PDT 24
Finished Jul 24 05:08:54 PM PDT 24
Peak memory 199772 kb
Host smart-1d162d19-e7fd-4880-948b-b9b8b3339222
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761860715 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_rstmgr_intersig_
mubi.761860715
Directory /workspace/42.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/42.pwrmgr_smoke.1853216613
Short name T283
Test name
Test status
Simulation time 30625210 ps
CPU time 0.64 seconds
Started Jul 24 05:08:54 PM PDT 24
Finished Jul 24 05:08:54 PM PDT 24
Peak memory 199052 kb
Host smart-07fe8fdb-2708-4614-8cab-12e930e26ff1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853216613 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_smoke.1853216613
Directory /workspace/42.pwrmgr_smoke/latest

Test location /workspace/coverage/default/43.pwrmgr_aborted_low_power.3890096279
Short name T239
Test name
Test status
Simulation time 34934287 ps
CPU time 0.8 seconds
Started Jul 24 05:09:12 PM PDT 24
Finished Jul 24 05:09:13 PM PDT 24
Peak memory 200436 kb
Host smart-5df9f2af-8160-4bb6-89cf-b516419cdead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890096279 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_aborted_low_power.3890096279
Directory /workspace/43.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/43.pwrmgr_disable_rom_integrity_check.2168606990
Short name T189
Test name
Test status
Simulation time 52145804 ps
CPU time 0.76 seconds
Started Jul 24 05:08:52 PM PDT 24
Finished Jul 24 05:08:53 PM PDT 24
Peak memory 199684 kb
Host smart-a50c7b51-06d5-4e16-a36f-ea798274ddc2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168606990 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_dis
able_rom_integrity_check.2168606990
Directory /workspace/43.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/43.pwrmgr_esc_clk_rst_malfunc.286972357
Short name T132
Test name
Test status
Simulation time 39132532 ps
CPU time 0.57 seconds
Started Jul 24 05:08:56 PM PDT 24
Finished Jul 24 05:08:56 PM PDT 24
Peak memory 198584 kb
Host smart-2bebe2df-8a45-4049-ab3d-19ce8fa539a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286972357 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_esc_clk_rst_
malfunc.286972357
Directory /workspace/43.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/43.pwrmgr_escalation_timeout.3310872164
Short name T263
Test name
Test status
Simulation time 612475849 ps
CPU time 0.94 seconds
Started Jul 24 05:09:03 PM PDT 24
Finished Jul 24 05:09:04 PM PDT 24
Peak memory 198672 kb
Host smart-3fef4471-e78f-4b5a-b6fc-17d628de6ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310872164 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_escalation_timeout.3310872164
Directory /workspace/43.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/43.pwrmgr_glitch.1076950500
Short name T486
Test name
Test status
Simulation time 69157097 ps
CPU time 0.62 seconds
Started Jul 24 05:08:52 PM PDT 24
Finished Jul 24 05:08:53 PM PDT 24
Peak memory 198552 kb
Host smart-4e9ec425-986a-4eb1-bfc5-bea06f5eef41
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076950500 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_glitch.1076950500
Directory /workspace/43.pwrmgr_glitch/latest

Test location /workspace/coverage/default/43.pwrmgr_global_esc.3888740975
Short name T306
Test name
Test status
Simulation time 44631100 ps
CPU time 0.6 seconds
Started Jul 24 05:09:06 PM PDT 24
Finished Jul 24 05:09:07 PM PDT 24
Peak memory 198912 kb
Host smart-889d1558-40dd-425e-8d2a-c09b7d4405fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888740975 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_global_esc.3888740975
Directory /workspace/43.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/43.pwrmgr_lowpower_invalid.3915073943
Short name T159
Test name
Test status
Simulation time 39155088 ps
CPU time 0.73 seconds
Started Jul 24 05:09:07 PM PDT 24
Finished Jul 24 05:09:08 PM PDT 24
Peak memory 201848 kb
Host smart-ac537050-48ea-4a9e-8c1d-85c06a0b4d66
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915073943 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_lowpower_inval
id.3915073943
Directory /workspace/43.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/43.pwrmgr_reset.1537807149
Short name T380
Test name
Test status
Simulation time 47049856 ps
CPU time 0.78 seconds
Started Jul 24 05:09:08 PM PDT 24
Finished Jul 24 05:09:09 PM PDT 24
Peak memory 199732 kb
Host smart-c2f1d4b1-5f84-4f23-b38b-75dd19682e89
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537807149 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset.1537807149
Directory /workspace/43.pwrmgr_reset/latest

Test location /workspace/coverage/default/43.pwrmgr_reset_invalid.3478758019
Short name T539
Test name
Test status
Simulation time 92602866 ps
CPU time 1.08 seconds
Started Jul 24 05:09:10 PM PDT 24
Finished Jul 24 05:09:11 PM PDT 24
Peak memory 209948 kb
Host smart-8a4b8a2d-b1d7-41de-8e2b-4dae91e3de68
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478758019 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset_invalid.3478758019
Directory /workspace/43.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/43.pwrmgr_sec_cm_rstmgr_intersig_mubi.1024304547
Short name T287
Test name
Test status
Simulation time 64278106 ps
CPU time 0.75 seconds
Started Jul 24 05:08:56 PM PDT 24
Finished Jul 24 05:08:56 PM PDT 24
Peak memory 198720 kb
Host smart-9d82887c-fca4-496f-a51e-d83c5477af81
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024304547 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1024304547
Directory /workspace/43.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/43.pwrmgr_smoke.1555824479
Short name T619
Test name
Test status
Simulation time 59184798 ps
CPU time 0.64 seconds
Started Jul 24 05:09:10 PM PDT 24
Finished Jul 24 05:09:11 PM PDT 24
Peak memory 199828 kb
Host smart-4b550396-3179-4cbd-8f4c-10a84d34d359
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555824479 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_smoke.1555824479
Directory /workspace/43.pwrmgr_smoke/latest

Test location /workspace/coverage/default/44.pwrmgr_aborted_low_power.1312576533
Short name T606
Test name
Test status
Simulation time 41042972 ps
CPU time 0.84 seconds
Started Jul 24 05:09:08 PM PDT 24
Finished Jul 24 05:09:09 PM PDT 24
Peak memory 200704 kb
Host smart-2cec712a-9b7e-470e-958f-19cd56d8c541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312576533 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_aborted_low_power.1312576533
Directory /workspace/44.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/44.pwrmgr_disable_rom_integrity_check.2169802331
Short name T135
Test name
Test status
Simulation time 83525547 ps
CPU time 0.67 seconds
Started Jul 24 05:09:06 PM PDT 24
Finished Jul 24 05:09:07 PM PDT 24
Peak memory 199568 kb
Host smart-216ff11c-bae6-46cf-b833-eacc1fc1fc8e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169802331 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_dis
able_rom_integrity_check.2169802331
Directory /workspace/44.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/44.pwrmgr_esc_clk_rst_malfunc.2912283569
Short name T555
Test name
Test status
Simulation time 38734467 ps
CPU time 0.6 seconds
Started Jul 24 05:08:53 PM PDT 24
Finished Jul 24 05:08:54 PM PDT 24
Peak memory 198468 kb
Host smart-ef333b2c-ea9a-4576-b320-62028416f60f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912283569 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_esc_clk_rst
_malfunc.2912283569
Directory /workspace/44.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/44.pwrmgr_escalation_timeout.1681957359
Short name T413
Test name
Test status
Simulation time 834576366 ps
CPU time 0.94 seconds
Started Jul 24 05:09:11 PM PDT 24
Finished Jul 24 05:09:12 PM PDT 24
Peak memory 198572 kb
Host smart-0d516212-38a4-4726-8172-09d3c379a459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681957359 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_escalation_timeout.1681957359
Directory /workspace/44.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/44.pwrmgr_glitch.3929539132
Short name T290
Test name
Test status
Simulation time 76163553 ps
CPU time 0.6 seconds
Started Jul 24 05:09:12 PM PDT 24
Finished Jul 24 05:09:13 PM PDT 24
Peak memory 197960 kb
Host smart-a75abf6a-585d-4552-9dcc-4dc8e203b4dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929539132 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_glitch.3929539132
Directory /workspace/44.pwrmgr_glitch/latest

Test location /workspace/coverage/default/44.pwrmgr_global_esc.3581302510
Short name T231
Test name
Test status
Simulation time 62251309 ps
CPU time 0.62 seconds
Started Jul 24 05:09:00 PM PDT 24
Finished Jul 24 05:09:01 PM PDT 24
Peak memory 198908 kb
Host smart-bb0bd17d-6663-4b83-9fd2-0f8ee92f735b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581302510 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_global_esc.3581302510
Directory /workspace/44.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/44.pwrmgr_lowpower_invalid.105894501
Short name T163
Test name
Test status
Simulation time 48865473 ps
CPU time 0.69 seconds
Started Jul 24 05:09:03 PM PDT 24
Finished Jul 24 05:09:04 PM PDT 24
Peak memory 201584 kb
Host smart-fc328115-49b2-482c-aed4-627672b11c36
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105894501 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_lowpower_invali
d.105894501
Directory /workspace/44.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/44.pwrmgr_reset.1001077309
Short name T43
Test name
Test status
Simulation time 77389535 ps
CPU time 0.74 seconds
Started Jul 24 05:08:51 PM PDT 24
Finished Jul 24 05:08:52 PM PDT 24
Peak memory 199516 kb
Host smart-084f0608-8457-446e-9b11-678d87f0dd49
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001077309 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset.1001077309
Directory /workspace/44.pwrmgr_reset/latest

Test location /workspace/coverage/default/44.pwrmgr_reset_invalid.1648808466
Short name T504
Test name
Test status
Simulation time 165284089 ps
CPU time 0.78 seconds
Started Jul 24 05:09:01 PM PDT 24
Finished Jul 24 05:09:02 PM PDT 24
Peak memory 210064 kb
Host smart-cfbbe031-8e4f-49b9-924f-d5767339c95c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648808466 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset_invalid.1648808466
Directory /workspace/44.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/44.pwrmgr_sec_cm_rstmgr_intersig_mubi.1801928641
Short name T344
Test name
Test status
Simulation time 177973210 ps
CPU time 0.81 seconds
Started Jul 24 05:09:06 PM PDT 24
Finished Jul 24 05:09:07 PM PDT 24
Peak memory 198512 kb
Host smart-26e261ce-1664-4b0b-ad47-953e124c59a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801928641 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1801928641
Directory /workspace/44.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/44.pwrmgr_smoke.1175308760
Short name T310
Test name
Test status
Simulation time 30394813 ps
CPU time 0.65 seconds
Started Jul 24 05:09:05 PM PDT 24
Finished Jul 24 05:09:06 PM PDT 24
Peak memory 199892 kb
Host smart-10847303-8840-4c8f-b7e8-3cc0f99a011f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175308760 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_smoke.1175308760
Directory /workspace/44.pwrmgr_smoke/latest

Test location /workspace/coverage/default/45.pwrmgr_aborted_low_power.248173410
Short name T121
Test name
Test status
Simulation time 78389397 ps
CPU time 0.69 seconds
Started Jul 24 05:09:08 PM PDT 24
Finished Jul 24 05:09:08 PM PDT 24
Peak memory 199144 kb
Host smart-36da6901-41b5-459a-b541-4da190641978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248173410 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_aborted_low_power.248173410
Directory /workspace/45.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/45.pwrmgr_disable_rom_integrity_check.3931522491
Short name T28
Test name
Test status
Simulation time 52132678 ps
CPU time 0.78 seconds
Started Jul 24 05:09:03 PM PDT 24
Finished Jul 24 05:09:04 PM PDT 24
Peak memory 198988 kb
Host smart-d0f84bee-1375-47f7-9e8d-9406d9027075
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931522491 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_dis
able_rom_integrity_check.3931522491
Directory /workspace/45.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/45.pwrmgr_esc_clk_rst_malfunc.2271103295
Short name T601
Test name
Test status
Simulation time 31604201 ps
CPU time 0.67 seconds
Started Jul 24 05:09:15 PM PDT 24
Finished Jul 24 05:09:16 PM PDT 24
Peak memory 198488 kb
Host smart-a5c36269-f477-4044-a31b-d8963ab9279b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271103295 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_esc_clk_rst
_malfunc.2271103295
Directory /workspace/45.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/45.pwrmgr_escalation_timeout.3607857499
Short name T276
Test name
Test status
Simulation time 598409651 ps
CPU time 0.99 seconds
Started Jul 24 05:09:06 PM PDT 24
Finished Jul 24 05:09:07 PM PDT 24
Peak memory 198640 kb
Host smart-abe54e07-209b-45c2-a79b-191f30c30087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607857499 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_escalation_timeout.3607857499
Directory /workspace/45.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/45.pwrmgr_glitch.2808661223
Short name T39
Test name
Test status
Simulation time 28203963 ps
CPU time 0.63 seconds
Started Jul 24 05:09:08 PM PDT 24
Finished Jul 24 05:09:09 PM PDT 24
Peak memory 197928 kb
Host smart-136158de-9acb-4943-83da-f18e0c7a6aac
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808661223 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_glitch.2808661223
Directory /workspace/45.pwrmgr_glitch/latest

Test location /workspace/coverage/default/45.pwrmgr_global_esc.2385732373
Short name T316
Test name
Test status
Simulation time 30988866 ps
CPU time 0.61 seconds
Started Jul 24 05:09:22 PM PDT 24
Finished Jul 24 05:09:23 PM PDT 24
Peak memory 198936 kb
Host smart-5fc73928-9b53-4922-9bd1-a0cc46aca575
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385732373 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_global_esc.2385732373
Directory /workspace/45.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/45.pwrmgr_lowpower_invalid.1387558721
Short name T178
Test name
Test status
Simulation time 45351815 ps
CPU time 0.72 seconds
Started Jul 24 05:08:55 PM PDT 24
Finished Jul 24 05:08:56 PM PDT 24
Peak memory 201940 kb
Host smart-131e2886-95ef-4500-aa49-f7f63b701fec
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387558721 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_lowpower_inval
id.1387558721
Directory /workspace/45.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/45.pwrmgr_reset.1913678955
Short name T453
Test name
Test status
Simulation time 35945807 ps
CPU time 0.68 seconds
Started Jul 24 05:09:17 PM PDT 24
Finished Jul 24 05:09:18 PM PDT 24
Peak memory 198700 kb
Host smart-6857c6a9-813c-4f1c-923c-be0063a850b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913678955 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset.1913678955
Directory /workspace/45.pwrmgr_reset/latest

Test location /workspace/coverage/default/45.pwrmgr_reset_invalid.3326017791
Short name T259
Test name
Test status
Simulation time 164534650 ps
CPU time 0.79 seconds
Started Jul 24 05:09:07 PM PDT 24
Finished Jul 24 05:09:08 PM PDT 24
Peak memory 209896 kb
Host smart-81bc8c49-8348-4188-b1ee-d5a71d42a8a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326017791 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset_invalid.3326017791
Directory /workspace/45.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/45.pwrmgr_sec_cm_rstmgr_intersig_mubi.1710639886
Short name T499
Test name
Test status
Simulation time 77108673 ps
CPU time 0.76 seconds
Started Jul 24 05:09:00 PM PDT 24
Finished Jul 24 05:09:01 PM PDT 24
Peak memory 198616 kb
Host smart-8adb5563-756e-4aed-af6f-11a65d8eeed6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710639886 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1710639886
Directory /workspace/45.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/45.pwrmgr_smoke.3015231406
Short name T382
Test name
Test status
Simulation time 28364465 ps
CPU time 0.67 seconds
Started Jul 24 05:08:52 PM PDT 24
Finished Jul 24 05:08:53 PM PDT 24
Peak memory 199876 kb
Host smart-51aa8940-5cd2-4b93-9f3a-9265fbfa51c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015231406 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_smoke.3015231406
Directory /workspace/45.pwrmgr_smoke/latest

Test location /workspace/coverage/default/46.pwrmgr_aborted_low_power.1817181393
Short name T506
Test name
Test status
Simulation time 46454124 ps
CPU time 0.73 seconds
Started Jul 24 05:09:09 PM PDT 24
Finished Jul 24 05:09:10 PM PDT 24
Peak memory 199316 kb
Host smart-1be6d110-52db-4aa4-84c1-512fff0ef035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817181393 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_aborted_low_power.1817181393
Directory /workspace/46.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/46.pwrmgr_disable_rom_integrity_check.2242704256
Short name T198
Test name
Test status
Simulation time 49146781 ps
CPU time 0.78 seconds
Started Jul 24 05:09:08 PM PDT 24
Finished Jul 24 05:09:09 PM PDT 24
Peak memory 199120 kb
Host smart-aef9c01b-ffe6-4363-ad7e-95e07f7583a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242704256 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_dis
able_rom_integrity_check.2242704256
Directory /workspace/46.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/46.pwrmgr_esc_clk_rst_malfunc.3905675009
Short name T275
Test name
Test status
Simulation time 43052924 ps
CPU time 0.6 seconds
Started Jul 24 05:09:11 PM PDT 24
Finished Jul 24 05:09:12 PM PDT 24
Peak memory 198500 kb
Host smart-314eed57-8f2d-40bd-a9af-285def43bfde
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905675009 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_esc_clk_rst
_malfunc.3905675009
Directory /workspace/46.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/46.pwrmgr_escalation_timeout.2859208529
Short name T360
Test name
Test status
Simulation time 306157450 ps
CPU time 0.97 seconds
Started Jul 24 05:09:18 PM PDT 24
Finished Jul 24 05:09:19 PM PDT 24
Peak memory 198640 kb
Host smart-d816686b-03b4-4f44-8ec5-748ec58de91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859208529 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_escalation_timeout.2859208529
Directory /workspace/46.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/46.pwrmgr_glitch.2416132205
Short name T350
Test name
Test status
Simulation time 35856171 ps
CPU time 0.61 seconds
Started Jul 24 05:09:29 PM PDT 24
Finished Jul 24 05:09:30 PM PDT 24
Peak memory 198656 kb
Host smart-3c4149be-8f38-4e82-b8df-8b8315d41c68
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416132205 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_glitch.2416132205
Directory /workspace/46.pwrmgr_glitch/latest

Test location /workspace/coverage/default/46.pwrmgr_global_esc.2911070631
Short name T384
Test name
Test status
Simulation time 55092198 ps
CPU time 0.58 seconds
Started Jul 24 05:09:07 PM PDT 24
Finished Jul 24 05:09:08 PM PDT 24
Peak memory 198644 kb
Host smart-2bedd39b-b105-4c23-bef5-ceb623f1eafc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911070631 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_global_esc.2911070631
Directory /workspace/46.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/46.pwrmgr_lowpower_invalid.3030405009
Short name T162
Test name
Test status
Simulation time 44918279 ps
CPU time 0.74 seconds
Started Jul 24 05:09:07 PM PDT 24
Finished Jul 24 05:09:08 PM PDT 24
Peak memory 201880 kb
Host smart-6bf9fabb-cdb8-4335-b87a-1e78c9f0d2e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030405009 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_lowpower_inval
id.3030405009
Directory /workspace/46.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/46.pwrmgr_reset.1179453801
Short name T423
Test name
Test status
Simulation time 101662538 ps
CPU time 0.69 seconds
Started Jul 24 05:09:08 PM PDT 24
Finished Jul 24 05:09:09 PM PDT 24
Peak memory 199644 kb
Host smart-94404fdf-a4d0-475b-834d-14511dfbde1c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179453801 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset.1179453801
Directory /workspace/46.pwrmgr_reset/latest

Test location /workspace/coverage/default/46.pwrmgr_reset_invalid.554705330
Short name T531
Test name
Test status
Simulation time 127371641 ps
CPU time 0.84 seconds
Started Jul 24 05:09:20 PM PDT 24
Finished Jul 24 05:09:21 PM PDT 24
Peak memory 209868 kb
Host smart-afccdcb6-5858-4deb-865d-b3e3360779f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554705330 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset_invalid.554705330
Directory /workspace/46.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/46.pwrmgr_sec_cm_rstmgr_intersig_mubi.1058182252
Short name T271
Test name
Test status
Simulation time 82361548 ps
CPU time 0.73 seconds
Started Jul 24 05:09:26 PM PDT 24
Finished Jul 24 05:09:27 PM PDT 24
Peak memory 198684 kb
Host smart-9563bd6b-68f6-4936-b759-f8005eb6a47f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058182252 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1058182252
Directory /workspace/46.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/46.pwrmgr_smoke.4174365391
Short name T228
Test name
Test status
Simulation time 28797503 ps
CPU time 0.68 seconds
Started Jul 24 05:09:15 PM PDT 24
Finished Jul 24 05:09:16 PM PDT 24
Peak memory 199816 kb
Host smart-7cf76e67-5709-4ad9-8847-cb00fbd3ac90
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174365391 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_smoke.4174365391
Directory /workspace/46.pwrmgr_smoke/latest

Test location /workspace/coverage/default/47.pwrmgr_aborted_low_power.90003552
Short name T154
Test name
Test status
Simulation time 96106670 ps
CPU time 0.88 seconds
Started Jul 24 05:09:18 PM PDT 24
Finished Jul 24 05:09:19 PM PDT 24
Peak memory 200528 kb
Host smart-86bf6273-944f-4bae-99a0-c4d27762af62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90003552 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_aborted_low_power.90003552
Directory /workspace/47.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/47.pwrmgr_disable_rom_integrity_check.3243921974
Short name T202
Test name
Test status
Simulation time 82441127 ps
CPU time 0.68 seconds
Started Jul 24 05:09:10 PM PDT 24
Finished Jul 24 05:09:10 PM PDT 24
Peak memory 200056 kb
Host smart-c187655c-b127-473a-a272-5b7e53cbca22
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243921974 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_dis
able_rom_integrity_check.3243921974
Directory /workspace/47.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/47.pwrmgr_esc_clk_rst_malfunc.1259567382
Short name T364
Test name
Test status
Simulation time 40040734 ps
CPU time 0.59 seconds
Started Jul 24 05:09:18 PM PDT 24
Finished Jul 24 05:09:19 PM PDT 24
Peak memory 198576 kb
Host smart-2c4e513c-3791-46cb-891b-aed642132ae2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259567382 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_esc_clk_rst
_malfunc.1259567382
Directory /workspace/47.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/47.pwrmgr_escalation_timeout.3428273800
Short name T586
Test name
Test status
Simulation time 314522964 ps
CPU time 0.95 seconds
Started Jul 24 05:09:18 PM PDT 24
Finished Jul 24 05:09:19 PM PDT 24
Peak memory 198672 kb
Host smart-b441607a-4170-4e57-b3f7-d7517322b3d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428273800 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_escalation_timeout.3428273800
Directory /workspace/47.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/47.pwrmgr_glitch.1016078687
Short name T493
Test name
Test status
Simulation time 41907069 ps
CPU time 0.62 seconds
Started Jul 24 05:09:33 PM PDT 24
Finished Jul 24 05:09:34 PM PDT 24
Peak memory 198580 kb
Host smart-e95b525b-a24f-46ef-91fc-0773f06d8575
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016078687 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_glitch.1016078687
Directory /workspace/47.pwrmgr_glitch/latest

Test location /workspace/coverage/default/47.pwrmgr_global_esc.4066622907
Short name T627
Test name
Test status
Simulation time 46167009 ps
CPU time 0.65 seconds
Started Jul 24 05:09:12 PM PDT 24
Finished Jul 24 05:09:13 PM PDT 24
Peak memory 198480 kb
Host smart-ccf3e5da-960f-4781-ac83-7bd29782d597
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066622907 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_global_esc.4066622907
Directory /workspace/47.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/47.pwrmgr_lowpower_invalid.200722031
Short name T174
Test name
Test status
Simulation time 45112066 ps
CPU time 0.73 seconds
Started Jul 24 05:09:29 PM PDT 24
Finished Jul 24 05:09:30 PM PDT 24
Peak memory 201980 kb
Host smart-ffe123de-7728-4837-9fde-756d83c5e6c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200722031 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_lowpower_invali
d.200722031
Directory /workspace/47.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/47.pwrmgr_reset.4126584687
Short name T365
Test name
Test status
Simulation time 91837395 ps
CPU time 0.8 seconds
Started Jul 24 05:09:16 PM PDT 24
Finished Jul 24 05:09:17 PM PDT 24
Peak memory 198876 kb
Host smart-94a7e1e0-4193-4958-b3e8-a37523d8ca68
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126584687 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset.4126584687
Directory /workspace/47.pwrmgr_reset/latest

Test location /workspace/coverage/default/47.pwrmgr_reset_invalid.2342267856
Short name T433
Test name
Test status
Simulation time 144492552 ps
CPU time 0.83 seconds
Started Jul 24 05:09:18 PM PDT 24
Finished Jul 24 05:09:19 PM PDT 24
Peak memory 210028 kb
Host smart-fb98baeb-605a-44c2-90b6-f426af1b8c55
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342267856 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset_invalid.2342267856
Directory /workspace/47.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/47.pwrmgr_sec_cm_ctrl_config_regwen.910656949
Short name T572
Test name
Test status
Simulation time 52302851 ps
CPU time 0.6 seconds
Started Jul 24 05:09:15 PM PDT 24
Finished Jul 24 05:09:15 PM PDT 24
Peak memory 199060 kb
Host smart-db937e5f-db92-4326-ad2a-4e4b75d23c91
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910656949 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_c
m_ctrl_config_regwen.910656949
Directory /workspace/47.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/47.pwrmgr_sec_cm_rstmgr_intersig_mubi.3607154245
Short name T538
Test name
Test status
Simulation time 126435777 ps
CPU time 0.72 seconds
Started Jul 24 05:09:25 PM PDT 24
Finished Jul 24 05:09:26 PM PDT 24
Peak memory 198808 kb
Host smart-9bfff67f-3210-4eb7-8b9e-b7f8c1875d95
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607154245 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3607154245
Directory /workspace/47.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/47.pwrmgr_smoke.2268365375
Short name T508
Test name
Test status
Simulation time 30258817 ps
CPU time 0.73 seconds
Started Jul 24 05:09:10 PM PDT 24
Finished Jul 24 05:09:11 PM PDT 24
Peak memory 199852 kb
Host smart-da4b3f9f-335d-463e-9fca-885f360b65c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268365375 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_smoke.2268365375
Directory /workspace/47.pwrmgr_smoke/latest

Test location /workspace/coverage/default/48.pwrmgr_aborted_low_power.492261339
Short name T317
Test name
Test status
Simulation time 31588248 ps
CPU time 1.03 seconds
Started Jul 24 05:09:11 PM PDT 24
Finished Jul 24 05:09:12 PM PDT 24
Peak memory 201540 kb
Host smart-0db0486d-04ac-4acd-9afc-c3bb037a7797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492261339 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_aborted_low_power.492261339
Directory /workspace/48.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/48.pwrmgr_esc_clk_rst_malfunc.2599591579
Short name T243
Test name
Test status
Simulation time 33183780 ps
CPU time 0.59 seconds
Started Jul 24 05:09:23 PM PDT 24
Finished Jul 24 05:09:23 PM PDT 24
Peak memory 198604 kb
Host smart-8a25e90b-8bb1-4844-81e4-b66e92ace6d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599591579 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_esc_clk_rst
_malfunc.2599591579
Directory /workspace/48.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/48.pwrmgr_escalation_timeout.3639094556
Short name T302
Test name
Test status
Simulation time 164652063 ps
CPU time 1 seconds
Started Jul 24 05:09:19 PM PDT 24
Finished Jul 24 05:09:25 PM PDT 24
Peak memory 198944 kb
Host smart-fa8f9159-90be-450c-b8d4-d1bc10493a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639094556 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_escalation_timeout.3639094556
Directory /workspace/48.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/48.pwrmgr_glitch.801492462
Short name T217
Test name
Test status
Simulation time 47597713 ps
CPU time 0.65 seconds
Started Jul 24 05:09:10 PM PDT 24
Finished Jul 24 05:09:11 PM PDT 24
Peak memory 197776 kb
Host smart-a3b773c4-84e2-48ae-89dc-95cd4d92f2b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801492462 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_glitch.801492462
Directory /workspace/48.pwrmgr_glitch/latest

Test location /workspace/coverage/default/48.pwrmgr_global_esc.1486558883
Short name T591
Test name
Test status
Simulation time 39668633 ps
CPU time 0.66 seconds
Started Jul 24 05:09:06 PM PDT 24
Finished Jul 24 05:09:07 PM PDT 24
Peak memory 198544 kb
Host smart-50bf971f-70d7-4c31-a14e-d1d95601d615
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486558883 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_global_esc.1486558883
Directory /workspace/48.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/48.pwrmgr_lowpower_invalid.2637405638
Short name T165
Test name
Test status
Simulation time 41312796 ps
CPU time 0.77 seconds
Started Jul 24 05:08:59 PM PDT 24
Finished Jul 24 05:09:00 PM PDT 24
Peak memory 201988 kb
Host smart-5b9a12d9-d07e-48dc-8457-d28e64840805
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637405638 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_lowpower_inval
id.2637405638
Directory /workspace/48.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/48.pwrmgr_reset.1588835912
Short name T307
Test name
Test status
Simulation time 108282743 ps
CPU time 0.8 seconds
Started Jul 24 05:09:07 PM PDT 24
Finished Jul 24 05:09:08 PM PDT 24
Peak memory 199084 kb
Host smart-25614ff4-2d15-4525-81ba-77bb5f343b6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588835912 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset.1588835912
Directory /workspace/48.pwrmgr_reset/latest

Test location /workspace/coverage/default/48.pwrmgr_reset_invalid.3750681090
Short name T401
Test name
Test status
Simulation time 161934297 ps
CPU time 0.76 seconds
Started Jul 24 05:08:59 PM PDT 24
Finished Jul 24 05:09:00 PM PDT 24
Peak memory 201852 kb
Host smart-0c1ff5e0-33b3-414a-b39c-9d174f74b9f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750681090 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset_invalid.3750681090
Directory /workspace/48.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/48.pwrmgr_sec_cm_rstmgr_intersig_mubi.3396309449
Short name T576
Test name
Test status
Simulation time 94738387 ps
CPU time 0.73 seconds
Started Jul 24 05:09:07 PM PDT 24
Finished Jul 24 05:09:08 PM PDT 24
Peak memory 199568 kb
Host smart-4dad8cf6-509d-45e1-8c9c-5aa5af58e895
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396309449 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3396309449
Directory /workspace/48.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/48.pwrmgr_smoke.2347221496
Short name T596
Test name
Test status
Simulation time 160728739 ps
CPU time 0.62 seconds
Started Jul 24 05:09:02 PM PDT 24
Finished Jul 24 05:09:03 PM PDT 24
Peak memory 199056 kb
Host smart-a631dba9-b07e-4f83-9814-0f4deacf55ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347221496 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_smoke.2347221496
Directory /workspace/48.pwrmgr_smoke/latest

Test location /workspace/coverage/default/49.pwrmgr_aborted_low_power.2020688211
Short name T416
Test name
Test status
Simulation time 53651631 ps
CPU time 0.88 seconds
Started Jul 24 05:09:13 PM PDT 24
Finished Jul 24 05:09:14 PM PDT 24
Peak memory 200980 kb
Host smart-b2fce2ee-d617-48ce-b72f-633c83ca9ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020688211 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_aborted_low_power.2020688211
Directory /workspace/49.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/49.pwrmgr_disable_rom_integrity_check.269725621
Short name T300
Test name
Test status
Simulation time 74848798 ps
CPU time 0.65 seconds
Started Jul 24 05:09:43 PM PDT 24
Finished Jul 24 05:09:49 PM PDT 24
Peak memory 198768 kb
Host smart-f55a65d5-1104-49d5-abeb-f834f25a9063
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269725621 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_disa
ble_rom_integrity_check.269725621
Directory /workspace/49.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/49.pwrmgr_esc_clk_rst_malfunc.3046246018
Short name T466
Test name
Test status
Simulation time 40285970 ps
CPU time 0.58 seconds
Started Jul 24 05:09:01 PM PDT 24
Finished Jul 24 05:09:02 PM PDT 24
Peak memory 198572 kb
Host smart-0c0a4c79-cf7c-4c46-a5fc-b8f457d081ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046246018 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_esc_clk_rst
_malfunc.3046246018
Directory /workspace/49.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/49.pwrmgr_escalation_timeout.864955160
Short name T533
Test name
Test status
Simulation time 563661297 ps
CPU time 0.97 seconds
Started Jul 24 05:09:10 PM PDT 24
Finished Jul 24 05:09:11 PM PDT 24
Peak memory 198612 kb
Host smart-66e91d2c-2801-4a5d-b08f-f93a65a4cfc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864955160 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_escalation_timeout.864955160
Directory /workspace/49.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/49.pwrmgr_glitch.2807743307
Short name T220
Test name
Test status
Simulation time 68116997 ps
CPU time 0.62 seconds
Started Jul 24 05:09:24 PM PDT 24
Finished Jul 24 05:09:29 PM PDT 24
Peak memory 197888 kb
Host smart-a0fbe187-b9c8-4c4f-ad1b-c2f2f358a246
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807743307 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_glitch.2807743307
Directory /workspace/49.pwrmgr_glitch/latest

Test location /workspace/coverage/default/49.pwrmgr_global_esc.3504932088
Short name T262
Test name
Test status
Simulation time 78196711 ps
CPU time 0.62 seconds
Started Jul 24 05:09:27 PM PDT 24
Finished Jul 24 05:09:28 PM PDT 24
Peak memory 198720 kb
Host smart-9bdf4345-8d1d-4c8f-bd9b-0aff6667548c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504932088 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_global_esc.3504932088
Directory /workspace/49.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/49.pwrmgr_reset.656394025
Short name T496
Test name
Test status
Simulation time 48009064 ps
CPU time 0.75 seconds
Started Jul 24 05:09:26 PM PDT 24
Finished Jul 24 05:09:27 PM PDT 24
Peak memory 198936 kb
Host smart-c5a6bd23-799b-4410-94ce-7a64f6c65bd0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656394025 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset.656394025
Directory /workspace/49.pwrmgr_reset/latest

Test location /workspace/coverage/default/49.pwrmgr_reset_invalid.597130856
Short name T579
Test name
Test status
Simulation time 149439322 ps
CPU time 0.9 seconds
Started Jul 24 05:09:20 PM PDT 24
Finished Jul 24 05:09:21 PM PDT 24
Peak memory 210096 kb
Host smart-4dbc2ef1-4f62-4cf5-835e-99c066138538
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597130856 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset_invalid.597130856
Directory /workspace/49.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/49.pwrmgr_sec_cm_rstmgr_intersig_mubi.3770316436
Short name T73
Test name
Test status
Simulation time 94931381 ps
CPU time 0.84 seconds
Started Jul 24 05:09:12 PM PDT 24
Finished Jul 24 05:09:13 PM PDT 24
Peak memory 199564 kb
Host smart-52c5e9b6-b2af-4685-9c62-654ce56869ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770316436 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3770316436
Directory /workspace/49.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/49.pwrmgr_smoke.2957085908
Short name T264
Test name
Test status
Simulation time 56080668 ps
CPU time 0.62 seconds
Started Jul 24 05:08:58 PM PDT 24
Finished Jul 24 05:08:58 PM PDT 24
Peak memory 199832 kb
Host smart-35976e8f-d43c-4e63-b480-f0418719f7b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957085908 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_smoke.2957085908
Directory /workspace/49.pwrmgr_smoke/latest

Test location /workspace/coverage/default/5.pwrmgr_aborted_low_power.3461798665
Short name T440
Test name
Test status
Simulation time 32739701 ps
CPU time 0.73 seconds
Started Jul 24 05:07:26 PM PDT 24
Finished Jul 24 05:07:27 PM PDT 24
Peak memory 199700 kb
Host smart-8c1d341e-670b-470b-8602-19f0e16b2f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461798665 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_aborted_low_power.3461798665
Directory /workspace/5.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/5.pwrmgr_disable_rom_integrity_check.378652024
Short name T133
Test name
Test status
Simulation time 51196223 ps
CPU time 0.73 seconds
Started Jul 24 05:07:34 PM PDT 24
Finished Jul 24 05:07:35 PM PDT 24
Peak memory 199640 kb
Host smart-9a898094-27eb-4659-a5ba-5d53e802ac8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378652024 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_disab
le_rom_integrity_check.378652024
Directory /workspace/5.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/5.pwrmgr_esc_clk_rst_malfunc.3637245556
Short name T9
Test name
Test status
Simulation time 32053840 ps
CPU time 0.65 seconds
Started Jul 24 05:07:17 PM PDT 24
Finished Jul 24 05:07:17 PM PDT 24
Peak memory 198056 kb
Host smart-7aaa6586-7039-4c95-8f9f-17ba574a70c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637245556 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_esc_clk_rst_
malfunc.3637245556
Directory /workspace/5.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/5.pwrmgr_escalation_timeout.4194500906
Short name T510
Test name
Test status
Simulation time 163677898 ps
CPU time 0.94 seconds
Started Jul 24 05:07:18 PM PDT 24
Finished Jul 24 05:07:19 PM PDT 24
Peak memory 198664 kb
Host smart-e820bc6d-cb24-42b3-82a7-1920c8f2c8fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194500906 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_escalation_timeout.4194500906
Directory /workspace/5.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/5.pwrmgr_glitch.3888789908
Short name T267
Test name
Test status
Simulation time 84493183 ps
CPU time 0.6 seconds
Started Jul 24 05:07:30 PM PDT 24
Finished Jul 24 05:07:31 PM PDT 24
Peak memory 197848 kb
Host smart-3dd860a6-7e12-4128-8948-40163de646a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888789908 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_glitch.3888789908
Directory /workspace/5.pwrmgr_glitch/latest

Test location /workspace/coverage/default/5.pwrmgr_global_esc.1584087813
Short name T249
Test name
Test status
Simulation time 35628722 ps
CPU time 0.72 seconds
Started Jul 24 05:07:23 PM PDT 24
Finished Jul 24 05:07:24 PM PDT 24
Peak memory 198476 kb
Host smart-6f74cce4-236b-487e-9375-1293630560f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584087813 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_global_esc.1584087813
Directory /workspace/5.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/5.pwrmgr_lowpower_invalid.479458854
Short name T166
Test name
Test status
Simulation time 48000743 ps
CPU time 0.7 seconds
Started Jul 24 05:07:15 PM PDT 24
Finished Jul 24 05:07:16 PM PDT 24
Peak memory 201616 kb
Host smart-f976af88-4915-4409-9aca-2724e677f968
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479458854 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_lowpower_invalid
.479458854
Directory /workspace/5.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/5.pwrmgr_reset.3219910436
Short name T410
Test name
Test status
Simulation time 63447439 ps
CPU time 0.74 seconds
Started Jul 24 05:07:30 PM PDT 24
Finished Jul 24 05:07:31 PM PDT 24
Peak memory 199628 kb
Host smart-e1c20dc9-9b72-4163-8a12-86c58eed5add
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219910436 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset.3219910436
Directory /workspace/5.pwrmgr_reset/latest

Test location /workspace/coverage/default/5.pwrmgr_reset_invalid.2014830191
Short name T509
Test name
Test status
Simulation time 98148645 ps
CPU time 0.96 seconds
Started Jul 24 05:07:34 PM PDT 24
Finished Jul 24 05:07:35 PM PDT 24
Peak memory 210164 kb
Host smart-3cef330c-91ab-4530-97d2-ac50d89f3796
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014830191 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset_invalid.2014830191
Directory /workspace/5.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/5.pwrmgr_sec_cm_rstmgr_intersig_mubi.2558171513
Short name T623
Test name
Test status
Simulation time 55822226 ps
CPU time 0.79 seconds
Started Jul 24 05:07:25 PM PDT 24
Finished Jul 24 05:07:26 PM PDT 24
Peak memory 198240 kb
Host smart-86f378b8-1db6-4b64-861d-e42d7f1a3bbf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558171513 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2558171513
Directory /workspace/5.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/5.pwrmgr_smoke.2825748980
Short name T256
Test name
Test status
Simulation time 63592880 ps
CPU time 0.64 seconds
Started Jul 24 05:07:30 PM PDT 24
Finished Jul 24 05:07:31 PM PDT 24
Peak memory 199024 kb
Host smart-eed3f8ad-b69b-4e62-8287-dc3dda274caa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825748980 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_smoke.2825748980
Directory /workspace/5.pwrmgr_smoke/latest

Test location /workspace/coverage/default/5.pwrmgr_wakeup.3933244039
Short name T142
Test name
Test status
Simulation time 46599855 ps
CPU time 0.75 seconds
Started Jul 24 05:07:21 PM PDT 24
Finished Jul 24 05:07:22 PM PDT 24
Peak memory 199692 kb
Host smart-c46d06b6-4fa1-4bc3-82d7-12bb2ee3fa51
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933244039 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_wakeup.3933244039
Directory /workspace/5.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/6.pwrmgr_aborted_low_power.3172940690
Short name T473
Test name
Test status
Simulation time 35922933 ps
CPU time 0.71 seconds
Started Jul 24 05:07:28 PM PDT 24
Finished Jul 24 05:07:29 PM PDT 24
Peak memory 199040 kb
Host smart-37d84c78-a0e7-47ba-914c-b676e69910f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172940690 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_aborted_low_power.3172940690
Directory /workspace/6.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/6.pwrmgr_disable_rom_integrity_check.4115626281
Short name T191
Test name
Test status
Simulation time 76254489 ps
CPU time 0.68 seconds
Started Jul 24 05:07:16 PM PDT 24
Finished Jul 24 05:07:17 PM PDT 24
Peak memory 199612 kb
Host smart-45eefb62-81a5-4745-947c-0c08ca8b6964
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115626281 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_disa
ble_rom_integrity_check.4115626281
Directory /workspace/6.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/6.pwrmgr_esc_clk_rst_malfunc.3805315626
Short name T595
Test name
Test status
Simulation time 31741776 ps
CPU time 0.6 seconds
Started Jul 24 05:07:36 PM PDT 24
Finished Jul 24 05:07:37 PM PDT 24
Peak memory 198512 kb
Host smart-3684d0b8-da42-45cf-9b0c-13d137171549
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805315626 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_esc_clk_rst_
malfunc.3805315626
Directory /workspace/6.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/6.pwrmgr_escalation_timeout.771656724
Short name T127
Test name
Test status
Simulation time 632869470 ps
CPU time 0.98 seconds
Started Jul 24 05:07:29 PM PDT 24
Finished Jul 24 05:07:31 PM PDT 24
Peak memory 198480 kb
Host smart-ecf433bc-cc70-4dd6-931c-1702dac5eaf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771656724 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_escalation_timeout.771656724
Directory /workspace/6.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/6.pwrmgr_glitch.3778142552
Short name T422
Test name
Test status
Simulation time 55531605 ps
CPU time 0.64 seconds
Started Jul 24 05:07:16 PM PDT 24
Finished Jul 24 05:07:17 PM PDT 24
Peak memory 198688 kb
Host smart-5d8d2c95-4ba7-4847-99a0-13865062d530
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778142552 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_glitch.3778142552
Directory /workspace/6.pwrmgr_glitch/latest

Test location /workspace/coverage/default/6.pwrmgr_global_esc.1828288384
Short name T237
Test name
Test status
Simulation time 30356420 ps
CPU time 0.62 seconds
Started Jul 24 05:07:30 PM PDT 24
Finished Jul 24 05:07:31 PM PDT 24
Peak memory 198516 kb
Host smart-250cc075-f297-4a14-9281-dfee8b6ea134
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828288384 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_global_esc.1828288384
Directory /workspace/6.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/6.pwrmgr_lowpower_invalid.2234147159
Short name T157
Test name
Test status
Simulation time 49485912 ps
CPU time 0.71 seconds
Started Jul 24 05:07:29 PM PDT 24
Finished Jul 24 05:07:30 PM PDT 24
Peak memory 201984 kb
Host smart-d39550a1-6653-4a84-a79b-bc1bafd85752
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234147159 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_lowpower_invali
d.2234147159
Directory /workspace/6.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/6.pwrmgr_reset.3879034771
Short name T593
Test name
Test status
Simulation time 42396158 ps
CPU time 0.6 seconds
Started Jul 24 05:07:35 PM PDT 24
Finished Jul 24 05:07:36 PM PDT 24
Peak memory 198856 kb
Host smart-12c9214d-e872-40a7-a467-30aba2690a4c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879034771 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset.3879034771
Directory /workspace/6.pwrmgr_reset/latest

Test location /workspace/coverage/default/6.pwrmgr_reset_invalid.4047997411
Short name T235
Test name
Test status
Simulation time 94738498 ps
CPU time 1.02 seconds
Started Jul 24 05:07:24 PM PDT 24
Finished Jul 24 05:07:25 PM PDT 24
Peak memory 209960 kb
Host smart-2dd5d422-4fae-4e1f-b4ff-e9fd6f33ac36
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047997411 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset_invalid.4047997411
Directory /workspace/6.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/6.pwrmgr_sec_cm_rstmgr_intersig_mubi.1545167158
Short name T277
Test name
Test status
Simulation time 50912976 ps
CPU time 0.74 seconds
Started Jul 24 05:07:38 PM PDT 24
Finished Jul 24 05:07:39 PM PDT 24
Peak memory 198336 kb
Host smart-dac21f5f-6b2d-4b2f-93e7-788d49e9d63c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545167158 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_rstmgr_intersig_
mubi.1545167158
Directory /workspace/6.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/6.pwrmgr_smoke.3932090831
Short name T296
Test name
Test status
Simulation time 34485644 ps
CPU time 0.66 seconds
Started Jul 24 05:07:31 PM PDT 24
Finished Jul 24 05:07:32 PM PDT 24
Peak memory 199036 kb
Host smart-d2ab38a7-15ba-46bc-be83-0ca8086d9236
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932090831 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_smoke.3932090831
Directory /workspace/6.pwrmgr_smoke/latest

Test location /workspace/coverage/default/7.pwrmgr_aborted_low_power.654057498
Short name T272
Test name
Test status
Simulation time 41521010 ps
CPU time 0.81 seconds
Started Jul 24 05:07:20 PM PDT 24
Finished Jul 24 05:07:21 PM PDT 24
Peak memory 200452 kb
Host smart-828e4d19-ad0d-4b34-89d5-24ee1e678446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654057498 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_aborted_low_power.654057498
Directory /workspace/7.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/7.pwrmgr_disable_rom_integrity_check.1792956740
Short name T286
Test name
Test status
Simulation time 48009856 ps
CPU time 0.8 seconds
Started Jul 24 05:07:28 PM PDT 24
Finished Jul 24 05:07:29 PM PDT 24
Peak memory 199216 kb
Host smart-c8c6e7ba-74dc-4495-9c6a-fcd91cb30eb2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792956740 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_disa
ble_rom_integrity_check.1792956740
Directory /workspace/7.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.970272583
Short name T611
Test name
Test status
Simulation time 28626452 ps
CPU time 0.66 seconds
Started Jul 24 05:07:33 PM PDT 24
Finished Jul 24 05:07:34 PM PDT 24
Peak memory 198456 kb
Host smart-ea3171b0-4f30-4704-b9d5-eb7a62a29c1d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970272583 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_esc_clk_rst_m
alfunc.970272583
Directory /workspace/7.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/7.pwrmgr_escalation_timeout.57562214
Short name T374
Test name
Test status
Simulation time 320016775 ps
CPU time 0.93 seconds
Started Jul 24 05:07:26 PM PDT 24
Finished Jul 24 05:07:28 PM PDT 24
Peak memory 198976 kb
Host smart-5a8922cf-7a65-450d-a0e8-6ba7d271565e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57562214 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_escalation_timeout.57562214
Directory /workspace/7.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/7.pwrmgr_glitch.4136331229
Short name T291
Test name
Test status
Simulation time 43935139 ps
CPU time 0.65 seconds
Started Jul 24 05:07:35 PM PDT 24
Finished Jul 24 05:07:36 PM PDT 24
Peak memory 198592 kb
Host smart-29b40772-85ea-431d-806d-e2e725e4cc61
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136331229 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_glitch.4136331229
Directory /workspace/7.pwrmgr_glitch/latest

Test location /workspace/coverage/default/7.pwrmgr_global_esc.3733949279
Short name T518
Test name
Test status
Simulation time 120036326 ps
CPU time 0.6 seconds
Started Jul 24 05:07:26 PM PDT 24
Finished Jul 24 05:07:27 PM PDT 24
Peak memory 198960 kb
Host smart-99ccb8bb-0998-4966-94c3-eab58d464b46
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733949279 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_global_esc.3733949279
Directory /workspace/7.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/7.pwrmgr_lowpower_invalid.3377577917
Short name T161
Test name
Test status
Simulation time 42951898 ps
CPU time 0.71 seconds
Started Jul 24 05:07:33 PM PDT 24
Finished Jul 24 05:07:34 PM PDT 24
Peak memory 201632 kb
Host smart-59335061-c1db-4f01-b3b6-d1d21c8b5f5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377577917 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_lowpower_invali
d.3377577917
Directory /workspace/7.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/7.pwrmgr_reset.1864751105
Short name T22
Test name
Test status
Simulation time 59615698 ps
CPU time 0.81 seconds
Started Jul 24 05:07:23 PM PDT 24
Finished Jul 24 05:07:24 PM PDT 24
Peak memory 199632 kb
Host smart-73f7d5f0-b235-4a78-ab13-cd9401885945
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864751105 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset.1864751105
Directory /workspace/7.pwrmgr_reset/latest

Test location /workspace/coverage/default/7.pwrmgr_reset_invalid.4189418236
Short name T245
Test name
Test status
Simulation time 384585024 ps
CPU time 0.73 seconds
Started Jul 24 05:07:42 PM PDT 24
Finished Jul 24 05:07:43 PM PDT 24
Peak memory 210088 kb
Host smart-1acc06ce-5ddf-4d29-b159-932733eb73fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189418236 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset_invalid.4189418236
Directory /workspace/7.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.3717104796
Short name T92
Test name
Test status
Simulation time 93401677 ps
CPU time 0.84 seconds
Started Jul 24 05:07:36 PM PDT 24
Finished Jul 24 05:07:38 PM PDT 24
Peak memory 199804 kb
Host smart-27eecc5d-f545-43a5-ae46-fcddf5759707
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717104796 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_rstmgr_intersig_
mubi.3717104796
Directory /workspace/7.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/7.pwrmgr_smoke.2399843099
Short name T232
Test name
Test status
Simulation time 40858331 ps
CPU time 0.63 seconds
Started Jul 24 05:07:41 PM PDT 24
Finished Jul 24 05:07:41 PM PDT 24
Peak memory 199068 kb
Host smart-278037bc-7644-439b-99f5-113a44376d60
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399843099 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_smoke.2399843099
Directory /workspace/7.pwrmgr_smoke/latest

Test location /workspace/coverage/default/8.pwrmgr_aborted_low_power.3399007948
Short name T331
Test name
Test status
Simulation time 41077056 ps
CPU time 0.85 seconds
Started Jul 24 05:07:37 PM PDT 24
Finished Jul 24 05:07:38 PM PDT 24
Peak memory 200756 kb
Host smart-cef5207e-2598-4652-8c5e-91e162daff7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399007948 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_aborted_low_power.3399007948
Directory /workspace/8.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/8.pwrmgr_disable_rom_integrity_check.3124608633
Short name T397
Test name
Test status
Simulation time 61289653 ps
CPU time 0.71 seconds
Started Jul 24 05:07:44 PM PDT 24
Finished Jul 24 05:07:45 PM PDT 24
Peak memory 199656 kb
Host smart-1be56545-8e90-4cf6-a0e5-9f2f1b03aca9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124608633 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_disa
ble_rom_integrity_check.3124608633
Directory /workspace/8.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.1638772845
Short name T545
Test name
Test status
Simulation time 32387308 ps
CPU time 0.6 seconds
Started Jul 24 05:07:49 PM PDT 24
Finished Jul 24 05:07:50 PM PDT 24
Peak memory 198404 kb
Host smart-adf494c0-1d7c-4d7b-b115-d78d19ddddc7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638772845 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_esc_clk_rst_
malfunc.1638772845
Directory /workspace/8.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/8.pwrmgr_escalation_timeout.526120192
Short name T246
Test name
Test status
Simulation time 164133620 ps
CPU time 0.97 seconds
Started Jul 24 05:07:56 PM PDT 24
Finished Jul 24 05:07:57 PM PDT 24
Peak memory 198636 kb
Host smart-c66dab35-88ba-4d71-ad4f-5134a13c398b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526120192 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_escalation_timeout.526120192
Directory /workspace/8.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/8.pwrmgr_glitch.2693051269
Short name T305
Test name
Test status
Simulation time 65418297 ps
CPU time 0.61 seconds
Started Jul 24 05:07:29 PM PDT 24
Finished Jul 24 05:07:30 PM PDT 24
Peak memory 197872 kb
Host smart-5be14d1e-60b6-44c8-b13c-863b204278d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693051269 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_glitch.2693051269
Directory /workspace/8.pwrmgr_glitch/latest

Test location /workspace/coverage/default/8.pwrmgr_global_esc.874328576
Short name T584
Test name
Test status
Simulation time 78618134 ps
CPU time 0.59 seconds
Started Jul 24 05:07:31 PM PDT 24
Finished Jul 24 05:07:31 PM PDT 24
Peak memory 198784 kb
Host smart-6d3b8658-d164-4b05-97fe-7a9ba445de44
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874328576 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_global_esc.874328576
Directory /workspace/8.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/8.pwrmgr_lowpower_invalid.3668545384
Short name T182
Test name
Test status
Simulation time 55602892 ps
CPU time 0.66 seconds
Started Jul 24 05:07:37 PM PDT 24
Finished Jul 24 05:07:38 PM PDT 24
Peak memory 201944 kb
Host smart-483ec38b-46c0-4159-8858-51c4124b6d35
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668545384 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_lowpower_invali
d.3668545384
Directory /workspace/8.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/8.pwrmgr_reset.2965915825
Short name T589
Test name
Test status
Simulation time 199756576 ps
CPU time 0.67 seconds
Started Jul 24 05:07:11 PM PDT 24
Finished Jul 24 05:07:12 PM PDT 24
Peak memory 198960 kb
Host smart-49a34cfa-2a21-4f46-93a3-06b51833f02f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965915825 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset.2965915825
Directory /workspace/8.pwrmgr_reset/latest

Test location /workspace/coverage/default/8.pwrmgr_reset_invalid.2090776985
Short name T503
Test name
Test status
Simulation time 203237841 ps
CPU time 0.78 seconds
Started Jul 24 05:07:27 PM PDT 24
Finished Jul 24 05:07:28 PM PDT 24
Peak memory 210080 kb
Host smart-37255c91-e072-4f84-be5e-93d893e563fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090776985 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset_invalid.2090776985
Directory /workspace/8.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.2541056563
Short name T610
Test name
Test status
Simulation time 67602138 ps
CPU time 0.85 seconds
Started Jul 24 05:07:37 PM PDT 24
Finished Jul 24 05:07:38 PM PDT 24
Peak memory 199720 kb
Host smart-e7bceea0-7715-4f5a-a06b-d5af39afa13e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541056563 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2541056563
Directory /workspace/8.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/8.pwrmgr_smoke.2655102348
Short name T297
Test name
Test status
Simulation time 31849800 ps
CPU time 0.65 seconds
Started Jul 24 05:07:22 PM PDT 24
Finished Jul 24 05:07:23 PM PDT 24
Peak memory 199816 kb
Host smart-afddfa0d-e4f9-47b6-bada-1ef1aa06a597
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655102348 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_smoke.2655102348
Directory /workspace/8.pwrmgr_smoke/latest

Test location /workspace/coverage/default/9.pwrmgr_aborted_low_power.3858220030
Short name T104
Test name
Test status
Simulation time 51371241 ps
CPU time 0.75 seconds
Started Jul 24 05:07:41 PM PDT 24
Finished Jul 24 05:07:42 PM PDT 24
Peak memory 199408 kb
Host smart-ed1c6db2-5757-4cf2-b25d-037975dcef4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858220030 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_aborted_low_power.3858220030
Directory /workspace/9.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/9.pwrmgr_disable_rom_integrity_check.1672392153
Short name T517
Test name
Test status
Simulation time 80462922 ps
CPU time 0.66 seconds
Started Jul 24 05:07:29 PM PDT 24
Finished Jul 24 05:07:30 PM PDT 24
Peak memory 198804 kb
Host smart-c176b7f4-054d-42d5-88bf-9ef69a35ac3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672392153 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_disa
ble_rom_integrity_check.1672392153
Directory /workspace/9.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.3908596080
Short name T257
Test name
Test status
Simulation time 30712779 ps
CPU time 0.62 seconds
Started Jul 24 05:07:29 PM PDT 24
Finished Jul 24 05:07:29 PM PDT 24
Peak memory 198512 kb
Host smart-0ad5810d-cb45-4ee4-8ce2-1efc8e795874
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908596080 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_esc_clk_rst_
malfunc.3908596080
Directory /workspace/9.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/9.pwrmgr_escalation_timeout.577590558
Short name T309
Test name
Test status
Simulation time 3006926902 ps
CPU time 0.93 seconds
Started Jul 24 05:07:30 PM PDT 24
Finished Jul 24 05:07:31 PM PDT 24
Peak memory 198684 kb
Host smart-76a117c9-e3be-4a1a-a369-7df3f246d08d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577590558 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_escalation_timeout.577590558
Directory /workspace/9.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/9.pwrmgr_glitch.331796427
Short name T222
Test name
Test status
Simulation time 48476320 ps
CPU time 0.57 seconds
Started Jul 24 05:07:42 PM PDT 24
Finished Jul 24 05:07:43 PM PDT 24
Peak memory 198548 kb
Host smart-84c9842b-8e06-4c75-a70d-faca96d46402
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331796427 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_glitch.331796427
Directory /workspace/9.pwrmgr_glitch/latest

Test location /workspace/coverage/default/9.pwrmgr_global_esc.336698854
Short name T435
Test name
Test status
Simulation time 116778077 ps
CPU time 0.6 seconds
Started Jul 24 05:07:41 PM PDT 24
Finished Jul 24 05:07:41 PM PDT 24
Peak memory 198564 kb
Host smart-786be553-595d-4cae-b004-fff869152e4c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336698854 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_global_esc.336698854
Directory /workspace/9.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/9.pwrmgr_lowpower_invalid.996873899
Short name T151
Test name
Test status
Simulation time 44626157 ps
CPU time 0.73 seconds
Started Jul 24 05:07:36 PM PDT 24
Finished Jul 24 05:07:37 PM PDT 24
Peak memory 201920 kb
Host smart-5c13c13b-4224-498b-86ca-3a8fca8ca58f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996873899 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_lowpower_invalid
.996873899
Directory /workspace/9.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/9.pwrmgr_reset.2828605473
Short name T335
Test name
Test status
Simulation time 60969999 ps
CPU time 0.66 seconds
Started Jul 24 05:07:36 PM PDT 24
Finished Jul 24 05:07:37 PM PDT 24
Peak memory 199716 kb
Host smart-c1781fd1-ea19-469c-b6bc-f3f771ea4957
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828605473 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset.2828605473
Directory /workspace/9.pwrmgr_reset/latest

Test location /workspace/coverage/default/9.pwrmgr_reset_invalid.2000962190
Short name T528
Test name
Test status
Simulation time 105972623 ps
CPU time 0.94 seconds
Started Jul 24 05:07:42 PM PDT 24
Finished Jul 24 05:07:44 PM PDT 24
Peak memory 209968 kb
Host smart-5a2f37bd-d88e-42a4-aa7a-a4619aa5890c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000962190 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset_invalid.2000962190
Directory /workspace/9.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.503875173
Short name T534
Test name
Test status
Simulation time 54025080 ps
CPU time 0.77 seconds
Started Jul 24 05:07:23 PM PDT 24
Finished Jul 24 05:07:23 PM PDT 24
Peak memory 198620 kb
Host smart-667e8a9e-e3fd-4798-9792-61294f07ec1d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503875173 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.503875173
Directory /workspace/9.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/9.pwrmgr_smoke.3619285712
Short name T95
Test name
Test status
Simulation time 41367805 ps
CPU time 0.63 seconds
Started Jul 24 05:07:25 PM PDT 24
Finished Jul 24 05:07:25 PM PDT 24
Peak memory 199048 kb
Host smart-89eaf276-9f73-4c0a-837f-f8f3c8dacc7c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619285712 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_smoke.3619285712
Directory /workspace/9.pwrmgr_smoke/latest
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