Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	38835	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

28908

1

T2

1

T3

11

T4

14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	34202	1			T1	1		T3	15		T4	1
values[0x0]	16437	1			T2	1		T3	4		T4	37
values[0x1]	17104	1			T3	7		T4	26		T7	33

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	31026	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

36717

1

T2

1

T3

16

T4

19

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	252	1			T15	1		T97	6		T52	1
valid_sources[0x01]	223	1			T43	1		T99	1		T219	39
valid_sources[0x02]	300	1			T70	1		T15	4		T94	1
valid_sources[0x03]	217	1			T15	3		T220	3		T221	6
valid_sources[0x04]	252	1			T25	1		T28	3		T29	1
valid_sources[0x05]	238	1			T43	1		T70	1		T15	2
valid_sources[0x06]	284	1			T44	1		T149	1		T97	3
valid_sources[0x07]	299	1			T15	2		T97	2		T34	2
valid_sources[0x08]	185	1			T43	1		T15	8		T99	4
valid_sources[0x09]	224	1			T70	4		T149	1		T15	3
valid_sources[0x0a]	218	1			T8	4		T43	1		T70	1
valid_sources[0x0b]	167	1			T97	1		T99	1		T62	1
valid_sources[0x0c]	185	1			T15	5		T91	1		T99	2
valid_sources[0x0d]	237	1			T99	4		T219	2		T105	1
valid_sources[0x0e]	285	1			T99	6		T61	9		T62	1
valid_sources[0x0f]	185	1			T49	1		T152	1		T40	1
valid_sources[0x10]	156	1			T43	2		T70	1		T99	2
valid_sources[0x11]	242	1			T43	1		T70	1		T15	4
valid_sources[0x12]	198	1			T29	1		T70	1		T15	1
valid_sources[0x13]	264	1			T25	1		T43	1		T15	2
valid_sources[0x14]	231	1			T45	7		T99	5		T62	2
valid_sources[0x15]	256	1			T8	1		T25	1		T15	4
valid_sources[0x16]	220	1			T8	3		T26	1		T43	1
valid_sources[0x17]	261	1			T43	1		T70	1		T97	1
valid_sources[0x18]	215	1			T44	2		T70	1		T62	1
valid_sources[0x19]	215	1			T43	2		T222	1		T14	15
valid_sources[0x1a]	321	1			T15	1		T97	2		T51	1
valid_sources[0x1b]	409	1			T149	3		T99	1		T51	1
valid_sources[0x1c]	198	1			T43	1		T149	1		T15	2
valid_sources[0x1d]	212	1			T97	1		T99	3		T152	1
valid_sources[0x1e]	192	1			T43	1		T15	2		T41	1
valid_sources[0x1f]	254	1			T25	2		T70	1		T221	3
valid_sources[0x20]	236	1			T70	2		T15	1		T99	3
valid_sources[0x21]	268	1			T70	1		T15	1		T97	1
valid_sources[0x22]	328	1			T70	1		T45	1		T94	1
valid_sources[0x23]	295	1			T43	1		T220	1		T49	1
valid_sources[0x24]	290	1			T97	1		T142	1		T219	10
valid_sources[0x25]	235	1			T97	2		T99	2		T60	1
valid_sources[0x26]	330	1			T8	4		T25	2		T29	1
valid_sources[0x27]	296	1			T15	4		T97	1		T220	1
valid_sources[0x28]	184	1			T15	6		T97	2		T152	1
valid_sources[0x29]	284	1			T43	2		T45	2		T97	2
valid_sources[0x2a]	388	1			T43	1		T29	1		T99	2
valid_sources[0x2b]	171	1			T29	1		T97	1		T91	1
valid_sources[0x2c]	266	1			T8	4		T47	1		T70	1
valid_sources[0x2d]	448	1			T70	2		T223	244		T62	1
valid_sources[0x2e]	338	1			T156	2		T108	1		T109	6
valid_sources[0x2f]	242	1			T8	1		T43	6		T44	2
valid_sources[0x30]	225	1			T29	1		T91	2		T221	7
valid_sources[0x31]	251	1			T43	2		T149	1		T15	2
valid_sources[0x32]	317	1			T8	2		T222	2		T97	4
valid_sources[0x33]	236	1			T44	1		T70	1		T97	1
valid_sources[0x34]	323	1			T25	2		T99	1		T61	18
valid_sources[0x35]	259	1			T43	2		T17	1		T97	2
valid_sources[0x36]	388	1			T46	60		T149	1		T97	4
valid_sources[0x37]	209	1			T99	5		T52	2		T221	6
valid_sources[0x38]	307	1			T91	1		T99	2		T219	5
valid_sources[0x39]	248	1			T8	1		T43	1		T70	1
valid_sources[0x3a]	164	1			T43	1		T44	3		T97	5
valid_sources[0x3b]	207	1			T44	6		T15	2		T97	1
valid_sources[0x3c]	270	1			T11	1		T70	1		T45	3
valid_sources[0x3d]	280	1			T15	1		T97	1		T109	1
valid_sources[0x3e]	231	1			T8	3		T15	2		T219	1
valid_sources[0x3f]	251	1			T43	3		T45	1		T15	8
valid_sources[0x40]	270	1			T6	1		T8	6		T43	1
valid_sources[0x41]	224	1			T44	3		T42	1		T62	1
valid_sources[0x42]	150	1			T149	1		T221	7		T112	3
valid_sources[0x43]	251	1			T8	3		T15	2		T97	1
valid_sources[0x44]	185	1			T28	1		T44	1		T15	1
valid_sources[0x45]	221	1			T28	3		T43	1		T45	2
valid_sources[0x46]	281	1			T8	3		T43	1		T70	1
valid_sources[0x47]	244	1			T8	4		T70	1		T151	1
valid_sources[0x48]	178	1			T15	1		T99	1		T221	1
valid_sources[0x49]	253	1			T70	2		T15	3		T99	4
valid_sources[0x4a]	204	1			T58	7		T99	1		T186	15
valid_sources[0x4b]	216	1			T8	1		T70	1		T97	2
valid_sources[0x4c]	166	1			T8	5		T44	2		T97	1
valid_sources[0x4d]	279	1			T149	1		T99	3		T51	1
valid_sources[0x4e]	204	1			T99	2		T220	2		T34	1
valid_sources[0x4f]	201	1			T43	2		T29	2		T70	1
valid_sources[0x50]	255	1			T43	4		T62	2		T108	1
valid_sources[0x51]	234	1			T44	1		T97	2		T99	5
valid_sources[0x52]	226	1			T97	1		T156	1		T20	1
valid_sources[0x53]	192	1			T15	1		T97	3		T34	2
valid_sources[0x54]	199	1			T43	2		T15	4		T99	1
valid_sources[0x55]	332	1			T29	2		T70	2		T45	9
valid_sources[0x56]	580	1			T45	1		T15	1		T99	1
valid_sources[0x57]	382	1			T12	10		T43	1		T149	1
valid_sources[0x58]	229	1			T8	5		T49	1		T163	1
valid_sources[0x59]	238	1			T149	1		T99	1		T51	2
valid_sources[0x5a]	267	1			T43	4		T222	3		T97	3
valid_sources[0x5b]	346	1			T149	1		T220	1		T49	1
valid_sources[0x5c]	594	1			T8	2		T30	29		T39	3
valid_sources[0x5d]	186	1			T9	1		T97	1		T99	2
valid_sources[0x5e]	248	1			T97	2		T151	2		T61	4
valid_sources[0x5f]	281	1			T12	4		T43	4		T44	1
valid_sources[0x60]	194	1			T29	1		T52	1		T197	2
valid_sources[0x61]	348	1			T70	1		T15	9		T97	1
valid_sources[0x62]	332	1			T43	1		T97	2		T99	6
valid_sources[0x63]	321	1			T25	1		T70	1		T152	1
valid_sources[0x64]	295	1			T29	1		T97	9		T62	1
valid_sources[0x65]	428	1			T43	3		T29	1		T70	1
valid_sources[0x66]	223	1			T70	1		T15	1		T144	1
valid_sources[0x67]	261	1			T29	1		T15	2		T97	3
valid_sources[0x68]	275	1			T8	2		T70	1		T224	1
valid_sources[0x69]	207	1			T94	2		T62	2		T156	1
valid_sources[0x6a]	221	1			T43	3		T220	2		T108	1
valid_sources[0x6b]	228	1			T8	1		T70	1		T99	8
valid_sources[0x6c]	200	1			T25	1		T15	2		T97	1
valid_sources[0x6d]	309	1			T1	1		T4	64		T15	4
valid_sources[0x6e]	204	1			T8	3		T25	1		T97	1
valid_sources[0x6f]	299	1			T43	1		T44	3		T15	2
valid_sources[0x70]	184	1			T28	2		T70	1		T99	8
valid_sources[0x71]	284	1			T44	1		T91	1		T220	2
valid_sources[0x72]	262	1			T28	1		T43	1		T44	1
valid_sources[0x73]	619	1			T44	1		T70	1		T99	4
valid_sources[0x74]	232	1			T70	1		T15	2		T97	3
valid_sources[0x75]	221	1			T97	2		T99	1		T52	1
valid_sources[0x76]	223	1			T70	2		T220	3		T225	1
valid_sources[0x77]	269	1			T8	7		T43	2		T97	3
valid_sources[0x78]	218	1			T43	1		T44	2		T29	1
valid_sources[0x79]	194	1			T29	1		T70	2		T45	1
valid_sources[0x7a]	268	1			T70	2		T15	1		T151	2
valid_sources[0x7b]	239	1			T8	1		T97	2		T91	1
valid_sources[0x7c]	266	1			T99	2		T105	1		T108	1
valid_sources[0x7d]	358	1			T10	52		T28	1		T14	14
valid_sources[0x7e]	272	1			T15	1		T97	1		T99	2
valid_sources[0x7f]	243	1			T44	1		T34	4		T111	1
valid_sources[0x80]	261	1			T70	1		T14	6		T97	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

14118

1

T3

6

T4

1

T5

1

values[0x0]

all_enables

biggest_size

8369

1

T2

1

T3

1

T4

10

values[0x1]

all_enables

biggest_size

6421

1

T3

4

T4

3

T7

7