Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2900300	11785	0	0
intr_enable_rd_A	2900300	2451	0	0
reset_en_rd_A	2900300	1396	0	0
reset_en_regwen_rd_A	2900300	1283	0	0
wake_info_capture_dis_rd_A	2900300	1176	0	0
wakeup_en_rd_A	2900300	2041	0	0
wakeup_en_regwen_rd_A	2900300	1206	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2900300	11785	0	0
T22	8528	10	0	0
T23	12078	8	0	0
T24	13376	13	0	0
T63	2064	317	0	0
T64	3316	22	0	0
T65	3431	18	0	0
T66	12629	836	0	0
T73	4530	259	0	0
T80	1550	18	0	0
T101	8353	6	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2900300	2451	0	0
T3	2067	5	0	0
T4	1912	0	0	0
T5	2317	0	0	0
T6	1547	0	0	0
T7	3746	0	0	0
T8	7566	0	0	0
T9	15304	0	0	0
T10	4719	0	0	0
T11	15156	0	0	0
T12	2560	0	0	0
T53	0	1	0	0
T58	0	8	0	0
T91	0	2	0	0
T96	0	81	0	0
T97	0	90	0	0
T104	0	28	0	0
T109	0	39	0	0
T111	0	78	0	0
T138	0	30	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2900300	1396	0	0
T23	12078	117	0	0
T65	3431	14	0	0
T66	12629	55	0	0
T69	3492	58	0	0
T80	1550	7	0	0
T101	8353	80	0	0
T120	1275	6	0	0
T121	1632	8	0	0
T139	4928	98	0	0
T140	5375	26	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2900300	1283	0	0
T23	12078	88	0	0
T65	3431	8	0	0
T66	12629	32	0	0
T69	3492	61	0	0
T80	1550	3	0	0
T101	8353	35	0	0
T121	1632	2	0	0
T122	1244	3	0	0
T139	4928	103	0	0
T140	5375	28	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2900300	1176	0	0
T23	12078	96	0	0
T65	3431	11	0	0
T66	12629	14	0	0
T69	3492	49	0	0
T80	1550	1	0	0
T101	8353	32	0	0
T120	1275	8	0	0
T121	1632	7	0	0
T139	4928	123	0	0
T140	5375	21	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2900300	2041	0	0
T23	12078	275	0	0
T65	3431	12	0	0
T66	12629	28	0	0
T69	3492	50	0	0
T80	1550	10	0	0
T101	8353	90	0	0
T120	1275	1	0	0
T121	1632	10	0	0
T139	4928	118	0	0
T140	5375	68	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2900300	1206	0	0
T23	12078	56	0	0
T65	3431	9	0	0
T66	12629	21	0	0
T69	3492	46	0	0
T80	1550	14	0	0
T101	8353	32	0	0
T120	1275	4	0	0
T121	1632	1	0	0
T139	4928	104	0	0
T140	5375	43	0	0