Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	6866310	9138	0	0
StatusRise_A	6866310	12549	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866310	9138	0	0
T2	46434	3	0	0
T3	6201	6	0	0
T4	5736	18	0	0
T5	6951	0	0	0
T6	4641	0	0	0
T7	11238	45	0	0
T8	22698	54	0	0
T9	45912	3	0	0
T10	14157	48	0	0
T11	0	9	0	0
T12	7680	3	0	0
T25	0	15	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866310	12549	0	0
T1	4020	6	0	0
T2	46434	6	0	0
T3	6201	9	0	0
T4	5736	21	0	0
T5	6951	9	0	0
T6	4641	15	0	0
T7	11238	48	0	0
T8	22698	57	0	0
T9	45912	6	0	0
T10	14157	51	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	2288770	3077	0	0
StatusRise_A	2288770	4224	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2288770	3077	0	0
T2	15478	1	0	0
T3	2067	2	0	0
T4	1912	6	0	0
T5	2317	0	0	0
T6	1547	0	0	0
T7	3746	15	0	0
T8	7566	18	0	0
T9	15304	1	0	0
T10	4719	16	0	0
T11	0	3	0	0
T12	2560	1	0	0
T25	0	5	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2288770	4224	0	0
T1	1340	2	0	0
T2	15478	2	0	0
T3	2067	3	0	0
T4	1912	7	0	0
T5	2317	3	0	0
T6	1547	5	0	0
T7	3746	16	0	0
T8	7566	19	0	0
T9	15304	2	0	0
T10	4719	17	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	2288770	3077	0	0
StatusRise_A	2288770	4224	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2288770	3077	0	0
T2	15478	1	0	0
T3	2067	2	0	0
T4	1912	6	0	0
T5	2317	0	0	0
T6	1547	0	0	0
T7	3746	15	0	0
T8	7566	18	0	0
T9	15304	1	0	0
T10	4719	16	0	0
T11	0	3	0	0
T12	2560	1	0	0
T25	0	5	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2288770	4224	0	0
T1	1340	2	0	0
T2	15478	2	0	0
T3	2067	3	0	0
T4	1912	7	0	0
T5	2317	3	0	0
T6	1547	5	0	0
T7	3746	16	0	0
T8	7566	19	0	0
T9	15304	2	0	0
T10	4719	17	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	2288770	2984	0	0
StatusRise_A	2288770	4101	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2288770	2984	0	0
T2	15478	1	0	0
T3	2067	2	0	0
T4	1912	6	0	0
T5	2317	0	0	0
T6	1547	0	0	0
T7	3746	15	0	0
T8	7566	18	0	0
T9	15304	1	0	0
T10	4719	16	0	0
T11	0	3	0	0
T12	2560	1	0	0
T25	0	5	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2288770	4101	0	0
T1	1340	2	0	0
T2	15478	2	0	0
T3	2067	3	0	0
T4	1912	7	0	0
T5	2317	3	0	0
T6	1547	5	0	0
T7	3746	16	0	0
T8	7566	19	0	0
T9	15304	2	0	0
T10	4719	17	0	0