Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	2289124	5285	0	0
EscTimeoutStoppedByClReset_A	2288770	91672	0	0
EscTimeoutTriggersReset_A	305288	302	0	0
RomAllowActiveState_A	2288770	3874	0	0
RomAllowCheckGoodState_A	2288770	3924	0	0
RomBlockActiveState_A	2288770	29654	0	0
RomBlockCheckGoodState_A	2288770	19813	0	0
RomIntgChkDisFalse_A	2288770	2101159	0	0
RomIntgChkDisTrue_A	2288770	33748	0	0
RstreqChkEsctimeout_A	2288770	994	0	0
RstreqChkFsmterm_A	2288770	160	0	0
RstreqChkGlbesc_A	2288770	994	0	0
RstreqChkMainpd_A	2288770	51466	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2289124	5285	0	0
T2	15479	229	0	0
T3	2068	0	0	0
T4	1912	0	0	0
T5	2317	0	0	0
T6	1548	0	0	0
T7	3746	0	0	0
T8	7567	0	0	0
T9	15304	75	0	0
T10	4720	0	0	0
T11	0	145	0	0
T12	2561	0	0	0
T41	0	24	0	0
T141	0	4	0	0
T142	0	104	0	0
T143	0	32	0	0
T144	0	8	0	0
T145	0	271	0	0
T146	0	10	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2288770	91672	0	0
T1	1340	10	0	0
T2	15478	17	0	0
T3	2067	12	0	0
T4	1912	86	0	0
T5	2317	58	0	0
T6	1547	55	0	0
T7	3746	493	0	0
T8	7566	339	0	0
T9	15304	13	0	0
T10	4719	644	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305288	302	0	0
T2	190	3	0	0
T3	188	0	0	0
T4	1503	0	0	0
T5	218	0	0	0
T6	531	0	0	0
T7	445	0	0	0
T8	726	0	0	0
T9	362	2	0	0
T10	344	0	0	0
T11	0	3	0	0
T12	201	0	0	0
T41	0	2	0	0
T141	0	3	0	0
T142	0	3	0	0
T143	0	2	0	0
T144	0	3	0	0
T145	0	3	0	0
T147	0	2	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2288770	3874	0	0
T1	1340	2	0	0
T2	15478	2	0	0
T3	2067	3	0	0
T4	1912	7	0	0
T5	2317	3	0	0
T6	1547	5	0	0
T7	3746	16	0	0
T8	7566	12	0	0
T9	15304	2	0	0
T10	4719	17	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2288770	3924	0	0
T1	1340	2	0	0
T2	15478	2	0	0
T3	2067	3	0	0
T4	1912	7	0	0
T5	2317	3	0	0
T6	1547	5	0	0
T7	3746	16	0	0
T8	7566	13	0	0
T9	15304	2	0	0
T10	4719	17	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2288770	29654	0	0
T13	1670	0	0	0
T25	1450	243	0	0
T26	1010	0	0	0
T28	1450	129	0	0
T29	0	520	0	0
T30	2484	0	0	0
T43	2726	0	0	0
T44	4645	0	0	0
T47	943	0	0	0
T48	1495	0	0	0
T58	2530	0	0	0
T148	0	296	0	0
T149	0	1384	0	0
T150	0	1100	0	0
T151	0	27	0	0
T152	0	366	0	0
T153	0	338	0	0
T154	0	1062	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2288770	19813	0	0
T13	1670	0	0	0
T25	1450	50	0	0
T26	1010	0	0	0
T28	1450	5	0	0
T29	0	240	0	0
T30	2484	0	0	0
T38	0	23	0	0
T43	2726	0	0	0
T44	4645	0	0	0
T47	943	0	0	0
T48	1495	0	0	0
T58	2530	0	0	0
T148	0	42	0	0
T149	0	850	0	0
T150	0	844	0	0
T152	0	141	0	0
T153	0	137	0	0
T154	0	912	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2288770	2101159	0	0
T1	1340	1202	0	0
T2	15478	15406	0	0
T3	2067	1978	0	0
T4	1912	1858	0	0
T5	2317	2127	0	0
T6	1547	1189	0	0
T7	3746	3646	0	0
T8	7566	6751	0	0
T9	15304	15221	0	0
T10	4719	4629	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2288770	33748	0	0
T13	1670	0	0	0
T26	1010	0	0	0
T28	1450	86	0	0
T29	0	113	0	0
T30	2484	0	0	0
T43	2726	0	0	0
T44	4645	0	0	0
T47	943	0	0	0
T48	1495	0	0	0
T58	2530	0	0	0
T90	1658	0	0	0
T148	0	639	0	0
T150	0	1947	0	0
T151	0	257	0	0
T152	0	1002	0	0
T153	0	600	0	0
T154	0	2164	0	0
T155	0	105	0	0
T156	0	908	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2288770	994	0	0
T1	1340	1	0	0
T2	15478	1	0	0
T3	2067	0	0	0
T4	1912	0	0	0
T5	2317	0	0	0
T6	1547	4	0	0
T7	3746	6	0	0
T8	7566	8	0	0
T9	15304	1	0	0
T10	4719	5	0	0
T11	0	1	0	0
T25	0	2	0	0
T28	0	2	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2288770	160	0	0
T19	21425	20	0	0
T20	0	40	0	0
T21	0	40	0	0
T32	0	20	0	0
T33	0	40	0	0
T34	3030	0	0	0
T35	2616	0	0	0
T36	5577	0	0	0
T37	908	0	0	0
T38	2043	0	0	0
T39	1142	0	0	0
T40	950	0	0	0
T41	14913	0	0	0
T42	1784	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2288770	994	0	0
T1	1340	1	0	0
T2	15478	1	0	0
T3	2067	0	0	0
T4	1912	0	0	0
T5	2317	0	0	0
T6	1547	4	0	0
T7	3746	6	0	0
T8	7566	8	0	0
T9	15304	1	0	0
T10	4719	5	0	0
T11	0	1	0	0
T25	0	2	0	0
T28	0	2	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2288770	51466	0	0
T5	2317	12	0	0
T6	1547	0	0	0
T7	3746	471	0	0
T8	7566	181	0	0
T9	15304	0	0	0
T10	4719	672	0	0
T11	15156	0	0	0
T12	2560	0	0	0
T25	1450	69	0	0
T26	0	17	0	0
T28	1450	14	0	0
T29	0	456	0	0
T43	0	126	0	0
T44	0	106	0	0