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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.37 98.23 96.15 99.44 96.00 96.18 100.00 95.58


Total test records in report: 739
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T558 /workspace/coverage/default/14.pwrmgr_global_esc.4145310317 Jul 26 06:58:43 PM PDT 24 Jul 26 06:58:44 PM PDT 24 91476225 ps
T559 /workspace/coverage/default/23.pwrmgr_aborted_low_power.1665553173 Jul 26 06:59:17 PM PDT 24 Jul 26 06:59:18 PM PDT 24 22741909 ps
T560 /workspace/coverage/default/4.pwrmgr_smoke.693286150 Jul 26 06:57:47 PM PDT 24 Jul 26 06:57:48 PM PDT 24 29492289 ps
T561 /workspace/coverage/default/4.pwrmgr_global_esc.948266463 Jul 26 06:57:55 PM PDT 24 Jul 26 06:57:56 PM PDT 24 58072702 ps
T562 /workspace/coverage/default/2.pwrmgr_aborted_low_power.250101796 Jul 26 06:57:38 PM PDT 24 Jul 26 06:57:39 PM PDT 24 75086519 ps
T563 /workspace/coverage/default/20.pwrmgr_global_esc.3119675487 Jul 26 06:58:57 PM PDT 24 Jul 26 06:58:58 PM PDT 24 84042440 ps
T564 /workspace/coverage/default/43.pwrmgr_smoke.2463546034 Jul 26 07:00:20 PM PDT 24 Jul 26 07:00:21 PM PDT 24 57942594 ps
T565 /workspace/coverage/default/30.pwrmgr_smoke.2783742182 Jul 26 06:59:45 PM PDT 24 Jul 26 06:59:46 PM PDT 24 116054866 ps
T566 /workspace/coverage/default/21.pwrmgr_escalation_timeout.1526879901 Jul 26 06:59:04 PM PDT 24 Jul 26 06:59:05 PM PDT 24 319990011 ps
T567 /workspace/coverage/default/39.pwrmgr_disable_rom_integrity_check.2127767212 Jul 26 07:00:12 PM PDT 24 Jul 26 07:00:14 PM PDT 24 63099502 ps
T568 /workspace/coverage/default/40.pwrmgr_global_esc.2007752818 Jul 26 07:00:13 PM PDT 24 Jul 26 07:00:14 PM PDT 24 31827774 ps
T188 /workspace/coverage/default/41.pwrmgr_lowpower_invalid.3063815915 Jul 26 07:00:20 PM PDT 24 Jul 26 07:00:21 PM PDT 24 163388236 ps
T569 /workspace/coverage/default/16.pwrmgr_reset_invalid.1808871819 Jul 26 06:58:50 PM PDT 24 Jul 26 06:58:52 PM PDT 24 107693794 ps
T57 /workspace/coverage/default/6.pwrmgr_wakeup_reset.356674069 Jul 26 06:58:04 PM PDT 24 Jul 26 06:58:04 PM PDT 24 59078098 ps
T570 /workspace/coverage/default/8.pwrmgr_escalation_timeout.2854142344 Jul 26 06:58:11 PM PDT 24 Jul 26 06:58:12 PM PDT 24 488501142 ps
T571 /workspace/coverage/default/42.pwrmgr_esc_clk_rst_malfunc.2760546122 Jul 26 07:00:23 PM PDT 24 Jul 26 07:00:24 PM PDT 24 30284377 ps
T572 /workspace/coverage/default/25.pwrmgr_reset.1040202095 Jul 26 06:59:24 PM PDT 24 Jul 26 06:59:25 PM PDT 24 65848587 ps
T573 /workspace/coverage/default/48.pwrmgr_sec_cm_rstmgr_intersig_mubi.262350034 Jul 26 07:00:43 PM PDT 24 Jul 26 07:00:44 PM PDT 24 63949680 ps
T574 /workspace/coverage/default/35.pwrmgr_reset.1385840337 Jul 26 06:59:55 PM PDT 24 Jul 26 06:59:56 PM PDT 24 88753901 ps
T575 /workspace/coverage/default/49.pwrmgr_sec_cm_rstmgr_intersig_mubi.1842454325 Jul 26 07:00:40 PM PDT 24 Jul 26 07:00:41 PM PDT 24 50708974 ps
T576 /workspace/coverage/default/16.pwrmgr_reset.2124468288 Jul 26 06:58:48 PM PDT 24 Jul 26 06:58:49 PM PDT 24 70070404 ps
T577 /workspace/coverage/default/3.pwrmgr_global_esc.42147318 Jul 26 06:57:47 PM PDT 24 Jul 26 06:57:48 PM PDT 24 67151785 ps
T578 /workspace/coverage/default/33.pwrmgr_lowpower_invalid.4293028951 Jul 26 06:59:46 PM PDT 24 Jul 26 06:59:47 PM PDT 24 48308988 ps
T579 /workspace/coverage/default/8.pwrmgr_lowpower_invalid.2645201979 Jul 26 06:58:22 PM PDT 24 Jul 26 06:58:23 PM PDT 24 186147699 ps
T580 /workspace/coverage/default/34.pwrmgr_global_esc.1085878878 Jul 26 06:59:47 PM PDT 24 Jul 26 06:59:48 PM PDT 24 28754944 ps
T581 /workspace/coverage/default/35.pwrmgr_disable_rom_integrity_check.8750271 Jul 26 06:59:55 PM PDT 24 Jul 26 06:59:56 PM PDT 24 59602579 ps
T582 /workspace/coverage/default/48.pwrmgr_esc_clk_rst_malfunc.3495323187 Jul 26 07:00:40 PM PDT 24 Jul 26 07:00:41 PM PDT 24 39804788 ps
T583 /workspace/coverage/default/2.pwrmgr_smoke.4030588557 Jul 26 06:57:39 PM PDT 24 Jul 26 06:57:39 PM PDT 24 29856383 ps
T584 /workspace/coverage/default/19.pwrmgr_esc_clk_rst_malfunc.3326425832 Jul 26 06:58:58 PM PDT 24 Jul 26 06:58:59 PM PDT 24 28536021 ps
T585 /workspace/coverage/default/29.pwrmgr_reset_invalid.1211036196 Jul 26 06:59:42 PM PDT 24 Jul 26 06:59:43 PM PDT 24 403480563 ps
T586 /workspace/coverage/default/47.pwrmgr_global_esc.2200584852 Jul 26 07:00:32 PM PDT 24 Jul 26 07:00:33 PM PDT 24 28991204 ps
T587 /workspace/coverage/default/22.pwrmgr_esc_clk_rst_malfunc.2022611341 Jul 26 06:59:04 PM PDT 24 Jul 26 06:59:05 PM PDT 24 43554041 ps
T588 /workspace/coverage/default/15.pwrmgr_lowpower_invalid.3632961739 Jul 26 06:58:56 PM PDT 24 Jul 26 06:58:57 PM PDT 24 43938220 ps
T589 /workspace/coverage/default/18.pwrmgr_sec_cm_rstmgr_intersig_mubi.277507292 Jul 26 06:58:56 PM PDT 24 Jul 26 06:58:57 PM PDT 24 262062434 ps
T590 /workspace/coverage/default/35.pwrmgr_lowpower_invalid.3309874037 Jul 26 06:59:56 PM PDT 24 Jul 26 06:59:56 PM PDT 24 81815844 ps
T591 /workspace/coverage/default/48.pwrmgr_glitch.863414756 Jul 26 07:00:47 PM PDT 24 Jul 26 07:00:52 PM PDT 24 34053940 ps
T592 /workspace/coverage/default/13.pwrmgr_sec_cm_rstmgr_intersig_mubi.2719347748 Jul 26 06:58:37 PM PDT 24 Jul 26 06:58:39 PM PDT 24 65070045 ps
T593 /workspace/coverage/default/15.pwrmgr_disable_rom_integrity_check.2478165823 Jul 26 06:58:48 PM PDT 24 Jul 26 06:58:49 PM PDT 24 55269150 ps
T594 /workspace/coverage/default/31.pwrmgr_glitch.3518084272 Jul 26 06:59:45 PM PDT 24 Jul 26 06:59:45 PM PDT 24 40515700 ps
T595 /workspace/coverage/default/6.pwrmgr_reset_invalid.3784093251 Jul 26 06:58:06 PM PDT 24 Jul 26 06:58:06 PM PDT 24 154074895 ps
T596 /workspace/coverage/default/41.pwrmgr_global_esc.492664728 Jul 26 07:00:16 PM PDT 24 Jul 26 07:00:17 PM PDT 24 25380880 ps
T597 /workspace/coverage/default/16.pwrmgr_aborted_low_power.1730618163 Jul 26 06:58:56 PM PDT 24 Jul 26 06:58:57 PM PDT 24 20530354 ps
T598 /workspace/coverage/default/38.pwrmgr_smoke.2625672385 Jul 26 07:00:14 PM PDT 24 Jul 26 07:00:15 PM PDT 24 29843483 ps
T599 /workspace/coverage/default/6.pwrmgr_lowpower_invalid.2301023520 Jul 26 06:58:05 PM PDT 24 Jul 26 06:58:06 PM PDT 24 51194616 ps
T600 /workspace/coverage/default/40.pwrmgr_escalation_timeout.3679693377 Jul 26 07:00:14 PM PDT 24 Jul 26 07:00:15 PM PDT 24 611936215 ps
T601 /workspace/coverage/default/7.pwrmgr_reset_invalid.2405155524 Jul 26 06:58:11 PM PDT 24 Jul 26 06:58:12 PM PDT 24 99813659 ps
T602 /workspace/coverage/default/39.pwrmgr_aborted_low_power.2872252025 Jul 26 07:00:15 PM PDT 24 Jul 26 07:00:16 PM PDT 24 46498805 ps
T603 /workspace/coverage/default/22.pwrmgr_lowpower_invalid.721640365 Jul 26 06:59:04 PM PDT 24 Jul 26 06:59:05 PM PDT 24 57127376 ps
T604 /workspace/coverage/default/10.pwrmgr_smoke.100154276 Jul 26 06:58:20 PM PDT 24 Jul 26 06:58:21 PM PDT 24 71610736 ps
T605 /workspace/coverage/default/23.pwrmgr_escalation_timeout.2777363408 Jul 26 06:59:15 PM PDT 24 Jul 26 06:59:17 PM PDT 24 653775937 ps
T606 /workspace/coverage/default/3.pwrmgr_escalation_timeout.3507713794 Jul 26 06:57:48 PM PDT 24 Jul 26 06:57:49 PM PDT 24 578956957 ps
T607 /workspace/coverage/default/31.pwrmgr_global_esc.4145775500 Jul 26 06:59:40 PM PDT 24 Jul 26 06:59:41 PM PDT 24 49965572 ps
T608 /workspace/coverage/default/13.pwrmgr_glitch.2976421510 Jul 26 06:58:36 PM PDT 24 Jul 26 06:58:37 PM PDT 24 29233253 ps
T609 /workspace/coverage/default/5.pwrmgr_escalation_timeout.2162371863 Jul 26 06:58:04 PM PDT 24 Jul 26 06:58:05 PM PDT 24 304215724 ps
T610 /workspace/coverage/default/4.pwrmgr_escalation_timeout.1189063144 Jul 26 06:57:53 PM PDT 24 Jul 26 06:57:54 PM PDT 24 650250125 ps
T611 /workspace/coverage/default/26.pwrmgr_sec_cm_rstmgr_intersig_mubi.1344065549 Jul 26 06:59:25 PM PDT 24 Jul 26 06:59:26 PM PDT 24 53616202 ps
T612 /workspace/coverage/default/19.pwrmgr_glitch.357985898 Jul 26 06:59:03 PM PDT 24 Jul 26 06:59:04 PM PDT 24 55998025 ps
T613 /workspace/coverage/default/9.pwrmgr_aborted_low_power.3686705213 Jul 26 06:58:20 PM PDT 24 Jul 26 06:58:21 PM PDT 24 96165343 ps
T614 /workspace/coverage/default/21.pwrmgr_esc_clk_rst_malfunc.1240647728 Jul 26 06:59:04 PM PDT 24 Jul 26 06:59:05 PM PDT 24 29978474 ps
T615 /workspace/coverage/default/7.pwrmgr_glitch.1916781015 Jul 26 06:58:13 PM PDT 24 Jul 26 06:58:14 PM PDT 24 51415738 ps
T616 /workspace/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.2423651493 Jul 26 06:58:10 PM PDT 24 Jul 26 06:58:11 PM PDT 24 37205523 ps
T617 /workspace/coverage/default/18.pwrmgr_escalation_timeout.3372795587 Jul 26 06:58:59 PM PDT 24 Jul 26 06:59:00 PM PDT 24 163108255 ps
T618 /workspace/coverage/default/18.pwrmgr_smoke.2412854878 Jul 26 06:58:52 PM PDT 24 Jul 26 06:58:53 PM PDT 24 101068209 ps
T619 /workspace/coverage/default/8.pwrmgr_disable_rom_integrity_check.514037188 Jul 26 06:58:17 PM PDT 24 Jul 26 06:58:18 PM PDT 24 191387889 ps
T620 /workspace/coverage/default/33.pwrmgr_glitch.2636185592 Jul 26 06:59:52 PM PDT 24 Jul 26 06:59:53 PM PDT 24 79490421 ps
T621 /workspace/coverage/default/4.pwrmgr_glitch.2056911236 Jul 26 06:57:54 PM PDT 24 Jul 26 06:57:55 PM PDT 24 58221868 ps
T622 /workspace/coverage/default/36.pwrmgr_smoke.2313914769 Jul 26 06:59:56 PM PDT 24 Jul 26 06:59:57 PM PDT 24 41693493 ps
T623 /workspace/coverage/default/0.pwrmgr_global_esc.2276996919 Jul 26 06:57:23 PM PDT 24 Jul 26 06:57:24 PM PDT 24 20621380 ps
T624 /workspace/coverage/default/49.pwrmgr_aborted_low_power.2070591585 Jul 26 07:00:54 PM PDT 24 Jul 26 07:00:55 PM PDT 24 57734517 ps
T625 /workspace/coverage/default/8.pwrmgr_reset_invalid.2062428598 Jul 26 06:58:18 PM PDT 24 Jul 26 06:58:19 PM PDT 24 164236186 ps
T626 /workspace/coverage/default/32.pwrmgr_reset_invalid.2951789816 Jul 26 06:59:46 PM PDT 24 Jul 26 06:59:48 PM PDT 24 163253584 ps
T627 /workspace/coverage/default/44.pwrmgr_escalation_timeout.2771446059 Jul 26 07:00:30 PM PDT 24 Jul 26 07:00:32 PM PDT 24 625319941 ps
T201 /workspace/coverage/default/1.pwrmgr_lowpower_wakeup_race.1736768746 Jul 26 06:57:28 PM PDT 24 Jul 26 06:57:29 PM PDT 24 61058985 ps
T628 /workspace/coverage/default/47.pwrmgr_disable_rom_integrity_check.4233719530 Jul 26 07:00:41 PM PDT 24 Jul 26 07:00:42 PM PDT 24 66631060 ps
T21 /workspace/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.2530735784 Jul 26 06:49:12 PM PDT 24 Jul 26 06:49:13 PM PDT 24 77898460 ps
T75 /workspace/coverage/cover_reg_top/0.pwrmgr_intr_test.764118498 Jul 26 06:48:19 PM PDT 24 Jul 26 06:48:20 PM PDT 24 48009722 ps
T70 /workspace/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.4205582060 Jul 26 06:49:14 PM PDT 24 Jul 26 06:49:16 PM PDT 24 109153233 ps
T22 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.3750426937 Jul 26 06:48:19 PM PDT 24 Jul 26 06:48:20 PM PDT 24 123080629 ps
T71 /workspace/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.457631193 Jul 26 06:48:47 PM PDT 24 Jul 26 06:48:48 PM PDT 24 147791569 ps
T23 /workspace/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.2921561123 Jul 26 06:48:26 PM PDT 24 Jul 26 06:48:28 PM PDT 24 320090927 ps
T64 /workspace/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.3065428290 Jul 26 06:49:12 PM PDT 24 Jul 26 06:49:14 PM PDT 24 208072528 ps
T65 /workspace/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.3420899775 Jul 26 06:49:17 PM PDT 24 Jul 26 06:49:19 PM PDT 24 105362581 ps
T121 /workspace/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.3192175645 Jul 26 06:48:35 PM PDT 24 Jul 26 06:48:37 PM PDT 24 21590504 ps
T63 /workspace/coverage/cover_reg_top/19.pwrmgr_tl_errors.1799111557 Jul 26 06:49:13 PM PDT 24 Jul 26 06:49:15 PM PDT 24 89840127 ps
T106 /workspace/coverage/cover_reg_top/15.pwrmgr_csr_rw.918319609 Jul 26 06:49:14 PM PDT 24 Jul 26 06:49:15 PM PDT 24 18684312 ps
T79 /workspace/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.314251229 Jul 26 06:49:12 PM PDT 24 Jul 26 06:49:13 PM PDT 24 69462796 ps
T66 /workspace/coverage/cover_reg_top/4.pwrmgr_tl_errors.2710868473 Jul 26 06:48:35 PM PDT 24 Jul 26 06:48:37 PM PDT 24 187171284 ps
T76 /workspace/coverage/cover_reg_top/1.pwrmgr_intr_test.3341254362 Jul 26 06:48:29 PM PDT 24 Jul 26 06:48:29 PM PDT 24 18246955 ps
T116 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.3352161273 Jul 26 06:48:35 PM PDT 24 Jul 26 06:48:39 PM PDT 24 1603395345 ps
T77 /workspace/coverage/cover_reg_top/27.pwrmgr_intr_test.2190792534 Jul 26 06:49:12 PM PDT 24 Jul 26 06:49:13 PM PDT 24 35648564 ps
T122 /workspace/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.2613936964 Jul 26 06:48:26 PM PDT 24 Jul 26 06:48:27 PM PDT 24 27246514 ps
T74 /workspace/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.3962936035 Jul 26 06:49:13 PM PDT 24 Jul 26 06:49:15 PM PDT 24 146040754 ps
T629 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.3206004867 Jul 26 06:48:27 PM PDT 24 Jul 26 06:48:28 PM PDT 24 38884421 ps
T158 /workspace/coverage/cover_reg_top/26.pwrmgr_intr_test.1632447387 Jul 26 06:49:12 PM PDT 24 Jul 26 06:49:14 PM PDT 24 36123864 ps
T156 /workspace/coverage/cover_reg_top/40.pwrmgr_intr_test.3466033345 Jul 26 06:49:15 PM PDT 24 Jul 26 06:49:16 PM PDT 24 19205232 ps
T630 /workspace/coverage/cover_reg_top/7.pwrmgr_csr_rw.1164433779 Jul 26 06:48:40 PM PDT 24 Jul 26 06:48:41 PM PDT 24 55761272 ps
T631 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.195150397 Jul 26 06:48:21 PM PDT 24 Jul 26 06:48:22 PM PDT 24 77689770 ps
T67 /workspace/coverage/cover_reg_top/18.pwrmgr_tl_errors.1961349004 Jul 26 06:49:12 PM PDT 24 Jul 26 06:49:15 PM PDT 24 262241974 ps
T157 /workspace/coverage/cover_reg_top/22.pwrmgr_intr_test.2202523637 Jul 26 06:49:11 PM PDT 24 Jul 26 06:49:12 PM PDT 24 25657097 ps
T73 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.3135963804 Jul 26 06:48:36 PM PDT 24 Jul 26 06:48:37 PM PDT 24 50578427 ps
T107 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.2779231741 Jul 26 06:48:28 PM PDT 24 Jul 26 06:48:29 PM PDT 24 67486457 ps
T159 /workspace/coverage/cover_reg_top/49.pwrmgr_intr_test.387824249 Jul 26 06:49:21 PM PDT 24 Jul 26 06:49:22 PM PDT 24 145645188 ps
T632 /workspace/coverage/cover_reg_top/13.pwrmgr_intr_test.2949962437 Jul 26 06:49:14 PM PDT 24 Jul 26 06:49:15 PM PDT 24 20541231 ps
T108 /workspace/coverage/cover_reg_top/16.pwrmgr_csr_rw.3887557769 Jul 26 06:49:18 PM PDT 24 Jul 26 06:49:19 PM PDT 24 162551596 ps
T633 /workspace/coverage/cover_reg_top/2.pwrmgr_intr_test.459882111 Jul 26 06:48:28 PM PDT 24 Jul 26 06:48:29 PM PDT 24 44845221 ps
T72 /workspace/coverage/cover_reg_top/3.pwrmgr_tl_errors.2777189680 Jul 26 06:48:28 PM PDT 24 Jul 26 06:48:29 PM PDT 24 43530582 ps
T634 /workspace/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.1665059483 Jul 26 06:49:15 PM PDT 24 Jul 26 06:49:16 PM PDT 24 279452624 ps
T123 /workspace/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.889578827 Jul 26 06:49:14 PM PDT 24 Jul 26 06:49:15 PM PDT 24 194656632 ps
T124 /workspace/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.2067858098 Jul 26 06:49:09 PM PDT 24 Jul 26 06:49:10 PM PDT 24 41583616 ps
T635 /workspace/coverage/cover_reg_top/44.pwrmgr_intr_test.386996597 Jul 26 06:49:16 PM PDT 24 Jul 26 06:49:17 PM PDT 24 18119265 ps
T80 /workspace/coverage/cover_reg_top/16.pwrmgr_tl_errors.3505815584 Jul 26 06:49:13 PM PDT 24 Jul 26 06:49:15 PM PDT 24 53712747 ps
T125 /workspace/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.2674151360 Jul 26 06:48:45 PM PDT 24 Jul 26 06:48:46 PM PDT 24 128137443 ps
T81 /workspace/coverage/cover_reg_top/2.pwrmgr_tl_errors.3054165710 Jul 26 06:48:31 PM PDT 24 Jul 26 06:48:33 PM PDT 24 132370716 ps
T82 /workspace/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.636900692 Jul 26 06:48:23 PM PDT 24 Jul 26 06:48:25 PM PDT 24 142119352 ps
T126 /workspace/coverage/cover_reg_top/12.pwrmgr_csr_rw.3161169596 Jul 26 06:49:12 PM PDT 24 Jul 26 06:49:13 PM PDT 24 19668517 ps
T636 /workspace/coverage/cover_reg_top/24.pwrmgr_intr_test.2299474359 Jul 26 06:49:14 PM PDT 24 Jul 26 06:49:15 PM PDT 24 65309456 ps
T637 /workspace/coverage/cover_reg_top/38.pwrmgr_intr_test.3665371410 Jul 26 06:49:11 PM PDT 24 Jul 26 06:49:12 PM PDT 24 35506295 ps
T638 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.4059117880 Jul 26 06:48:35 PM PDT 24 Jul 26 06:48:37 PM PDT 24 43599384 ps
T639 /workspace/coverage/cover_reg_top/15.pwrmgr_tl_errors.3192816060 Jul 26 06:49:12 PM PDT 24 Jul 26 06:49:13 PM PDT 24 362520481 ps
T109 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.3140617755 Jul 26 06:48:35 PM PDT 24 Jul 26 06:48:36 PM PDT 24 27186917 ps
T640 /workspace/coverage/cover_reg_top/17.pwrmgr_intr_test.416966495 Jul 26 06:49:14 PM PDT 24 Jul 26 06:49:15 PM PDT 24 41034042 ps
T131 /workspace/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.900215335 Jul 26 06:49:12 PM PDT 24 Jul 26 06:49:13 PM PDT 24 79872309 ps
T641 /workspace/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.2269939794 Jul 26 06:49:17 PM PDT 24 Jul 26 06:49:18 PM PDT 24 21357345 ps
T642 /workspace/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.2873114574 Jul 26 06:49:13 PM PDT 24 Jul 26 06:49:14 PM PDT 24 109885080 ps
T643 /workspace/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.2059747776 Jul 26 06:48:42 PM PDT 24 Jul 26 06:48:43 PM PDT 24 39145029 ps
T644 /workspace/coverage/cover_reg_top/36.pwrmgr_intr_test.3113140611 Jul 26 06:49:16 PM PDT 24 Jul 26 06:49:17 PM PDT 24 17940038 ps
T645 /workspace/coverage/cover_reg_top/35.pwrmgr_intr_test.2857382072 Jul 26 06:49:13 PM PDT 24 Jul 26 06:49:14 PM PDT 24 60380633 ps
T110 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.2838660754 Jul 26 06:48:28 PM PDT 24 Jul 26 06:48:29 PM PDT 24 30256285 ps
T78 /workspace/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.4023811333 Jul 26 06:48:19 PM PDT 24 Jul 26 06:48:21 PM PDT 24 555294050 ps
T132 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.1643763435 Jul 26 06:48:27 PM PDT 24 Jul 26 06:48:30 PM PDT 24 1123468699 ps
T646 /workspace/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.1513145767 Jul 26 06:48:41 PM PDT 24 Jul 26 06:48:42 PM PDT 24 255297385 ps
T647 /workspace/coverage/cover_reg_top/1.pwrmgr_tl_errors.940057357 Jul 26 06:48:21 PM PDT 24 Jul 26 06:48:23 PM PDT 24 83721488 ps
T648 /workspace/coverage/cover_reg_top/37.pwrmgr_intr_test.1612265067 Jul 26 06:49:14 PM PDT 24 Jul 26 06:49:15 PM PDT 24 49527583 ps
T649 /workspace/coverage/cover_reg_top/16.pwrmgr_intr_test.473876517 Jul 26 06:49:13 PM PDT 24 Jul 26 06:49:14 PM PDT 24 59294491 ps
T650 /workspace/coverage/cover_reg_top/12.pwrmgr_intr_test.1635578685 Jul 26 06:49:13 PM PDT 24 Jul 26 06:49:14 PM PDT 24 101574340 ps
T651 /workspace/coverage/cover_reg_top/48.pwrmgr_intr_test.1093451945 Jul 26 06:49:19 PM PDT 24 Jul 26 06:49:20 PM PDT 24 50170570 ps
T652 /workspace/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.1980962376 Jul 26 06:48:45 PM PDT 24 Jul 26 06:48:46 PM PDT 24 72857765 ps
T653 /workspace/coverage/cover_reg_top/0.pwrmgr_tl_errors.3661960162 Jul 26 06:48:20 PM PDT 24 Jul 26 06:48:23 PM PDT 24 251961430 ps
T654 /workspace/coverage/cover_reg_top/19.pwrmgr_intr_test.1543696448 Jul 26 06:49:12 PM PDT 24 Jul 26 06:49:13 PM PDT 24 38470068 ps
T655 /workspace/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.1277542159 Jul 26 06:49:13 PM PDT 24 Jul 26 06:49:14 PM PDT 24 42010745 ps
T111 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.1023950005 Jul 26 06:48:21 PM PDT 24 Jul 26 06:48:22 PM PDT 24 86809211 ps
T656 /workspace/coverage/cover_reg_top/6.pwrmgr_intr_test.610722843 Jul 26 06:48:41 PM PDT 24 Jul 26 06:48:42 PM PDT 24 30911454 ps
T657 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.3398096935 Jul 26 06:48:20 PM PDT 24 Jul 26 06:48:22 PM PDT 24 194837464 ps
T658 /workspace/coverage/cover_reg_top/25.pwrmgr_intr_test.3504122614 Jul 26 06:49:12 PM PDT 24 Jul 26 06:49:13 PM PDT 24 25636912 ps
T659 /workspace/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.1117624274 Jul 26 06:49:12 PM PDT 24 Jul 26 06:49:13 PM PDT 24 117427188 ps
T660 /workspace/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.3852564089 Jul 26 06:48:37 PM PDT 24 Jul 26 06:48:37 PM PDT 24 25013726 ps
T661 /workspace/coverage/cover_reg_top/21.pwrmgr_intr_test.176896924 Jul 26 06:49:12 PM PDT 24 Jul 26 06:49:13 PM PDT 24 17873896 ps
T662 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.1471892614 Jul 26 06:48:36 PM PDT 24 Jul 26 06:48:37 PM PDT 24 174527875 ps
T663 /workspace/coverage/cover_reg_top/31.pwrmgr_intr_test.4063986278 Jul 26 06:49:12 PM PDT 24 Jul 26 06:49:13 PM PDT 24 65382309 ps
T112 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_rw.2299872520 Jul 26 06:48:27 PM PDT 24 Jul 26 06:48:28 PM PDT 24 80002973 ps
T664 /workspace/coverage/cover_reg_top/10.pwrmgr_intr_test.11982058 Jul 26 06:49:09 PM PDT 24 Jul 26 06:49:09 PM PDT 24 17415771 ps
T665 /workspace/coverage/cover_reg_top/5.pwrmgr_intr_test.3730989764 Jul 26 06:48:43 PM PDT 24 Jul 26 06:48:44 PM PDT 24 21337821 ps
T666 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.109144187 Jul 26 06:48:29 PM PDT 24 Jul 26 06:48:30 PM PDT 24 20251802 ps
T146 /workspace/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.1989344104 Jul 26 06:48:42 PM PDT 24 Jul 26 06:48:43 PM PDT 24 321304944 ps
T667 /workspace/coverage/cover_reg_top/30.pwrmgr_intr_test.516784197 Jul 26 06:49:14 PM PDT 24 Jul 26 06:49:14 PM PDT 24 62738068 ps
T668 /workspace/coverage/cover_reg_top/42.pwrmgr_intr_test.700823355 Jul 26 06:49:15 PM PDT 24 Jul 26 06:49:16 PM PDT 24 19639004 ps
T669 /workspace/coverage/cover_reg_top/20.pwrmgr_intr_test.2834826832 Jul 26 06:49:15 PM PDT 24 Jul 26 06:49:16 PM PDT 24 17386038 ps
T670 /workspace/coverage/cover_reg_top/9.pwrmgr_intr_test.3089880276 Jul 26 06:49:09 PM PDT 24 Jul 26 06:49:10 PM PDT 24 47860813 ps
T133 /workspace/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.1991171303 Jul 26 06:49:11 PM PDT 24 Jul 26 06:49:11 PM PDT 24 70228670 ps
T671 /workspace/coverage/cover_reg_top/46.pwrmgr_intr_test.2635353714 Jul 26 06:49:15 PM PDT 24 Jul 26 06:49:16 PM PDT 24 29247809 ps
T672 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.1145345496 Jul 26 06:48:35 PM PDT 24 Jul 26 06:48:37 PM PDT 24 400971938 ps
T673 /workspace/coverage/cover_reg_top/29.pwrmgr_intr_test.4136443874 Jul 26 06:49:14 PM PDT 24 Jul 26 06:49:15 PM PDT 24 41127684 ps
T113 /workspace/coverage/cover_reg_top/9.pwrmgr_csr_rw.2474077610 Jul 26 06:49:09 PM PDT 24 Jul 26 06:49:09 PM PDT 24 22108492 ps
T83 /workspace/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.1530309676 Jul 26 06:49:16 PM PDT 24 Jul 26 06:49:18 PM PDT 24 281881874 ps
T674 /workspace/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.3942472053 Jul 26 06:49:10 PM PDT 24 Jul 26 06:49:11 PM PDT 24 137036564 ps
T84 /workspace/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.1293463905 Jul 26 06:49:10 PM PDT 24 Jul 26 06:49:12 PM PDT 24 363832817 ps
T114 /workspace/coverage/cover_reg_top/18.pwrmgr_csr_rw.1847472889 Jul 26 06:49:11 PM PDT 24 Jul 26 06:49:11 PM PDT 24 20777193 ps
T675 /workspace/coverage/cover_reg_top/17.pwrmgr_tl_errors.556174862 Jul 26 06:49:14 PM PDT 24 Jul 26 06:49:17 PM PDT 24 416590903 ps
T676 /workspace/coverage/cover_reg_top/18.pwrmgr_intr_test.4070780808 Jul 26 06:49:13 PM PDT 24 Jul 26 06:49:14 PM PDT 24 30159610 ps
T115 /workspace/coverage/cover_reg_top/19.pwrmgr_csr_rw.1869010593 Jul 26 06:49:11 PM PDT 24 Jul 26 06:49:12 PM PDT 24 32386355 ps
T677 /workspace/coverage/cover_reg_top/33.pwrmgr_intr_test.4119112777 Jul 26 06:49:12 PM PDT 24 Jul 26 06:49:14 PM PDT 24 39477642 ps
T678 /workspace/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.1656333086 Jul 26 06:49:15 PM PDT 24 Jul 26 06:49:16 PM PDT 24 63960538 ps
T117 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_rw.2461177305 Jul 26 06:48:26 PM PDT 24 Jul 26 06:48:27 PM PDT 24 72401083 ps
T118 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_rw.3492233474 Jul 26 06:48:22 PM PDT 24 Jul 26 06:48:23 PM PDT 24 29525348 ps
T679 /workspace/coverage/cover_reg_top/3.pwrmgr_intr_test.2508656059 Jul 26 06:48:27 PM PDT 24 Jul 26 06:48:27 PM PDT 24 18151078 ps
T680 /workspace/coverage/cover_reg_top/41.pwrmgr_intr_test.28488831 Jul 26 06:49:15 PM PDT 24 Jul 26 06:49:16 PM PDT 24 19625191 ps
T681 /workspace/coverage/cover_reg_top/7.pwrmgr_tl_errors.92357220 Jul 26 06:48:41 PM PDT 24 Jul 26 06:48:42 PM PDT 24 26643336 ps
T682 /workspace/coverage/cover_reg_top/13.pwrmgr_tl_errors.2265396905 Jul 26 06:49:12 PM PDT 24 Jul 26 06:49:14 PM PDT 24 62369803 ps
T683 /workspace/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.3490594278 Jul 26 06:49:08 PM PDT 24 Jul 26 06:49:10 PM PDT 24 55438923 ps
T119 /workspace/coverage/cover_reg_top/5.pwrmgr_csr_rw.1125214897 Jul 26 06:48:40 PM PDT 24 Jul 26 06:48:41 PM PDT 24 39533612 ps
T684 /workspace/coverage/cover_reg_top/47.pwrmgr_intr_test.1816642109 Jul 26 06:49:14 PM PDT 24 Jul 26 06:49:14 PM PDT 24 21971057 ps
T85 /workspace/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.3711310758 Jul 26 06:49:13 PM PDT 24 Jul 26 06:49:15 PM PDT 24 253262062 ps
T685 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.3204191742 Jul 26 06:48:34 PM PDT 24 Jul 26 06:48:35 PM PDT 24 53155666 ps
T686 /workspace/coverage/cover_reg_top/7.pwrmgr_intr_test.260043638 Jul 26 06:48:43 PM PDT 24 Jul 26 06:48:44 PM PDT 24 22355704 ps
T687 /workspace/coverage/cover_reg_top/8.pwrmgr_csr_rw.1409581294 Jul 26 06:49:09 PM PDT 24 Jul 26 06:49:10 PM PDT 24 18522829 ps
T688 /workspace/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.3996181611 Jul 26 06:48:28 PM PDT 24 Jul 26 06:48:29 PM PDT 24 144994530 ps
T689 /workspace/coverage/cover_reg_top/14.pwrmgr_intr_test.2276830998 Jul 26 06:49:15 PM PDT 24 Jul 26 06:49:16 PM PDT 24 35352737 ps
T690 /workspace/coverage/cover_reg_top/13.pwrmgr_csr_rw.725547790 Jul 26 06:49:12 PM PDT 24 Jul 26 06:49:14 PM PDT 24 25622713 ps
T691 /workspace/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.1134825629 Jul 26 06:49:11 PM PDT 24 Jul 26 06:49:13 PM PDT 24 588706621 ps
T692 /workspace/coverage/cover_reg_top/10.pwrmgr_tl_errors.1978691120 Jul 26 06:49:10 PM PDT 24 Jul 26 06:49:13 PM PDT 24 91977116 ps
T693 /workspace/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.793724187 Jul 26 06:49:10 PM PDT 24 Jul 26 06:49:11 PM PDT 24 46947000 ps
T694 /workspace/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.2811738026 Jul 26 06:49:13 PM PDT 24 Jul 26 06:49:15 PM PDT 24 42497006 ps
T695 /workspace/coverage/cover_reg_top/23.pwrmgr_intr_test.3677221649 Jul 26 06:49:12 PM PDT 24 Jul 26 06:49:13 PM PDT 24 26188869 ps
T696 /workspace/coverage/cover_reg_top/9.pwrmgr_tl_errors.31255236 Jul 26 06:49:08 PM PDT 24 Jul 26 06:49:11 PM PDT 24 905916317 ps
T697 /workspace/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.4021357413 Jul 26 06:49:14 PM PDT 24 Jul 26 06:49:15 PM PDT 24 56148573 ps
T698 /workspace/coverage/cover_reg_top/4.pwrmgr_intr_test.2191992539 Jul 26 06:48:32 PM PDT 24 Jul 26 06:48:33 PM PDT 24 17449280 ps
T699 /workspace/coverage/cover_reg_top/17.pwrmgr_csr_rw.3373004599 Jul 26 06:49:17 PM PDT 24 Jul 26 06:49:18 PM PDT 24 17769480 ps
T700 /workspace/coverage/cover_reg_top/6.pwrmgr_tl_errors.345091939 Jul 26 06:48:43 PM PDT 24 Jul 26 06:48:44 PM PDT 24 44157186 ps
T701 /workspace/coverage/cover_reg_top/28.pwrmgr_intr_test.878239962 Jul 26 06:49:12 PM PDT 24 Jul 26 06:49:13 PM PDT 24 19597130 ps
T702 /workspace/coverage/cover_reg_top/5.pwrmgr_tl_errors.1652190954 Jul 26 06:48:35 PM PDT 24 Jul 26 06:48:37 PM PDT 24 36666205 ps
T703 /workspace/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.1370765172 Jul 26 06:49:13 PM PDT 24 Jul 26 06:49:14 PM PDT 24 235618804 ps
T704 /workspace/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.3446457192 Jul 26 06:49:10 PM PDT 24 Jul 26 06:49:11 PM PDT 24 106079685 ps
T705 /workspace/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.4026020603 Jul 26 06:49:10 PM PDT 24 Jul 26 06:49:11 PM PDT 24 110041595 ps
T706 /workspace/coverage/cover_reg_top/11.pwrmgr_tl_errors.1247197422 Jul 26 06:49:12 PM PDT 24 Jul 26 06:49:15 PM PDT 24 849536268 ps
T707 /workspace/coverage/cover_reg_top/12.pwrmgr_tl_errors.3432626445 Jul 26 06:49:11 PM PDT 24 Jul 26 06:49:13 PM PDT 24 312296392 ps
T708 /workspace/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.1050111881 Jul 26 06:48:30 PM PDT 24 Jul 26 06:48:31 PM PDT 24 28276563 ps
T709 /workspace/coverage/cover_reg_top/6.pwrmgr_csr_rw.2929734427 Jul 26 06:48:43 PM PDT 24 Jul 26 06:48:44 PM PDT 24 45922942 ps
T710 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.2919869393 Jul 26 06:48:27 PM PDT 24 Jul 26 06:48:28 PM PDT 24 52223644 ps
T711 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.2955690602 Jul 26 06:48:28 PM PDT 24 Jul 26 06:48:30 PM PDT 24 565151279 ps
T712 /workspace/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.459195185 Jul 26 06:48:42 PM PDT 24 Jul 26 06:48:43 PM PDT 24 329094637 ps
T713 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_rw.2252698505 Jul 26 06:48:34 PM PDT 24 Jul 26 06:48:35 PM PDT 24 150635224 ps
T714 /workspace/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.2729884506 Jul 26 06:49:09 PM PDT 24 Jul 26 06:49:10 PM PDT 24 36174395 ps
T715 /workspace/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.3025928397 Jul 26 06:48:36 PM PDT 24 Jul 26 06:48:37 PM PDT 24 94589383 ps
T716 /workspace/coverage/cover_reg_top/15.pwrmgr_intr_test.2939710001 Jul 26 06:49:15 PM PDT 24 Jul 26 06:49:16 PM PDT 24 53286599 ps
T717 /workspace/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.438341007 Jul 26 06:49:12 PM PDT 24 Jul 26 06:49:14 PM PDT 24 203972018 ps
T718 /workspace/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.24034259 Jul 26 06:49:10 PM PDT 24 Jul 26 06:49:11 PM PDT 24 95249716 ps
T719 /workspace/coverage/cover_reg_top/34.pwrmgr_intr_test.3005571172 Jul 26 06:49:13 PM PDT 24 Jul 26 06:49:14 PM PDT 24 23484403 ps
T720 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.943130497 Jul 26 06:48:27 PM PDT 24 Jul 26 06:48:28 PM PDT 24 28113499 ps
T721 /workspace/coverage/cover_reg_top/45.pwrmgr_intr_test.3894489986 Jul 26 06:49:15 PM PDT 24 Jul 26 06:49:16 PM PDT 24 66746409 ps
T722 /workspace/coverage/cover_reg_top/14.pwrmgr_csr_rw.1035506545 Jul 26 06:49:13 PM PDT 24 Jul 26 06:49:14 PM PDT 24 48068428 ps
T723 /workspace/coverage/cover_reg_top/32.pwrmgr_intr_test.1492153357 Jul 26 06:49:14 PM PDT 24 Jul 26 06:49:15 PM PDT 24 68441510 ps
T724 /workspace/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.261866762 Jul 26 06:48:19 PM PDT 24 Jul 26 06:48:20 PM PDT 24 22315329 ps
T725 /workspace/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.3604254426 Jul 26 06:49:12 PM PDT 24 Jul 26 06:49:14 PM PDT 24 129337659 ps
T726 /workspace/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.520603339 Jul 26 06:49:14 PM PDT 24 Jul 26 06:49:15 PM PDT 24 44243666 ps
T727 /workspace/coverage/cover_reg_top/8.pwrmgr_tl_errors.2847335241 Jul 26 06:48:43 PM PDT 24 Jul 26 06:48:45 PM PDT 24 122286386 ps
T728 /workspace/coverage/cover_reg_top/14.pwrmgr_tl_errors.3833238181 Jul 26 06:49:13 PM PDT 24 Jul 26 06:49:15 PM PDT 24 37726736 ps
T729 /workspace/coverage/cover_reg_top/8.pwrmgr_intr_test.2678237774 Jul 26 06:49:10 PM PDT 24 Jul 26 06:49:10 PM PDT 24 19172009 ps
T730 /workspace/coverage/cover_reg_top/11.pwrmgr_csr_rw.1136230277 Jul 26 06:49:11 PM PDT 24 Jul 26 06:49:11 PM PDT 24 17439932 ps
T731 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.2736845255 Jul 26 06:48:28 PM PDT 24 Jul 26 06:48:29 PM PDT 24 64570709 ps
T732 /workspace/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.689517484 Jul 26 06:49:12 PM PDT 24 Jul 26 06:49:13 PM PDT 24 78774273 ps
T733 /workspace/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.1916515946 Jul 26 06:48:42 PM PDT 24 Jul 26 06:48:43 PM PDT 24 73442029 ps
T734 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_rw.2706233916 Jul 26 06:48:28 PM PDT 24 Jul 26 06:48:28 PM PDT 24 52133954 ps
T735 /workspace/coverage/cover_reg_top/11.pwrmgr_intr_test.1312197845 Jul 26 06:49:13 PM PDT 24 Jul 26 06:49:14 PM PDT 24 28691878 ps
T147 /workspace/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.1707361233 Jul 26 06:48:36 PM PDT 24 Jul 26 06:48:38 PM PDT 24 418143666 ps
T736 /workspace/coverage/cover_reg_top/39.pwrmgr_intr_test.3832078698 Jul 26 06:49:15 PM PDT 24 Jul 26 06:49:16 PM PDT 24 90825141 ps
T120 /workspace/coverage/cover_reg_top/10.pwrmgr_csr_rw.1357796993 Jul 26 06:49:11 PM PDT 24 Jul 26 06:49:12 PM PDT 24 30116840 ps
T737 /workspace/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.1275878198 Jul 26 06:49:12 PM PDT 24 Jul 26 06:49:14 PM PDT 24 105814091 ps
T738 /workspace/coverage/cover_reg_top/43.pwrmgr_intr_test.703642620 Jul 26 06:49:13 PM PDT 24 Jul 26 06:49:14 PM PDT 24 22518877 ps
T739 /workspace/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.843788368 Jul 26 06:49:16 PM PDT 24 Jul 26 06:49:17 PM PDT 24 52161419 ps

Test location /workspace/coverage/default/24.pwrmgr_smoke.2175953711
Short name T8
Test name
Test status
Simulation time 32597556 ps
CPU time 0.66 seconds
Started Jul 26 06:59:14 PM PDT 24
Finished Jul 26 06:59:15 PM PDT 24
Peak memory 198532 kb
Host smart-b26abe10-38a9-462f-aa48-d3a1abb0d857
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175953711 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_smoke.2175953711
Directory /workspace/24.pwrmgr_smoke/latest

Test location /workspace/coverage/default/42.pwrmgr_aborted_low_power.1206370145
Short name T14
Test name
Test status
Simulation time 35456343 ps
CPU time 0.81 seconds
Started Jul 26 07:00:20 PM PDT 24
Finished Jul 26 07:00:21 PM PDT 24
Peak memory 199224 kb
Host smart-15b1d2d3-940d-4376-ad57-a38226864daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206370145 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_aborted_low_power.1206370145
Directory /workspace/42.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/46.pwrmgr_reset_invalid.2697980574
Short name T43
Test name
Test status
Simulation time 111164239 ps
CPU time 1.06 seconds
Started Jul 26 07:00:31 PM PDT 24
Finished Jul 26 07:00:32 PM PDT 24
Peak memory 209580 kb
Host smart-5e688b2f-38f7-4107-b668-f0588c8107a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697980574 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset_invalid.2697980574
Directory /workspace/46.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/24.pwrmgr_disable_rom_integrity_check.2763141440
Short name T10
Test name
Test status
Simulation time 66220330 ps
CPU time 0.68 seconds
Started Jul 26 06:59:16 PM PDT 24
Finished Jul 26 06:59:17 PM PDT 24
Peak memory 198320 kb
Host smart-184460a1-3445-467d-a984-ca133775226f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763141440 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_dis
able_rom_integrity_check.2763141440
Directory /workspace/24.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.3065428290
Short name T64
Test name
Test status
Simulation time 208072528 ps
CPU time 1.93 seconds
Started Jul 26 06:49:12 PM PDT 24
Finished Jul 26 06:49:14 PM PDT 24
Peak memory 201156 kb
Host smart-a719dd81-cd81-4f9d-a559-26046206a250
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065428290 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_intg_er
r.3065428290
Directory /workspace/11.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm.3594448380
Short name T18
Test name
Test status
Simulation time 306569968 ps
CPU time 1.44 seconds
Started Jul 26 06:57:54 PM PDT 24
Finished Jul 26 06:57:55 PM PDT 24
Peak memory 217008 kb
Host smart-23661000-21a1-4b7e-9bb3-e82532a6e714
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594448380 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm.3594448380
Directory /workspace/4.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/30.pwrmgr_lowpower_invalid.2224502130
Short name T88
Test name
Test status
Simulation time 56991621 ps
CPU time 0.67 seconds
Started Jul 26 06:59:43 PM PDT 24
Finished Jul 26 06:59:44 PM PDT 24
Peak memory 201360 kb
Host smart-0f597218-43b2-43fb-a9d4-201727da59ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224502130 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_lowpower_inval
id.2224502130
Directory /workspace/30.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/42.pwrmgr_stress_all.3450509989
Short name T36
Test name
Test status
Simulation time 618722104 ps
CPU time 1.51 seconds
Started Jul 26 07:00:21 PM PDT 24
Finished Jul 26 07:00:22 PM PDT 24
Peak memory 201160 kb
Host smart-0ba76615-934c-488b-896e-a9f9639889b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450509989 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_stress_all.3450509989
Directory /workspace/42.pwrmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_tl_errors.1799111557
Short name T63
Test name
Test status
Simulation time 89840127 ps
CPU time 2.14 seconds
Started Jul 26 06:49:13 PM PDT 24
Finished Jul 26 06:49:15 PM PDT 24
Peak memory 197892 kb
Host smart-52e05e7b-b6bc-43c8-b865-3cfbfd800e81
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799111557 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_errors.1799111557
Directory /workspace/19.pwrmgr_tl_errors/latest

Test location /workspace/coverage/default/35.pwrmgr_sec_cm_ctrl_config_regwen.2008905623
Short name T143
Test name
Test status
Simulation time 65827444 ps
CPU time 0.84 seconds
Started Jul 26 06:59:51 PM PDT 24
Finished Jul 26 06:59:52 PM PDT 24
Peak memory 200004 kb
Host smart-bfb0c8f9-d2cc-47d8-a08c-739427661201
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008905623 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_
cm_ctrl_config_regwen.2008905623
Directory /workspace/35.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/1.pwrmgr_escalation_timeout.2754540015
Short name T12
Test name
Test status
Simulation time 554498007 ps
CPU time 0.96 seconds
Started Jul 26 06:57:37 PM PDT 24
Finished Jul 26 06:57:38 PM PDT 24
Peak memory 198196 kb
Host smart-78083584-4190-49a4-b90e-ff0171326a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754540015 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_escalation_timeout.2754540015
Directory /workspace/1.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/41.pwrmgr_wakeup.264224645
Short name T53
Test name
Test status
Simulation time 46443792 ps
CPU time 0.82 seconds
Started Jul 26 07:00:16 PM PDT 24
Finished Jul 26 07:00:17 PM PDT 24
Peak memory 199160 kb
Host smart-78a677ac-5419-45ae-9c36-6be1e978b1cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264224645 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_wakeup.264224645
Directory /workspace/41.pwrmgr_wakeup/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_intr_test.459882111
Short name T633
Test name
Test status
Simulation time 44845221 ps
CPU time 0.62 seconds
Started Jul 26 06:48:28 PM PDT 24
Finished Jul 26 06:48:29 PM PDT 24
Peak memory 195496 kb
Host smart-71bfc0fc-c2aa-40ff-8af9-529eb92a4cdf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459882111 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_intr_test.459882111
Directory /workspace/2.pwrmgr_intr_test/latest

Test location /workspace/coverage/default/5.pwrmgr_aborted_low_power.3026452907
Short name T94
Test name
Test status
Simulation time 232060890 ps
CPU time 0.8 seconds
Started Jul 26 06:57:55 PM PDT 24
Finished Jul 26 06:57:56 PM PDT 24
Peak memory 200068 kb
Host smart-67e119e7-3e2c-4cd7-8439-6d8918b1bacc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026452907 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_aborted_low_power.3026452907
Directory /workspace/5.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_csr_rw.918319609
Short name T106
Test name
Test status
Simulation time 18684312 ps
CPU time 0.65 seconds
Started Jul 26 06:49:14 PM PDT 24
Finished Jul 26 06:49:15 PM PDT 24
Peak memory 196904 kb
Host smart-efcf546f-cc2f-4d5f-a835-9d1c56ef4718
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918319609 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_csr_rw.918319609
Directory /workspace/15.pwrmgr_csr_rw/latest

Test location /workspace/coverage/default/17.pwrmgr_wakeup_reset.1429840233
Short name T56
Test name
Test status
Simulation time 76043217 ps
CPU time 0.66 seconds
Started Jul 26 06:58:48 PM PDT 24
Finished Jul 26 06:58:48 PM PDT 24
Peak memory 199252 kb
Host smart-97c1a4fb-086d-48f3-a7a2-abbb63784315
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429840233 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_wakeup_reset.1429840233
Directory /workspace/17.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/1.pwrmgr_disable_rom_integrity_check.4041348405
Short name T164
Test name
Test status
Simulation time 48012864 ps
CPU time 0.74 seconds
Started Jul 26 06:57:38 PM PDT 24
Finished Jul 26 06:57:39 PM PDT 24
Peak memory 198500 kb
Host smart-6fab4f58-bc55-4562-b905-fa015baac500
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041348405 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_disa
ble_rom_integrity_check.4041348405
Directory /workspace/1.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/1.pwrmgr_wakeup.3736629418
Short name T59
Test name
Test status
Simulation time 55112310 ps
CPU time 0.67 seconds
Started Jul 26 06:57:28 PM PDT 24
Finished Jul 26 06:57:29 PM PDT 24
Peak memory 199184 kb
Host smart-67adcc28-1010-496f-b76d-580d57ab7c1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736629418 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_wakeup.3736629418
Directory /workspace/1.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/41.pwrmgr_sec_cm_rstmgr_intersig_mubi.229926222
Short name T5
Test name
Test status
Simulation time 66963474 ps
CPU time 0.85 seconds
Started Jul 26 07:00:12 PM PDT 24
Finished Jul 26 07:00:14 PM PDT 24
Peak memory 198900 kb
Host smart-c7bf1684-fca9-4b30-9440-e1c309856506
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229926222 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_rstmgr_intersig_
mubi.229926222
Directory /workspace/41.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/29.pwrmgr_lowpower_wakeup_race.2439300761
Short name T25
Test name
Test status
Simulation time 36711793 ps
CPU time 0.68 seconds
Started Jul 26 06:59:33 PM PDT 24
Finished Jul 26 06:59:34 PM PDT 24
Peak memory 198324 kb
Host smart-55544323-3faf-43fc-a6e3-95dfd7c7d119
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439300761 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_lowpower_w
akeup_race.2439300761
Directory /workspace/29.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/1.pwrmgr_lowpower_invalid.698006480
Short name T168
Test name
Test status
Simulation time 66413591 ps
CPU time 0.68 seconds
Started Jul 26 06:57:38 PM PDT 24
Finished Jul 26 06:57:38 PM PDT 24
Peak memory 201692 kb
Host smart-c93ce3f8-f53f-4781-8800-022b7006f99c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698006480 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_lowpower_invalid
.698006480
Directory /workspace/1.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/12.pwrmgr_sec_cm_ctrl_config_regwen.1868175874
Short name T68
Test name
Test status
Simulation time 39139911 ps
CPU time 0.72 seconds
Started Jul 26 06:58:31 PM PDT 24
Finished Jul 26 06:58:32 PM PDT 24
Peak memory 199456 kb
Host smart-a57e576f-a4b9-4820-9bef-5de847e41bc3
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868175874 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_
cm_ctrl_config_regwen.1868175874
Directory /workspace/12.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/13.pwrmgr_disable_rom_integrity_check.3916747808
Short name T152
Test name
Test status
Simulation time 48465406 ps
CPU time 0.74 seconds
Started Jul 26 06:58:37 PM PDT 24
Finished Jul 26 06:58:38 PM PDT 24
Peak memory 198468 kb
Host smart-450f97fa-fe05-415c-8685-ad104b39a9f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916747808 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_dis
able_rom_integrity_check.3916747808
Directory /workspace/13.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/14.pwrmgr_sec_cm_ctrl_config_regwen.2186057426
Short name T55
Test name
Test status
Simulation time 74627797 ps
CPU time 0.66 seconds
Started Jul 26 06:58:41 PM PDT 24
Finished Jul 26 06:58:42 PM PDT 24
Peak memory 198568 kb
Host smart-b7a9911f-f835-44eb-bfd9-204dbb788f3d
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186057426 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_
cm_ctrl_config_regwen.2186057426
Directory /workspace/14.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/48.pwrmgr_disable_rom_integrity_check.3712602925
Short name T27
Test name
Test status
Simulation time 85143135 ps
CPU time 0.65 seconds
Started Jul 26 07:00:46 PM PDT 24
Finished Jul 26 07:00:47 PM PDT 24
Peak memory 198596 kb
Host smart-327eeffa-e0fe-4ac7-9a61-5972808a71e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712602925 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_dis
able_rom_integrity_check.3712602925
Directory /workspace/48.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_tl_errors.3505815584
Short name T80
Test name
Test status
Simulation time 53712747 ps
CPU time 1.49 seconds
Started Jul 26 06:49:13 PM PDT 24
Finished Jul 26 06:49:15 PM PDT 24
Peak memory 196860 kb
Host smart-2b0d9cc7-1534-44c1-8f5b-6a3f9288ed8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505815584 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_errors.3505815584
Directory /workspace/16.pwrmgr_tl_errors/latest

Test location /workspace/coverage/default/14.pwrmgr_aborted_low_power.618877854
Short name T96
Test name
Test status
Simulation time 36026654 ps
CPU time 1.1 seconds
Started Jul 26 06:58:34 PM PDT 24
Finished Jul 26 06:58:35 PM PDT 24
Peak memory 200916 kb
Host smart-ed5f3f57-3e52-4bcf-b8d1-205cb0af6108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618877854 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_aborted_low_power.618877854
Directory /workspace/14.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/27.pwrmgr_lowpower_invalid.1247074062
Short name T528
Test name
Test status
Simulation time 44245103 ps
CPU time 0.69 seconds
Started Jul 26 06:59:32 PM PDT 24
Finished Jul 26 06:59:33 PM PDT 24
Peak memory 201424 kb
Host smart-12d01bb6-e19d-44bc-8ef5-51c099d1c734
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247074062 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_lowpower_inval
id.1247074062
Directory /workspace/27.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.2779231741
Short name T107
Test name
Test status
Simulation time 67486457 ps
CPU time 0.65 seconds
Started Jul 26 06:48:28 PM PDT 24
Finished Jul 26 06:48:29 PM PDT 24
Peak memory 195632 kb
Host smart-4ed083c1-4973-49e3-ba3b-6ef480a7383f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779231741 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_hw_reset.2
779231741
Directory /workspace/1.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.2921561123
Short name T23
Test name
Test status
Simulation time 320090927 ps
CPU time 1.42 seconds
Started Jul 26 06:48:26 PM PDT 24
Finished Jul 26 06:48:28 PM PDT 24
Peak memory 201044 kb
Host smart-e0730751-726d-4e38-9046-ec0ad4a8a98c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921561123 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_intg_err
.2921561123
Directory /workspace/3.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/11.pwrmgr_disable_rom_integrity_check.2297784641
Short name T482
Test name
Test status
Simulation time 67174968 ps
CPU time 0.7 seconds
Started Jul 26 06:58:27 PM PDT 24
Finished Jul 26 06:58:28 PM PDT 24
Peak memory 199136 kb
Host smart-3c51b10e-2d9f-4d57-a7a0-41bdc8dd6204
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297784641 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_dis
able_rom_integrity_check.2297784641
Directory /workspace/11.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/11.pwrmgr_lowpower_invalid.272409852
Short name T189
Test name
Test status
Simulation time 51397198 ps
CPU time 0.66 seconds
Started Jul 26 06:58:26 PM PDT 24
Finished Jul 26 06:58:27 PM PDT 24
Peak memory 201368 kb
Host smart-1a5fd3a6-666e-47c2-b9dd-07cae60e06c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272409852 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_lowpower_invali
d.272409852
Directory /workspace/11.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/18.pwrmgr_lowpower_invalid.1414993238
Short name T187
Test name
Test status
Simulation time 41221380 ps
CPU time 0.72 seconds
Started Jul 26 06:58:58 PM PDT 24
Finished Jul 26 06:58:59 PM PDT 24
Peak memory 201408 kb
Host smart-3c75040b-3353-468d-bd15-a14254542d55
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414993238 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_lowpower_inval
id.1414993238
Directory /workspace/18.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/20.pwrmgr_disable_rom_integrity_check.397345849
Short name T154
Test name
Test status
Simulation time 65939838 ps
CPU time 0.64 seconds
Started Jul 26 06:59:04 PM PDT 24
Finished Jul 26 06:59:05 PM PDT 24
Peak memory 198300 kb
Host smart-ad0f705b-3eaf-419e-8afd-99b922a03ed2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397345849 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_disa
ble_rom_integrity_check.397345849
Directory /workspace/20.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/32.pwrmgr_lowpower_invalid.3288080663
Short name T186
Test name
Test status
Simulation time 90735400 ps
CPU time 0.67 seconds
Started Jul 26 06:59:46 PM PDT 24
Finished Jul 26 06:59:46 PM PDT 24
Peak memory 201444 kb
Host smart-ed04c130-c723-4b42-9538-6feb8c9259da
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288080663 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_lowpower_inval
id.3288080663
Directory /workspace/32.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/48.pwrmgr_lowpower_invalid.3104492259
Short name T192
Test name
Test status
Simulation time 40472917 ps
CPU time 0.73 seconds
Started Jul 26 07:00:40 PM PDT 24
Finished Jul 26 07:00:41 PM PDT 24
Peak memory 201436 kb
Host smart-22617aa6-d5bb-473a-b42e-96fa07f62b68
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104492259 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_lowpower_inval
id.3104492259
Directory /workspace/48.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/0.pwrmgr_glitch.391038199
Short name T209
Test name
Test status
Simulation time 130088188 ps
CPU time 0.61 seconds
Started Jul 26 06:57:29 PM PDT 24
Finished Jul 26 06:57:30 PM PDT 24
Peak memory 198072 kb
Host smart-bcc69588-1826-4bb8-80cc-5c0745ef6266
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391038199 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_glitch.391038199
Directory /workspace/0.pwrmgr_glitch/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm.2863239590
Short name T31
Test name
Test status
Simulation time 728368652 ps
CPU time 1.58 seconds
Started Jul 26 06:57:30 PM PDT 24
Finished Jul 26 06:57:31 PM PDT 24
Peak memory 218056 kb
Host smart-1f32fcbd-a711-4cdb-a3d6-f3a4ac33790b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863239590 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm.2863239590
Directory /workspace/0.pwrmgr_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_intr_test.3341254362
Short name T76
Test name
Test status
Simulation time 18246955 ps
CPU time 0.62 seconds
Started Jul 26 06:48:29 PM PDT 24
Finished Jul 26 06:48:29 PM PDT 24
Peak memory 195496 kb
Host smart-d374f880-d08e-47d6-a36e-eade48b2f4cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341254362 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_intr_test.3341254362
Directory /workspace/1.pwrmgr_intr_test/latest

Test location /workspace/coverage/default/10.pwrmgr_lowpower_invalid.881400198
Short name T197
Test name
Test status
Simulation time 44374200 ps
CPU time 0.73 seconds
Started Jul 26 06:58:26 PM PDT 24
Finished Jul 26 06:58:27 PM PDT 24
Peak memory 201412 kb
Host smart-35a13594-6d77-4c3d-b77a-d426995096af
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881400198 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_lowpower_invali
d.881400198
Directory /workspace/10.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/18.pwrmgr_lowpower_wakeup_race.4259881652
Short name T144
Test name
Test status
Simulation time 92613968 ps
CPU time 0.63 seconds
Started Jul 26 06:58:51 PM PDT 24
Finished Jul 26 06:58:52 PM PDT 24
Peak memory 198572 kb
Host smart-8f15bb6a-e5fe-495f-90a1-60e4848ac39e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259881652 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_lowpower_w
akeup_race.4259881652
Directory /workspace/18.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/19.pwrmgr_disable_rom_integrity_check.1112041480
Short name T153
Test name
Test status
Simulation time 73019662 ps
CPU time 0.66 seconds
Started Jul 26 06:58:58 PM PDT 24
Finished Jul 26 06:58:59 PM PDT 24
Peak memory 199232 kb
Host smart-002e0431-a1d2-4ff5-9768-55e7f61b8ab0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112041480 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_dis
able_rom_integrity_check.1112041480
Directory /workspace/19.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/21.pwrmgr_lowpower_invalid.284161524
Short name T199
Test name
Test status
Simulation time 40522918 ps
CPU time 0.73 seconds
Started Jul 26 06:59:06 PM PDT 24
Finished Jul 26 06:59:07 PM PDT 24
Peak memory 201476 kb
Host smart-288d85f9-ea57-4074-a3ea-08f7a3e0a36b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284161524 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_lowpower_invali
d.284161524
Directory /workspace/21.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/39.pwrmgr_lowpower_invalid.3424669502
Short name T170
Test name
Test status
Simulation time 42954171 ps
CPU time 0.71 seconds
Started Jul 26 07:00:11 PM PDT 24
Finished Jul 26 07:00:12 PM PDT 24
Peak memory 201400 kb
Host smart-07e025e5-08dc-400b-9e9f-b72266d6f208
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424669502 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_lowpower_inval
id.3424669502
Directory /workspace/39.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/6.pwrmgr_wakeup_reset.356674069
Short name T57
Test name
Test status
Simulation time 59078098 ps
CPU time 0.64 seconds
Started Jul 26 06:58:04 PM PDT 24
Finished Jul 26 06:58:04 PM PDT 24
Peak memory 198652 kb
Host smart-46a39673-a030-4098-94d8-385ace703dde
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356674069 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_wakeup_reset.356674069
Directory /workspace/6.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.4023811333
Short name T78
Test name
Test status
Simulation time 555294050 ps
CPU time 1.51 seconds
Started Jul 26 06:48:19 PM PDT 24
Finished Jul 26 06:48:21 PM PDT 24
Peak memory 195948 kb
Host smart-db2f5b1c-f372-4eca-a20a-a0825d4b1344
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023811333 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_intg_err
.4023811333
Directory /workspace/0.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.1530309676
Short name T83
Test name
Test status
Simulation time 281881874 ps
CPU time 1.55 seconds
Started Jul 26 06:49:16 PM PDT 24
Finished Jul 26 06:49:18 PM PDT 24
Peak memory 201172 kb
Host smart-fa35932e-fd5b-4b8f-b0a9-f602236e23a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530309676 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_intg_er
r.1530309676
Directory /workspace/16.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.195150397
Short name T631
Test name
Test status
Simulation time 77689770 ps
CPU time 0.96 seconds
Started Jul 26 06:48:21 PM PDT 24
Finished Jul 26 06:48:22 PM PDT 24
Peak memory 195588 kb
Host smart-0dc7e985-de75-4b89-96e9-3f16d37242fa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195150397 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_aliasing.195150397
Directory /workspace/0.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.3398096935
Short name T657
Test name
Test status
Simulation time 194837464 ps
CPU time 1.69 seconds
Started Jul 26 06:48:20 PM PDT 24
Finished Jul 26 06:48:22 PM PDT 24
Peak memory 195768 kb
Host smart-ae3652ec-b97b-43ad-98c6-b7e7185aab15
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398096935 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_bit_bash.3
398096935
Directory /workspace/0.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.1023950005
Short name T111
Test name
Test status
Simulation time 86809211 ps
CPU time 0.62 seconds
Started Jul 26 06:48:21 PM PDT 24
Finished Jul 26 06:48:22 PM PDT 24
Peak memory 198344 kb
Host smart-81ec27ed-1bdd-4666-9349-81414a63b847
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023950005 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_hw_reset.1
023950005
Directory /workspace/0.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.3750426937
Short name T22
Test name
Test status
Simulation time 123080629 ps
CPU time 0.85 seconds
Started Jul 26 06:48:19 PM PDT 24
Finished Jul 26 06:48:20 PM PDT 24
Peak memory 195772 kb
Host smart-ce24a076-9ea7-455a-9f18-707d32770ef2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750426937 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.pwrmgr_csr_mem_rw_with_rand_reset.3750426937
Directory /workspace/0.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_rw.3492233474
Short name T118
Test name
Test status
Simulation time 29525348 ps
CPU time 0.62 seconds
Started Jul 26 06:48:22 PM PDT 24
Finished Jul 26 06:48:23 PM PDT 24
Peak memory 195604 kb
Host smart-365db292-99cf-4f02-91c8-4f9e06124ab4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492233474 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_rw.3492233474
Directory /workspace/0.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_intr_test.764118498
Short name T75
Test name
Test status
Simulation time 48009722 ps
CPU time 0.58 seconds
Started Jul 26 06:48:19 PM PDT 24
Finished Jul 26 06:48:20 PM PDT 24
Peak memory 195540 kb
Host smart-e66be718-3f47-40eb-9cd7-054fb03f3def
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764118498 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_intr_test.764118498
Directory /workspace/0.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.261866762
Short name T724
Test name
Test status
Simulation time 22315329 ps
CPU time 0.73 seconds
Started Jul 26 06:48:19 PM PDT 24
Finished Jul 26 06:48:20 PM PDT 24
Peak memory 197952 kb
Host smart-7f59d4bd-d5bc-4ba8-b45a-bffb64c43ad1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261866762 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sam
e_csr_outstanding.261866762
Directory /workspace/0.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_tl_errors.3661960162
Short name T653
Test name
Test status
Simulation time 251961430 ps
CPU time 2.05 seconds
Started Jul 26 06:48:20 PM PDT 24
Finished Jul 26 06:48:23 PM PDT 24
Peak memory 197940 kb
Host smart-d55ec834-1aaf-4ec8-b11a-34646c6fa5db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661960162 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_errors.3661960162
Directory /workspace/0.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.109144187
Short name T666
Test name
Test status
Simulation time 20251802 ps
CPU time 0.76 seconds
Started Jul 26 06:48:29 PM PDT 24
Finished Jul 26 06:48:30 PM PDT 24
Peak memory 197912 kb
Host smart-7d6544b9-dc80-482e-bb8c-c0f5c2a059ba
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109144187 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_aliasing.109144187
Directory /workspace/1.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.2955690602
Short name T711
Test name
Test status
Simulation time 565151279 ps
CPU time 2.1 seconds
Started Jul 26 06:48:28 PM PDT 24
Finished Jul 26 06:48:30 PM PDT 24
Peak memory 195764 kb
Host smart-deb64598-9594-4d89-963f-a56fd560b5c5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955690602 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_bit_bash.2
955690602
Directory /workspace/1.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.2919869393
Short name T710
Test name
Test status
Simulation time 52223644 ps
CPU time 0.78 seconds
Started Jul 26 06:48:27 PM PDT 24
Finished Jul 26 06:48:28 PM PDT 24
Peak memory 195808 kb
Host smart-12ffc7ac-476e-4ed9-91af-778ef0db2e61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919869393 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.pwrmgr_csr_mem_rw_with_rand_reset.2919869393
Directory /workspace/1.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_rw.2299872520
Short name T112
Test name
Test status
Simulation time 80002973 ps
CPU time 0.64 seconds
Started Jul 26 06:48:27 PM PDT 24
Finished Jul 26 06:48:28 PM PDT 24
Peak memory 195524 kb
Host smart-a332d227-72df-4695-9fd2-1cc90a6774b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299872520 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_rw.2299872520
Directory /workspace/1.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.2613936964
Short name T122
Test name
Test status
Simulation time 27246514 ps
CPU time 0.81 seconds
Started Jul 26 06:48:26 PM PDT 24
Finished Jul 26 06:48:27 PM PDT 24
Peak memory 195548 kb
Host smart-fd9d4ed9-1068-4fda-b467-cadc1b47dc84
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613936964 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sa
me_csr_outstanding.2613936964
Directory /workspace/1.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_tl_errors.940057357
Short name T647
Test name
Test status
Simulation time 83721488 ps
CPU time 2.11 seconds
Started Jul 26 06:48:21 PM PDT 24
Finished Jul 26 06:48:23 PM PDT 24
Peak memory 198056 kb
Host smart-f7c2d1ff-4f8c-4de6-bf07-02b6665aafa8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940057357 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_errors.940057357
Directory /workspace/1.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.636900692
Short name T82
Test name
Test status
Simulation time 142119352 ps
CPU time 1.08 seconds
Started Jul 26 06:48:23 PM PDT 24
Finished Jul 26 06:48:25 PM PDT 24
Peak memory 200776 kb
Host smart-9c0c50e3-c163-4780-b028-5c0976851cc2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636900692 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_intg_err.
636900692
Directory /workspace/1.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.1275878198
Short name T737
Test name
Test status
Simulation time 105814091 ps
CPU time 1.39 seconds
Started Jul 26 06:49:12 PM PDT 24
Finished Jul 26 06:49:14 PM PDT 24
Peak memory 201212 kb
Host smart-546c7b60-dabc-41bc-be32-06767548fe55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275878198 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.pwrmgr_csr_mem_rw_with_rand_reset.1275878198
Directory /workspace/10.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_csr_rw.1357796993
Short name T120
Test name
Test status
Simulation time 30116840 ps
CPU time 0.65 seconds
Started Jul 26 06:49:11 PM PDT 24
Finished Jul 26 06:49:12 PM PDT 24
Peak memory 196804 kb
Host smart-5c07f881-1f45-436e-8ff6-6ebb8269394b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357796993 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_csr_rw.1357796993
Directory /workspace/10.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_intr_test.11982058
Short name T664
Test name
Test status
Simulation time 17415771 ps
CPU time 0.6 seconds
Started Jul 26 06:49:09 PM PDT 24
Finished Jul 26 06:49:09 PM PDT 24
Peak memory 195536 kb
Host smart-9df1df50-f492-4080-9399-91b247658d03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11982058 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_intr_test.11982058
Directory /workspace/10.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.2067858098
Short name T124
Test name
Test status
Simulation time 41583616 ps
CPU time 0.84 seconds
Started Jul 26 06:49:09 PM PDT 24
Finished Jul 26 06:49:10 PM PDT 24
Peak memory 199000 kb
Host smart-9e71cbaf-2c12-4f9d-a6f7-4c37c068ef8b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067858098 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_s
ame_csr_outstanding.2067858098
Directory /workspace/10.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_tl_errors.1978691120
Short name T692
Test name
Test status
Simulation time 91977116 ps
CPU time 2.32 seconds
Started Jul 26 06:49:10 PM PDT 24
Finished Jul 26 06:49:13 PM PDT 24
Peak memory 196948 kb
Host smart-ddbe0122-c17d-498d-bb9c-76aed24a384f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978691120 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_errors.1978691120
Directory /workspace/10.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.438341007
Short name T717
Test name
Test status
Simulation time 203972018 ps
CPU time 1.74 seconds
Started Jul 26 06:49:12 PM PDT 24
Finished Jul 26 06:49:14 PM PDT 24
Peak memory 200880 kb
Host smart-e63c5657-baeb-447c-a2cb-6578668fe534
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438341007 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_intg_err
.438341007
Directory /workspace/10.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.1991171303
Short name T133
Test name
Test status
Simulation time 70228670 ps
CPU time 0.71 seconds
Started Jul 26 06:49:11 PM PDT 24
Finished Jul 26 06:49:11 PM PDT 24
Peak memory 195748 kb
Host smart-4efb49dc-dff7-475b-bc8f-b5ef22164d56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991171303 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.pwrmgr_csr_mem_rw_with_rand_reset.1991171303
Directory /workspace/11.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_csr_rw.1136230277
Short name T730
Test name
Test status
Simulation time 17439932 ps
CPU time 0.64 seconds
Started Jul 26 06:49:11 PM PDT 24
Finished Jul 26 06:49:11 PM PDT 24
Peak memory 195624 kb
Host smart-c3e6fd69-ffc6-48a1-a3df-a08477c24f87
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136230277 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_csr_rw.1136230277
Directory /workspace/11.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_intr_test.1312197845
Short name T735
Test name
Test status
Simulation time 28691878 ps
CPU time 0.63 seconds
Started Jul 26 06:49:13 PM PDT 24
Finished Jul 26 06:49:14 PM PDT 24
Peak memory 195544 kb
Host smart-0ae1ad84-17a8-4cc3-a8d8-340f3e437c12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312197845 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_intr_test.1312197845
Directory /workspace/11.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.1117624274
Short name T659
Test name
Test status
Simulation time 117427188 ps
CPU time 0.9 seconds
Started Jul 26 06:49:12 PM PDT 24
Finished Jul 26 06:49:13 PM PDT 24
Peak memory 195596 kb
Host smart-bf34dcb4-d847-4f4e-9f74-8d239077d40f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117624274 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_s
ame_csr_outstanding.1117624274
Directory /workspace/11.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_tl_errors.1247197422
Short name T706
Test name
Test status
Simulation time 849536268 ps
CPU time 2.51 seconds
Started Jul 26 06:49:12 PM PDT 24
Finished Jul 26 06:49:15 PM PDT 24
Peak memory 197952 kb
Host smart-a26ffc07-5ffc-4f68-87ca-09786f16fb25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247197422 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_errors.1247197422
Directory /workspace/11.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.2530735784
Short name T21
Test name
Test status
Simulation time 77898460 ps
CPU time 0.73 seconds
Started Jul 26 06:49:12 PM PDT 24
Finished Jul 26 06:49:13 PM PDT 24
Peak memory 195804 kb
Host smart-86b518e9-0ae4-4a84-a2d1-c3cada3031eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530735784 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.pwrmgr_csr_mem_rw_with_rand_reset.2530735784
Directory /workspace/12.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_csr_rw.3161169596
Short name T126
Test name
Test status
Simulation time 19668517 ps
CPU time 0.67 seconds
Started Jul 26 06:49:12 PM PDT 24
Finished Jul 26 06:49:13 PM PDT 24
Peak memory 197800 kb
Host smart-0c22897d-ff91-4fa9-998f-a5d4bfdb1abf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161169596 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_csr_rw.3161169596
Directory /workspace/12.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_intr_test.1635578685
Short name T650
Test name
Test status
Simulation time 101574340 ps
CPU time 0.59 seconds
Started Jul 26 06:49:13 PM PDT 24
Finished Jul 26 06:49:14 PM PDT 24
Peak memory 195576 kb
Host smart-7afe14d0-2841-4647-87c3-1b40008c61cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635578685 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_intr_test.1635578685
Directory /workspace/12.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.4205582060
Short name T70
Test name
Test status
Simulation time 109153233 ps
CPU time 0.87 seconds
Started Jul 26 06:49:14 PM PDT 24
Finished Jul 26 06:49:16 PM PDT 24
Peak memory 198912 kb
Host smart-d4b5bfc9-e84f-4fe0-8156-d925917fb59f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205582060 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_s
ame_csr_outstanding.4205582060
Directory /workspace/12.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_tl_errors.3432626445
Short name T707
Test name
Test status
Simulation time 312296392 ps
CPU time 1.58 seconds
Started Jul 26 06:49:11 PM PDT 24
Finished Jul 26 06:49:13 PM PDT 24
Peak memory 196780 kb
Host smart-26b4842f-ca6a-42d1-8f77-3e841cf69b4c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432626445 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_errors.3432626445
Directory /workspace/12.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.1134825629
Short name T691
Test name
Test status
Simulation time 588706621 ps
CPU time 1.5 seconds
Started Jul 26 06:49:11 PM PDT 24
Finished Jul 26 06:49:13 PM PDT 24
Peak memory 201008 kb
Host smart-fbfa728e-17d2-4149-a574-8a6fa9cb3f71
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134825629 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_intg_er
r.1134825629
Directory /workspace/12.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.689517484
Short name T732
Test name
Test status
Simulation time 78774273 ps
CPU time 0.99 seconds
Started Jul 26 06:49:12 PM PDT 24
Finished Jul 26 06:49:13 PM PDT 24
Peak memory 195744 kb
Host smart-05be1c7b-2463-425f-af3d-daf5b28bc313
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689517484 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.pwrmgr_csr_mem_rw_with_rand_reset.689517484
Directory /workspace/13.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_csr_rw.725547790
Short name T690
Test name
Test status
Simulation time 25622713 ps
CPU time 0.7 seconds
Started Jul 26 06:49:12 PM PDT 24
Finished Jul 26 06:49:14 PM PDT 24
Peak memory 197780 kb
Host smart-fbe0573d-7a0f-415b-983f-e6ba73f72df0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725547790 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_csr_rw.725547790
Directory /workspace/13.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_intr_test.2949962437
Short name T632
Test name
Test status
Simulation time 20541231 ps
CPU time 0.69 seconds
Started Jul 26 06:49:14 PM PDT 24
Finished Jul 26 06:49:15 PM PDT 24
Peak memory 195560 kb
Host smart-79401f6c-88c9-47a5-b2a8-6cd752b7e747
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949962437 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_intr_test.2949962437
Directory /workspace/13.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.2811738026
Short name T694
Test name
Test status
Simulation time 42497006 ps
CPU time 0.71 seconds
Started Jul 26 06:49:13 PM PDT 24
Finished Jul 26 06:49:15 PM PDT 24
Peak memory 195684 kb
Host smart-acd53f84-38dc-48f9-84e8-cc342f1d8af6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811738026 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_s
ame_csr_outstanding.2811738026
Directory /workspace/13.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_tl_errors.2265396905
Short name T682
Test name
Test status
Simulation time 62369803 ps
CPU time 1.45 seconds
Started Jul 26 06:49:12 PM PDT 24
Finished Jul 26 06:49:14 PM PDT 24
Peak memory 196948 kb
Host smart-05d4325b-0631-4157-8aaf-44e1fa50321d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265396905 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_errors.2265396905
Directory /workspace/13.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.1370765172
Short name T703
Test name
Test status
Simulation time 235618804 ps
CPU time 1.06 seconds
Started Jul 26 06:49:13 PM PDT 24
Finished Jul 26 06:49:14 PM PDT 24
Peak memory 195900 kb
Host smart-a750963c-7d3f-46fa-ad3f-3cc17fc08d62
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370765172 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_intg_er
r.1370765172
Directory /workspace/13.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.314251229
Short name T79
Test name
Test status
Simulation time 69462796 ps
CPU time 0.77 seconds
Started Jul 26 06:49:12 PM PDT 24
Finished Jul 26 06:49:13 PM PDT 24
Peak memory 195844 kb
Host smart-06cc424a-4d15-4244-a717-a5093e1a308a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314251229 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.pwrmgr_csr_mem_rw_with_rand_reset.314251229
Directory /workspace/14.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_csr_rw.1035506545
Short name T722
Test name
Test status
Simulation time 48068428 ps
CPU time 0.61 seconds
Started Jul 26 06:49:13 PM PDT 24
Finished Jul 26 06:49:14 PM PDT 24
Peak memory 195588 kb
Host smart-7e30e22e-0d58-41cb-a359-861f254b1448
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035506545 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_csr_rw.1035506545
Directory /workspace/14.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_intr_test.2276830998
Short name T689
Test name
Test status
Simulation time 35352737 ps
CPU time 0.59 seconds
Started Jul 26 06:49:15 PM PDT 24
Finished Jul 26 06:49:16 PM PDT 24
Peak memory 195524 kb
Host smart-bf7edf84-da32-4b30-b401-a5edab903c16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276830998 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_intr_test.2276830998
Directory /workspace/14.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.1656333086
Short name T678
Test name
Test status
Simulation time 63960538 ps
CPU time 0.85 seconds
Started Jul 26 06:49:15 PM PDT 24
Finished Jul 26 06:49:16 PM PDT 24
Peak memory 198836 kb
Host smart-0e6ef889-e0a6-4379-a316-acab5b47994f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656333086 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_s
ame_csr_outstanding.1656333086
Directory /workspace/14.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_tl_errors.3833238181
Short name T728
Test name
Test status
Simulation time 37726736 ps
CPU time 1.66 seconds
Started Jul 26 06:49:13 PM PDT 24
Finished Jul 26 06:49:15 PM PDT 24
Peak memory 198064 kb
Host smart-131fecb3-d1d7-416c-b966-104b74fc5341
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833238181 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_errors.3833238181
Directory /workspace/14.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.3604254426
Short name T725
Test name
Test status
Simulation time 129337659 ps
CPU time 1.03 seconds
Started Jul 26 06:49:12 PM PDT 24
Finished Jul 26 06:49:14 PM PDT 24
Peak memory 200728 kb
Host smart-c094ff88-6708-4074-ab3c-5c401339fd8b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604254426 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_intg_er
r.3604254426
Directory /workspace/14.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.843788368
Short name T739
Test name
Test status
Simulation time 52161419 ps
CPU time 0.86 seconds
Started Jul 26 06:49:16 PM PDT 24
Finished Jul 26 06:49:17 PM PDT 24
Peak memory 195780 kb
Host smart-45450867-f842-40ca-b46e-21be48f757f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843788368 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.pwrmgr_csr_mem_rw_with_rand_reset.843788368
Directory /workspace/15.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_intr_test.2939710001
Short name T716
Test name
Test status
Simulation time 53286599 ps
CPU time 0.62 seconds
Started Jul 26 06:49:15 PM PDT 24
Finished Jul 26 06:49:16 PM PDT 24
Peak memory 195536 kb
Host smart-a3388f7b-c996-42a5-991d-1e1480bfcf9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939710001 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_intr_test.2939710001
Directory /workspace/15.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.889578827
Short name T123
Test name
Test status
Simulation time 194656632 ps
CPU time 0.88 seconds
Started Jul 26 06:49:14 PM PDT 24
Finished Jul 26 06:49:15 PM PDT 24
Peak memory 198912 kb
Host smart-5cd345f7-abae-4964-86da-d6a33ecf43ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889578827 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sa
me_csr_outstanding.889578827
Directory /workspace/15.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_tl_errors.3192816060
Short name T639
Test name
Test status
Simulation time 362520481 ps
CPU time 1.58 seconds
Started Jul 26 06:49:12 PM PDT 24
Finished Jul 26 06:49:13 PM PDT 24
Peak memory 196844 kb
Host smart-154e61c3-323e-48c0-8ae4-2a35c22259f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192816060 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_errors.3192816060
Directory /workspace/15.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.1665059483
Short name T634
Test name
Test status
Simulation time 279452624 ps
CPU time 1.58 seconds
Started Jul 26 06:49:15 PM PDT 24
Finished Jul 26 06:49:16 PM PDT 24
Peak memory 201116 kb
Host smart-b0e2dab0-7d15-4f0e-a2a8-dd7f37ce9925
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665059483 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_intg_er
r.1665059483
Directory /workspace/15.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.4021357413
Short name T697
Test name
Test status
Simulation time 56148573 ps
CPU time 0.94 seconds
Started Jul 26 06:49:14 PM PDT 24
Finished Jul 26 06:49:15 PM PDT 24
Peak memory 195796 kb
Host smart-b93e9854-40d6-4212-a5f6-e3c797027249
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021357413 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.pwrmgr_csr_mem_rw_with_rand_reset.4021357413
Directory /workspace/16.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_csr_rw.3887557769
Short name T108
Test name
Test status
Simulation time 162551596 ps
CPU time 0.68 seconds
Started Jul 26 06:49:18 PM PDT 24
Finished Jul 26 06:49:19 PM PDT 24
Peak memory 195616 kb
Host smart-a9ce4c77-6f5f-4c85-86c6-9c4a266aedbb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887557769 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_csr_rw.3887557769
Directory /workspace/16.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_intr_test.473876517
Short name T649
Test name
Test status
Simulation time 59294491 ps
CPU time 0.61 seconds
Started Jul 26 06:49:13 PM PDT 24
Finished Jul 26 06:49:14 PM PDT 24
Peak memory 195564 kb
Host smart-9e6f8dda-9f75-47fc-896f-2535f54d7319
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473876517 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_intr_test.473876517
Directory /workspace/16.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.2269939794
Short name T641
Test name
Test status
Simulation time 21357345 ps
CPU time 0.83 seconds
Started Jul 26 06:49:17 PM PDT 24
Finished Jul 26 06:49:18 PM PDT 24
Peak memory 195664 kb
Host smart-f297accf-32d9-43d6-9e4d-b246e58c2c85
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269939794 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_s
ame_csr_outstanding.2269939794
Directory /workspace/16.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.2729884506
Short name T714
Test name
Test status
Simulation time 36174395 ps
CPU time 0.76 seconds
Started Jul 26 06:49:09 PM PDT 24
Finished Jul 26 06:49:10 PM PDT 24
Peak memory 195832 kb
Host smart-eebc19bf-2721-4f7e-a7d7-4a5875595728
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729884506 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.pwrmgr_csr_mem_rw_with_rand_reset.2729884506
Directory /workspace/17.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_csr_rw.3373004599
Short name T699
Test name
Test status
Simulation time 17769480 ps
CPU time 0.63 seconds
Started Jul 26 06:49:17 PM PDT 24
Finished Jul 26 06:49:18 PM PDT 24
Peak memory 195632 kb
Host smart-6869204e-bfe7-421e-8cb2-cef5baef0149
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373004599 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_csr_rw.3373004599
Directory /workspace/17.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_intr_test.416966495
Short name T640
Test name
Test status
Simulation time 41034042 ps
CPU time 0.62 seconds
Started Jul 26 06:49:14 PM PDT 24
Finished Jul 26 06:49:15 PM PDT 24
Peak memory 195568 kb
Host smart-48151d6a-193c-4069-9092-cb5505cbdde3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416966495 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_intr_test.416966495
Directory /workspace/17.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.520603339
Short name T726
Test name
Test status
Simulation time 44243666 ps
CPU time 0.83 seconds
Started Jul 26 06:49:14 PM PDT 24
Finished Jul 26 06:49:15 PM PDT 24
Peak memory 195572 kb
Host smart-4746fc25-1414-4233-a82e-6506fd2ae6b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520603339 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sa
me_csr_outstanding.520603339
Directory /workspace/17.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_tl_errors.556174862
Short name T675
Test name
Test status
Simulation time 416590903 ps
CPU time 2.5 seconds
Started Jul 26 06:49:14 PM PDT 24
Finished Jul 26 06:49:17 PM PDT 24
Peak memory 198948 kb
Host smart-918a23d6-80fa-4238-86bc-02ae2f85f23b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556174862 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_errors.556174862
Directory /workspace/17.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.3420899775
Short name T65
Test name
Test status
Simulation time 105362581 ps
CPU time 1.12 seconds
Started Jul 26 06:49:17 PM PDT 24
Finished Jul 26 06:49:19 PM PDT 24
Peak memory 200568 kb
Host smart-e8c82623-ade1-4fa2-823b-6d8a263f6738
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420899775 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_intg_er
r.3420899775
Directory /workspace/17.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.1277542159
Short name T655
Test name
Test status
Simulation time 42010745 ps
CPU time 0.9 seconds
Started Jul 26 06:49:13 PM PDT 24
Finished Jul 26 06:49:14 PM PDT 24
Peak memory 201108 kb
Host smart-0f505d58-6474-4a84-a13c-72cc89b2b114
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277542159 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.pwrmgr_csr_mem_rw_with_rand_reset.1277542159
Directory /workspace/18.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_csr_rw.1847472889
Short name T114
Test name
Test status
Simulation time 20777193 ps
CPU time 0.69 seconds
Started Jul 26 06:49:11 PM PDT 24
Finished Jul 26 06:49:11 PM PDT 24
Peak memory 197792 kb
Host smart-8f77faa2-8521-4746-a26c-5d76d79ca15b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847472889 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_csr_rw.1847472889
Directory /workspace/18.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_intr_test.4070780808
Short name T676
Test name
Test status
Simulation time 30159610 ps
CPU time 0.61 seconds
Started Jul 26 06:49:13 PM PDT 24
Finished Jul 26 06:49:14 PM PDT 24
Peak memory 195632 kb
Host smart-b166d68a-2c05-4106-9a9c-abc8af6433e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070780808 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_intr_test.4070780808
Directory /workspace/18.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.793724187
Short name T693
Test name
Test status
Simulation time 46947000 ps
CPU time 0.9 seconds
Started Jul 26 06:49:10 PM PDT 24
Finished Jul 26 06:49:11 PM PDT 24
Peak memory 195656 kb
Host smart-39ba235a-012e-4859-a943-89308893f06b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793724187 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sa
me_csr_outstanding.793724187
Directory /workspace/18.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_tl_errors.1961349004
Short name T67
Test name
Test status
Simulation time 262241974 ps
CPU time 2.89 seconds
Started Jul 26 06:49:12 PM PDT 24
Finished Jul 26 06:49:15 PM PDT 24
Peak memory 196992 kb
Host smart-756b42e5-110f-442b-8b99-f7d4b108f02a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961349004 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_errors.1961349004
Directory /workspace/18.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.3446457192
Short name T704
Test name
Test status
Simulation time 106079685 ps
CPU time 1.15 seconds
Started Jul 26 06:49:10 PM PDT 24
Finished Jul 26 06:49:11 PM PDT 24
Peak memory 200512 kb
Host smart-4726d902-1e16-4eaf-8185-b7efea854bdc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446457192 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_intg_er
r.3446457192
Directory /workspace/18.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.3962936035
Short name T74
Test name
Test status
Simulation time 146040754 ps
CPU time 1.06 seconds
Started Jul 26 06:49:13 PM PDT 24
Finished Jul 26 06:49:15 PM PDT 24
Peak memory 195616 kb
Host smart-3a916c18-2c0a-448b-98c1-c6546e6d8697
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962936035 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.pwrmgr_csr_mem_rw_with_rand_reset.3962936035
Directory /workspace/19.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_csr_rw.1869010593
Short name T115
Test name
Test status
Simulation time 32386355 ps
CPU time 0.63 seconds
Started Jul 26 06:49:11 PM PDT 24
Finished Jul 26 06:49:12 PM PDT 24
Peak memory 195596 kb
Host smart-c54c963f-9d7b-4bf6-85fd-37c772525449
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869010593 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_csr_rw.1869010593
Directory /workspace/19.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_intr_test.1543696448
Short name T654
Test name
Test status
Simulation time 38470068 ps
CPU time 0.6 seconds
Started Jul 26 06:49:12 PM PDT 24
Finished Jul 26 06:49:13 PM PDT 24
Peak memory 195560 kb
Host smart-be477175-c3ab-4e40-a0b4-d4419afcec5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543696448 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_intr_test.1543696448
Directory /workspace/19.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.24034259
Short name T718
Test name
Test status
Simulation time 95249716 ps
CPU time 0.89 seconds
Started Jul 26 06:49:10 PM PDT 24
Finished Jul 26 06:49:11 PM PDT 24
Peak memory 198868 kb
Host smart-a22eb518-be19-49b0-a860-d6d8f504c67b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24034259 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sam
e_csr_outstanding.24034259
Directory /workspace/19.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.1293463905
Short name T84
Test name
Test status
Simulation time 363832817 ps
CPU time 1.45 seconds
Started Jul 26 06:49:10 PM PDT 24
Finished Jul 26 06:49:12 PM PDT 24
Peak memory 195812 kb
Host smart-9afeecf2-d202-4679-a484-27beaa4ab019
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293463905 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_intg_er
r.1293463905
Directory /workspace/19.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.943130497
Short name T720
Test name
Test status
Simulation time 28113499 ps
CPU time 0.74 seconds
Started Jul 26 06:48:27 PM PDT 24
Finished Jul 26 06:48:28 PM PDT 24
Peak memory 195580 kb
Host smart-d894c3fc-8d4e-4f59-8331-549a25e15b21
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943130497 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_aliasing.943130497
Directory /workspace/2.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.1643763435
Short name T132
Test name
Test status
Simulation time 1123468699 ps
CPU time 3.31 seconds
Started Jul 26 06:48:27 PM PDT 24
Finished Jul 26 06:48:30 PM PDT 24
Peak memory 195840 kb
Host smart-cf230ac9-960f-479c-b5fd-ca4042430249
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643763435 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_bit_bash.1
643763435
Directory /workspace/2.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.3206004867
Short name T629
Test name
Test status
Simulation time 38884421 ps
CPU time 0.66 seconds
Started Jul 26 06:48:27 PM PDT 24
Finished Jul 26 06:48:28 PM PDT 24
Peak memory 198420 kb
Host smart-7242ef5d-7891-4ff2-8100-6c53b8dc3851
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206004867 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_hw_reset.3
206004867
Directory /workspace/2.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.2736845255
Short name T731
Test name
Test status
Simulation time 64570709 ps
CPU time 0.97 seconds
Started Jul 26 06:48:28 PM PDT 24
Finished Jul 26 06:48:29 PM PDT 24
Peak memory 195828 kb
Host smart-370fe261-dcc3-4634-ae47-8bd590ba70a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736845255 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.pwrmgr_csr_mem_rw_with_rand_reset.2736845255
Directory /workspace/2.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_rw.2706233916
Short name T734
Test name
Test status
Simulation time 52133954 ps
CPU time 0.61 seconds
Started Jul 26 06:48:28 PM PDT 24
Finished Jul 26 06:48:28 PM PDT 24
Peak memory 195604 kb
Host smart-f8d420c1-39dc-4c01-89a3-f5115934292a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706233916 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_rw.2706233916
Directory /workspace/2.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.1050111881
Short name T708
Test name
Test status
Simulation time 28276563 ps
CPU time 0.75 seconds
Started Jul 26 06:48:30 PM PDT 24
Finished Jul 26 06:48:31 PM PDT 24
Peak memory 197872 kb
Host smart-517f6bc7-8dd0-47f1-a792-59ddd5409674
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050111881 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sa
me_csr_outstanding.1050111881
Directory /workspace/2.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_tl_errors.3054165710
Short name T81
Test name
Test status
Simulation time 132370716 ps
CPU time 1.96 seconds
Started Jul 26 06:48:31 PM PDT 24
Finished Jul 26 06:48:33 PM PDT 24
Peak memory 198004 kb
Host smart-0b263fb9-a23f-464a-a107-7fcf2e8c1920
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054165710 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_errors.3054165710
Directory /workspace/2.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.3996181611
Short name T688
Test name
Test status
Simulation time 144994530 ps
CPU time 1.19 seconds
Started Jul 26 06:48:28 PM PDT 24
Finished Jul 26 06:48:29 PM PDT 24
Peak memory 200952 kb
Host smart-59cfe7fc-5a3e-42a5-900c-56b8e643ab8e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996181611 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_intg_err
.3996181611
Directory /workspace/2.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.pwrmgr_intr_test.2834826832
Short name T669
Test name
Test status
Simulation time 17386038 ps
CPU time 0.6 seconds
Started Jul 26 06:49:15 PM PDT 24
Finished Jul 26 06:49:16 PM PDT 24
Peak memory 195588 kb
Host smart-2d3d564f-5ff4-468f-af00-f9e4aba02fec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834826832 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.pwrmgr_intr_test.2834826832
Directory /workspace/20.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.pwrmgr_intr_test.176896924
Short name T661
Test name
Test status
Simulation time 17873896 ps
CPU time 0.62 seconds
Started Jul 26 06:49:12 PM PDT 24
Finished Jul 26 06:49:13 PM PDT 24
Peak memory 195460 kb
Host smart-a189c991-582c-4bff-8b79-f303c00cb286
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176896924 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.pwrmgr_intr_test.176896924
Directory /workspace/21.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.pwrmgr_intr_test.2202523637
Short name T157
Test name
Test status
Simulation time 25657097 ps
CPU time 0.62 seconds
Started Jul 26 06:49:11 PM PDT 24
Finished Jul 26 06:49:12 PM PDT 24
Peak memory 195544 kb
Host smart-45bfcef7-9fe9-4e7b-a51e-a877fa691683
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202523637 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.pwrmgr_intr_test.2202523637
Directory /workspace/22.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.pwrmgr_intr_test.3677221649
Short name T695
Test name
Test status
Simulation time 26188869 ps
CPU time 0.6 seconds
Started Jul 26 06:49:12 PM PDT 24
Finished Jul 26 06:49:13 PM PDT 24
Peak memory 195532 kb
Host smart-8ca85075-7ad5-4c57-b965-5fe5339f6ebf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677221649 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.pwrmgr_intr_test.3677221649
Directory /workspace/23.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.pwrmgr_intr_test.2299474359
Short name T636
Test name
Test status
Simulation time 65309456 ps
CPU time 0.58 seconds
Started Jul 26 06:49:14 PM PDT 24
Finished Jul 26 06:49:15 PM PDT 24
Peak memory 195588 kb
Host smart-bf5e1c30-4556-47b4-ae79-bc1821585aa6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299474359 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.pwrmgr_intr_test.2299474359
Directory /workspace/24.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.pwrmgr_intr_test.3504122614
Short name T658
Test name
Test status
Simulation time 25636912 ps
CPU time 0.66 seconds
Started Jul 26 06:49:12 PM PDT 24
Finished Jul 26 06:49:13 PM PDT 24
Peak memory 195568 kb
Host smart-1960bc52-4e8d-4f24-be65-44f0a36e89e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504122614 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.pwrmgr_intr_test.3504122614
Directory /workspace/25.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.pwrmgr_intr_test.1632447387
Short name T158
Test name
Test status
Simulation time 36123864 ps
CPU time 0.61 seconds
Started Jul 26 06:49:12 PM PDT 24
Finished Jul 26 06:49:14 PM PDT 24
Peak memory 195568 kb
Host smart-d31c0a45-abe7-4c9b-82db-b888573d8758
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632447387 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.pwrmgr_intr_test.1632447387
Directory /workspace/26.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.pwrmgr_intr_test.2190792534
Short name T77
Test name
Test status
Simulation time 35648564 ps
CPU time 0.64 seconds
Started Jul 26 06:49:12 PM PDT 24
Finished Jul 26 06:49:13 PM PDT 24
Peak memory 195556 kb
Host smart-2991962b-19de-4273-a2ad-e38ae3434fc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190792534 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.pwrmgr_intr_test.2190792534
Directory /workspace/27.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.pwrmgr_intr_test.878239962
Short name T701
Test name
Test status
Simulation time 19597130 ps
CPU time 0.63 seconds
Started Jul 26 06:49:12 PM PDT 24
Finished Jul 26 06:49:13 PM PDT 24
Peak memory 195588 kb
Host smart-89a1c9d1-092d-4812-878c-f6c228177123
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878239962 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.pwrmgr_intr_test.878239962
Directory /workspace/28.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.pwrmgr_intr_test.4136443874
Short name T673
Test name
Test status
Simulation time 41127684 ps
CPU time 0.64 seconds
Started Jul 26 06:49:14 PM PDT 24
Finished Jul 26 06:49:15 PM PDT 24
Peak memory 195588 kb
Host smart-139269a4-9988-4c0a-870e-c16420fd14c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136443874 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.pwrmgr_intr_test.4136443874
Directory /workspace/29.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.3204191742
Short name T685
Test name
Test status
Simulation time 53155666 ps
CPU time 0.8 seconds
Started Jul 26 06:48:34 PM PDT 24
Finished Jul 26 06:48:35 PM PDT 24
Peak memory 197668 kb
Host smart-fdb6aa40-5dc2-4de7-af8f-e917ccef8eb2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204191742 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_aliasing.3
204191742
Directory /workspace/3.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.3352161273
Short name T116
Test name
Test status
Simulation time 1603395345 ps
CPU time 3.49 seconds
Started Jul 26 06:48:35 PM PDT 24
Finished Jul 26 06:48:39 PM PDT 24
Peak memory 195744 kb
Host smart-d5631940-fb1e-485c-9e28-ecffbeea32fe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352161273 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_bit_bash.3
352161273
Directory /workspace/3.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.2838660754
Short name T110
Test name
Test status
Simulation time 30256285 ps
CPU time 0.69 seconds
Started Jul 26 06:48:28 PM PDT 24
Finished Jul 26 06:48:29 PM PDT 24
Peak memory 196816 kb
Host smart-604d5d0e-6f34-44d7-8e57-07794ea9494b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838660754 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_hw_reset.2
838660754
Directory /workspace/3.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.4059117880
Short name T638
Test name
Test status
Simulation time 43599384 ps
CPU time 1.12 seconds
Started Jul 26 06:48:35 PM PDT 24
Finished Jul 26 06:48:37 PM PDT 24
Peak memory 195804 kb
Host smart-0c39f393-db10-4e36-bc98-da750c057b12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059117880 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.pwrmgr_csr_mem_rw_with_rand_reset.4059117880
Directory /workspace/3.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_rw.2461177305
Short name T117
Test name
Test status
Simulation time 72401083 ps
CPU time 0.65 seconds
Started Jul 26 06:48:26 PM PDT 24
Finished Jul 26 06:48:27 PM PDT 24
Peak memory 197728 kb
Host smart-ba808326-e4a4-47bd-a61c-de6b3991b7a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461177305 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_rw.2461177305
Directory /workspace/3.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_intr_test.2508656059
Short name T679
Test name
Test status
Simulation time 18151078 ps
CPU time 0.62 seconds
Started Jul 26 06:48:27 PM PDT 24
Finished Jul 26 06:48:27 PM PDT 24
Peak memory 195536 kb
Host smart-36d99026-1b74-4c00-9ee4-52c48a07946b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508656059 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_intr_test.2508656059
Directory /workspace/3.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.3852564089
Short name T660
Test name
Test status
Simulation time 25013726 ps
CPU time 0.84 seconds
Started Jul 26 06:48:37 PM PDT 24
Finished Jul 26 06:48:37 PM PDT 24
Peak memory 195672 kb
Host smart-8c441d5c-0e7a-47b5-9b30-b4f123ccbcf5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852564089 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sa
me_csr_outstanding.3852564089
Directory /workspace/3.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_tl_errors.2777189680
Short name T72
Test name
Test status
Simulation time 43530582 ps
CPU time 1.04 seconds
Started Jul 26 06:48:28 PM PDT 24
Finished Jul 26 06:48:29 PM PDT 24
Peak memory 201032 kb
Host smart-8739f917-c846-4aac-b06c-f3a51ea97647
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777189680 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_errors.2777189680
Directory /workspace/3.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.pwrmgr_intr_test.516784197
Short name T667
Test name
Test status
Simulation time 62738068 ps
CPU time 0.62 seconds
Started Jul 26 06:49:14 PM PDT 24
Finished Jul 26 06:49:14 PM PDT 24
Peak memory 195428 kb
Host smart-580ff3fc-2c15-43e3-9664-b1ed9fc5c456
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516784197 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.pwrmgr_intr_test.516784197
Directory /workspace/30.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.pwrmgr_intr_test.4063986278
Short name T663
Test name
Test status
Simulation time 65382309 ps
CPU time 0.63 seconds
Started Jul 26 06:49:12 PM PDT 24
Finished Jul 26 06:49:13 PM PDT 24
Peak memory 195564 kb
Host smart-104640d4-005d-42cd-b340-1c950bc6589c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063986278 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.pwrmgr_intr_test.4063986278
Directory /workspace/31.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.pwrmgr_intr_test.1492153357
Short name T723
Test name
Test status
Simulation time 68441510 ps
CPU time 0.61 seconds
Started Jul 26 06:49:14 PM PDT 24
Finished Jul 26 06:49:15 PM PDT 24
Peak memory 195552 kb
Host smart-ecab25dd-30af-4535-a265-611443b2ec89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492153357 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.pwrmgr_intr_test.1492153357
Directory /workspace/32.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.pwrmgr_intr_test.4119112777
Short name T677
Test name
Test status
Simulation time 39477642 ps
CPU time 0.58 seconds
Started Jul 26 06:49:12 PM PDT 24
Finished Jul 26 06:49:14 PM PDT 24
Peak memory 195528 kb
Host smart-a4db1fd8-6af2-401f-8b19-2216be858813
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119112777 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.pwrmgr_intr_test.4119112777
Directory /workspace/33.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.pwrmgr_intr_test.3005571172
Short name T719
Test name
Test status
Simulation time 23484403 ps
CPU time 0.64 seconds
Started Jul 26 06:49:13 PM PDT 24
Finished Jul 26 06:49:14 PM PDT 24
Peak memory 195552 kb
Host smart-3862ca56-6f21-4540-9bb5-4ed5e3deeeef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005571172 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.pwrmgr_intr_test.3005571172
Directory /workspace/34.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.pwrmgr_intr_test.2857382072
Short name T645
Test name
Test status
Simulation time 60380633 ps
CPU time 0.62 seconds
Started Jul 26 06:49:13 PM PDT 24
Finished Jul 26 06:49:14 PM PDT 24
Peak memory 195536 kb
Host smart-dcfadbbf-6bd5-40a0-8872-099528565f02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857382072 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.pwrmgr_intr_test.2857382072
Directory /workspace/35.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.pwrmgr_intr_test.3113140611
Short name T644
Test name
Test status
Simulation time 17940038 ps
CPU time 0.61 seconds
Started Jul 26 06:49:16 PM PDT 24
Finished Jul 26 06:49:17 PM PDT 24
Peak memory 195524 kb
Host smart-97ec537f-5aad-4b38-855e-1686c2eeeb23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113140611 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.pwrmgr_intr_test.3113140611
Directory /workspace/36.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.pwrmgr_intr_test.1612265067
Short name T648
Test name
Test status
Simulation time 49527583 ps
CPU time 0.6 seconds
Started Jul 26 06:49:14 PM PDT 24
Finished Jul 26 06:49:15 PM PDT 24
Peak memory 195540 kb
Host smart-3fc1a56d-8d46-4816-ab45-344fdb128fb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612265067 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.pwrmgr_intr_test.1612265067
Directory /workspace/37.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.pwrmgr_intr_test.3665371410
Short name T637
Test name
Test status
Simulation time 35506295 ps
CPU time 0.59 seconds
Started Jul 26 06:49:11 PM PDT 24
Finished Jul 26 06:49:12 PM PDT 24
Peak memory 195500 kb
Host smart-a86da000-ac1f-4fe0-958f-43f269566714
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665371410 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.pwrmgr_intr_test.3665371410
Directory /workspace/38.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.pwrmgr_intr_test.3832078698
Short name T736
Test name
Test status
Simulation time 90825141 ps
CPU time 0.62 seconds
Started Jul 26 06:49:15 PM PDT 24
Finished Jul 26 06:49:16 PM PDT 24
Peak memory 195544 kb
Host smart-22857580-9231-4c95-ad72-567ac044f92a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832078698 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.pwrmgr_intr_test.3832078698
Directory /workspace/39.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.1471892614
Short name T662
Test name
Test status
Simulation time 174527875 ps
CPU time 0.97 seconds
Started Jul 26 06:48:36 PM PDT 24
Finished Jul 26 06:48:37 PM PDT 24
Peak memory 195560 kb
Host smart-521c9022-f91d-4e53-a2a9-7789655ed54e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471892614 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_aliasing.1
471892614
Directory /workspace/4.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.1145345496
Short name T672
Test name
Test status
Simulation time 400971938 ps
CPU time 1.82 seconds
Started Jul 26 06:48:35 PM PDT 24
Finished Jul 26 06:48:37 PM PDT 24
Peak memory 195792 kb
Host smart-09d138f1-6a95-4207-aebb-b58f46fc33eb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145345496 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_bit_bash.1
145345496
Directory /workspace/4.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.3140617755
Short name T109
Test name
Test status
Simulation time 27186917 ps
CPU time 0.65 seconds
Started Jul 26 06:48:35 PM PDT 24
Finished Jul 26 06:48:36 PM PDT 24
Peak memory 195600 kb
Host smart-97cb4654-1e71-4a4a-aa52-9eeb1dde01cf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140617755 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_hw_reset.3
140617755
Directory /workspace/4.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.3135963804
Short name T73
Test name
Test status
Simulation time 50578427 ps
CPU time 1.31 seconds
Started Jul 26 06:48:36 PM PDT 24
Finished Jul 26 06:48:37 PM PDT 24
Peak memory 196980 kb
Host smart-9124fe88-7f1e-4f27-8360-44a1688b6775
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135963804 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.pwrmgr_csr_mem_rw_with_rand_reset.3135963804
Directory /workspace/4.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_rw.2252698505
Short name T713
Test name
Test status
Simulation time 150635224 ps
CPU time 0.61 seconds
Started Jul 26 06:48:34 PM PDT 24
Finished Jul 26 06:48:35 PM PDT 24
Peak memory 197832 kb
Host smart-fd093e78-6053-41f7-bd21-c1c0ceff0e16
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252698505 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_rw.2252698505
Directory /workspace/4.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_intr_test.2191992539
Short name T698
Test name
Test status
Simulation time 17449280 ps
CPU time 0.64 seconds
Started Jul 26 06:48:32 PM PDT 24
Finished Jul 26 06:48:33 PM PDT 24
Peak memory 195560 kb
Host smart-98a47743-e4ea-4828-9f90-f1a12c78ee04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191992539 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_intr_test.2191992539
Directory /workspace/4.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.3192175645
Short name T121
Test name
Test status
Simulation time 21590504 ps
CPU time 0.82 seconds
Started Jul 26 06:48:35 PM PDT 24
Finished Jul 26 06:48:37 PM PDT 24
Peak memory 195580 kb
Host smart-3490436c-9c72-42a9-a331-e4408a3088d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192175645 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sa
me_csr_outstanding.3192175645
Directory /workspace/4.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_tl_errors.2710868473
Short name T66
Test name
Test status
Simulation time 187171284 ps
CPU time 1.25 seconds
Started Jul 26 06:48:35 PM PDT 24
Finished Jul 26 06:48:37 PM PDT 24
Peak memory 195988 kb
Host smart-76b2cfe2-8199-4dfb-a35c-7caa30601a05
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710868473 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_errors.2710868473
Directory /workspace/4.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.1707361233
Short name T147
Test name
Test status
Simulation time 418143666 ps
CPU time 1.51 seconds
Started Jul 26 06:48:36 PM PDT 24
Finished Jul 26 06:48:38 PM PDT 24
Peak memory 195840 kb
Host smart-72ee470b-0b61-4611-b274-173003f6dd24
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707361233 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_intg_err
.1707361233
Directory /workspace/4.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.pwrmgr_intr_test.3466033345
Short name T156
Test name
Test status
Simulation time 19205232 ps
CPU time 0.63 seconds
Started Jul 26 06:49:15 PM PDT 24
Finished Jul 26 06:49:16 PM PDT 24
Peak memory 195544 kb
Host smart-7bf8a30e-19ff-4ba9-b9cb-028be9e39d6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466033345 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.pwrmgr_intr_test.3466033345
Directory /workspace/40.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.pwrmgr_intr_test.28488831
Short name T680
Test name
Test status
Simulation time 19625191 ps
CPU time 0.63 seconds
Started Jul 26 06:49:15 PM PDT 24
Finished Jul 26 06:49:16 PM PDT 24
Peak memory 195620 kb
Host smart-0c43e158-9c40-43ec-938b-e3fa74d3738b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28488831 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.pwrmgr_intr_test.28488831
Directory /workspace/41.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.pwrmgr_intr_test.700823355
Short name T668
Test name
Test status
Simulation time 19639004 ps
CPU time 0.63 seconds
Started Jul 26 06:49:15 PM PDT 24
Finished Jul 26 06:49:16 PM PDT 24
Peak memory 195544 kb
Host smart-2245d8c8-ac39-4605-af42-5b88f3168131
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700823355 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.pwrmgr_intr_test.700823355
Directory /workspace/42.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.pwrmgr_intr_test.703642620
Short name T738
Test name
Test status
Simulation time 22518877 ps
CPU time 0.63 seconds
Started Jul 26 06:49:13 PM PDT 24
Finished Jul 26 06:49:14 PM PDT 24
Peak memory 195584 kb
Host smart-d0a97bfe-a74b-4eb7-908a-e6999a0ff289
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703642620 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.pwrmgr_intr_test.703642620
Directory /workspace/43.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.pwrmgr_intr_test.386996597
Short name T635
Test name
Test status
Simulation time 18119265 ps
CPU time 0.62 seconds
Started Jul 26 06:49:16 PM PDT 24
Finished Jul 26 06:49:17 PM PDT 24
Peak memory 195620 kb
Host smart-4ac7cb9b-2acb-4369-b064-813f17fffde1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386996597 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.pwrmgr_intr_test.386996597
Directory /workspace/44.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.pwrmgr_intr_test.3894489986
Short name T721
Test name
Test status
Simulation time 66746409 ps
CPU time 0.61 seconds
Started Jul 26 06:49:15 PM PDT 24
Finished Jul 26 06:49:16 PM PDT 24
Peak memory 195552 kb
Host smart-f294f76b-b8f7-42f3-a3c6-759de2353fae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894489986 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.pwrmgr_intr_test.3894489986
Directory /workspace/45.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.pwrmgr_intr_test.2635353714
Short name T671
Test name
Test status
Simulation time 29247809 ps
CPU time 0.61 seconds
Started Jul 26 06:49:15 PM PDT 24
Finished Jul 26 06:49:16 PM PDT 24
Peak memory 195624 kb
Host smart-8b938091-0c38-421c-a13c-8ade1ada6eaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635353714 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.pwrmgr_intr_test.2635353714
Directory /workspace/46.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.pwrmgr_intr_test.1816642109
Short name T684
Test name
Test status
Simulation time 21971057 ps
CPU time 0.63 seconds
Started Jul 26 06:49:14 PM PDT 24
Finished Jul 26 06:49:14 PM PDT 24
Peak memory 195568 kb
Host smart-e227e81f-43ee-4fb0-b924-6ff9fec05d1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816642109 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.pwrmgr_intr_test.1816642109
Directory /workspace/47.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.pwrmgr_intr_test.1093451945
Short name T651
Test name
Test status
Simulation time 50170570 ps
CPU time 0.59 seconds
Started Jul 26 06:49:19 PM PDT 24
Finished Jul 26 06:49:20 PM PDT 24
Peak memory 195560 kb
Host smart-1c71ae6e-b8d3-46b9-a21e-513587407c84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093451945 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.pwrmgr_intr_test.1093451945
Directory /workspace/48.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.pwrmgr_intr_test.387824249
Short name T159
Test name
Test status
Simulation time 145645188 ps
CPU time 0.61 seconds
Started Jul 26 06:49:21 PM PDT 24
Finished Jul 26 06:49:22 PM PDT 24
Peak memory 195608 kb
Host smart-b7dee4fd-ad3a-4974-8a15-fdc1d4d5d68f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387824249 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.pwrmgr_intr_test.387824249
Directory /workspace/49.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.459195185
Short name T712
Test name
Test status
Simulation time 329094637 ps
CPU time 0.85 seconds
Started Jul 26 06:48:42 PM PDT 24
Finished Jul 26 06:48:43 PM PDT 24
Peak memory 195732 kb
Host smart-e3566f70-3e02-4ab0-989e-149fa08d6f18
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459195185 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.pwrmgr_csr_mem_rw_with_rand_reset.459195185
Directory /workspace/5.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_csr_rw.1125214897
Short name T119
Test name
Test status
Simulation time 39533612 ps
CPU time 0.61 seconds
Started Jul 26 06:48:40 PM PDT 24
Finished Jul 26 06:48:41 PM PDT 24
Peak memory 195620 kb
Host smart-79551a7e-072e-460b-bbeb-c3f1289ff42a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125214897 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_csr_rw.1125214897
Directory /workspace/5.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_intr_test.3730989764
Short name T665
Test name
Test status
Simulation time 21337821 ps
CPU time 0.63 seconds
Started Jul 26 06:48:43 PM PDT 24
Finished Jul 26 06:48:44 PM PDT 24
Peak memory 195524 kb
Host smart-3a2a2330-ec24-48b1-b74b-96e45c6971de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730989764 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_intr_test.3730989764
Directory /workspace/5.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.2674151360
Short name T125
Test name
Test status
Simulation time 128137443 ps
CPU time 0.89 seconds
Started Jul 26 06:48:45 PM PDT 24
Finished Jul 26 06:48:46 PM PDT 24
Peak memory 199092 kb
Host smart-24a156df-671c-4cc5-beca-d9406ab9e290
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674151360 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sa
me_csr_outstanding.2674151360
Directory /workspace/5.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_tl_errors.1652190954
Short name T702
Test name
Test status
Simulation time 36666205 ps
CPU time 1.54 seconds
Started Jul 26 06:48:35 PM PDT 24
Finished Jul 26 06:48:37 PM PDT 24
Peak memory 197176 kb
Host smart-ff90c73a-1a96-4368-94b9-2f80e495efb3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652190954 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_errors.1652190954
Directory /workspace/5.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.3025928397
Short name T715
Test name
Test status
Simulation time 94589383 ps
CPU time 1.06 seconds
Started Jul 26 06:48:36 PM PDT 24
Finished Jul 26 06:48:37 PM PDT 24
Peak memory 200852 kb
Host smart-1b858347-6821-4b8a-b651-47714b09e38f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025928397 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_intg_err
.3025928397
Directory /workspace/5.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.2059747776
Short name T643
Test name
Test status
Simulation time 39145029 ps
CPU time 1.05 seconds
Started Jul 26 06:48:42 PM PDT 24
Finished Jul 26 06:48:43 PM PDT 24
Peak memory 196716 kb
Host smart-6b472174-0a33-4dfc-bf99-4793d95e1c8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059747776 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.pwrmgr_csr_mem_rw_with_rand_reset.2059747776
Directory /workspace/6.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_csr_rw.2929734427
Short name T709
Test name
Test status
Simulation time 45922942 ps
CPU time 0.6 seconds
Started Jul 26 06:48:43 PM PDT 24
Finished Jul 26 06:48:44 PM PDT 24
Peak memory 195632 kb
Host smart-75d409f1-182d-4e88-a97c-5868d8acac55
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929734427 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_csr_rw.2929734427
Directory /workspace/6.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_intr_test.610722843
Short name T656
Test name
Test status
Simulation time 30911454 ps
CPU time 0.61 seconds
Started Jul 26 06:48:41 PM PDT 24
Finished Jul 26 06:48:42 PM PDT 24
Peak memory 195536 kb
Host smart-a636e70e-3f49-4b42-8058-7b98fdbf2fe3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610722843 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_intr_test.610722843
Directory /workspace/6.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.1916515946
Short name T733
Test name
Test status
Simulation time 73442029 ps
CPU time 0.81 seconds
Started Jul 26 06:48:42 PM PDT 24
Finished Jul 26 06:48:43 PM PDT 24
Peak memory 195672 kb
Host smart-d2c46c80-3c7d-4621-805b-3659cbbb8fb4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916515946 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sa
me_csr_outstanding.1916515946
Directory /workspace/6.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_tl_errors.345091939
Short name T700
Test name
Test status
Simulation time 44157186 ps
CPU time 1.11 seconds
Started Jul 26 06:48:43 PM PDT 24
Finished Jul 26 06:48:44 PM PDT 24
Peak memory 197712 kb
Host smart-7731b43c-13cf-4635-95dc-7fa701796851
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345091939 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_errors.345091939
Directory /workspace/6.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.1513145767
Short name T646
Test name
Test status
Simulation time 255297385 ps
CPU time 1.65 seconds
Started Jul 26 06:48:41 PM PDT 24
Finished Jul 26 06:48:42 PM PDT 24
Peak memory 200964 kb
Host smart-0a43ede1-4cb2-476a-947f-cf9a11b40964
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513145767 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_intg_err
.1513145767
Directory /workspace/6.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.1980962376
Short name T652
Test name
Test status
Simulation time 72857765 ps
CPU time 0.76 seconds
Started Jul 26 06:48:45 PM PDT 24
Finished Jul 26 06:48:46 PM PDT 24
Peak memory 195776 kb
Host smart-692afe6b-22e6-41d7-b0b5-28c8f3fac479
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980962376 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.pwrmgr_csr_mem_rw_with_rand_reset.1980962376
Directory /workspace/7.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_csr_rw.1164433779
Short name T630
Test name
Test status
Simulation time 55761272 ps
CPU time 0.66 seconds
Started Jul 26 06:48:40 PM PDT 24
Finished Jul 26 06:48:41 PM PDT 24
Peak memory 197808 kb
Host smart-8646a989-5327-4692-99c7-9fdda3ddc827
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164433779 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_csr_rw.1164433779
Directory /workspace/7.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_intr_test.260043638
Short name T686
Test name
Test status
Simulation time 22355704 ps
CPU time 0.62 seconds
Started Jul 26 06:48:43 PM PDT 24
Finished Jul 26 06:48:44 PM PDT 24
Peak memory 195548 kb
Host smart-5ad689f7-b745-45b5-bc85-c455e786fa06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260043638 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_intr_test.260043638
Directory /workspace/7.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.457631193
Short name T71
Test name
Test status
Simulation time 147791569 ps
CPU time 0.89 seconds
Started Jul 26 06:48:47 PM PDT 24
Finished Jul 26 06:48:48 PM PDT 24
Peak memory 195696 kb
Host smart-12f2d133-0b62-480f-9b95-d2fc49c2f8ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457631193 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sam
e_csr_outstanding.457631193
Directory /workspace/7.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_tl_errors.92357220
Short name T681
Test name
Test status
Simulation time 26643336 ps
CPU time 1.11 seconds
Started Jul 26 06:48:41 PM PDT 24
Finished Jul 26 06:48:42 PM PDT 24
Peak memory 196916 kb
Host smart-e405bfbc-3218-4832-9dfe-3fe918e8f2f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92357220 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_errors.92357220
Directory /workspace/7.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.1989344104
Short name T146
Test name
Test status
Simulation time 321304944 ps
CPU time 1.62 seconds
Started Jul 26 06:48:42 PM PDT 24
Finished Jul 26 06:48:43 PM PDT 24
Peak memory 201236 kb
Host smart-49633664-cd41-4177-9e39-a72c3320e78f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989344104 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_intg_err
.1989344104
Directory /workspace/7.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.3490594278
Short name T683
Test name
Test status
Simulation time 55438923 ps
CPU time 0.95 seconds
Started Jul 26 06:49:08 PM PDT 24
Finished Jul 26 06:49:10 PM PDT 24
Peak memory 196760 kb
Host smart-4a6f0dd1-a2fc-414e-8f4c-71ef9cd4170f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490594278 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.pwrmgr_csr_mem_rw_with_rand_reset.3490594278
Directory /workspace/8.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_csr_rw.1409581294
Short name T687
Test name
Test status
Simulation time 18522829 ps
CPU time 0.63 seconds
Started Jul 26 06:49:09 PM PDT 24
Finished Jul 26 06:49:10 PM PDT 24
Peak memory 195620 kb
Host smart-271a0b96-ef22-4972-af61-6021a0585760
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409581294 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_csr_rw.1409581294
Directory /workspace/8.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_intr_test.2678237774
Short name T729
Test name
Test status
Simulation time 19172009 ps
CPU time 0.63 seconds
Started Jul 26 06:49:10 PM PDT 24
Finished Jul 26 06:49:10 PM PDT 24
Peak memory 195512 kb
Host smart-a0e6e1fa-ca1e-4c18-bb7a-772de6e81eeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678237774 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_intr_test.2678237774
Directory /workspace/8.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.4026020603
Short name T705
Test name
Test status
Simulation time 110041595 ps
CPU time 0.89 seconds
Started Jul 26 06:49:10 PM PDT 24
Finished Jul 26 06:49:11 PM PDT 24
Peak memory 199016 kb
Host smart-7d22e1ec-16db-409a-b31c-78e77aa72ed0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026020603 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sa
me_csr_outstanding.4026020603
Directory /workspace/8.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_tl_errors.2847335241
Short name T727
Test name
Test status
Simulation time 122286386 ps
CPU time 1.58 seconds
Started Jul 26 06:48:43 PM PDT 24
Finished Jul 26 06:48:45 PM PDT 24
Peak memory 196912 kb
Host smart-d2c8d4ca-fbd4-4695-a1a8-39bdacd5fb48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847335241 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_errors.2847335241
Directory /workspace/8.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.3942472053
Short name T674
Test name
Test status
Simulation time 137036564 ps
CPU time 1.09 seconds
Started Jul 26 06:49:10 PM PDT 24
Finished Jul 26 06:49:11 PM PDT 24
Peak memory 200976 kb
Host smart-570c35de-1a9b-43f7-a7a5-2de66cef2c27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942472053 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_intg_err
.3942472053
Directory /workspace/8.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.900215335
Short name T131
Test name
Test status
Simulation time 79872309 ps
CPU time 0.95 seconds
Started Jul 26 06:49:12 PM PDT 24
Finished Jul 26 06:49:13 PM PDT 24
Peak memory 196664 kb
Host smart-90c3b226-580f-4936-a569-e1f0439b430c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900215335 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.pwrmgr_csr_mem_rw_with_rand_reset.900215335
Directory /workspace/9.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_csr_rw.2474077610
Short name T113
Test name
Test status
Simulation time 22108492 ps
CPU time 0.66 seconds
Started Jul 26 06:49:09 PM PDT 24
Finished Jul 26 06:49:09 PM PDT 24
Peak memory 197752 kb
Host smart-f169f91c-9a34-44ab-99d5-6f85532e0817
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474077610 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_csr_rw.2474077610
Directory /workspace/9.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_intr_test.3089880276
Short name T670
Test name
Test status
Simulation time 47860813 ps
CPU time 0.58 seconds
Started Jul 26 06:49:09 PM PDT 24
Finished Jul 26 06:49:10 PM PDT 24
Peak memory 195568 kb
Host smart-f547d200-12b8-4e55-9ee8-d1f3170cc06b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089880276 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_intr_test.3089880276
Directory /workspace/9.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.2873114574
Short name T642
Test name
Test status
Simulation time 109885080 ps
CPU time 0.83 seconds
Started Jul 26 06:49:13 PM PDT 24
Finished Jul 26 06:49:14 PM PDT 24
Peak memory 198728 kb
Host smart-f45e9831-0f80-4041-9c60-be819b7af412
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873114574 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sa
me_csr_outstanding.2873114574
Directory /workspace/9.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_tl_errors.31255236
Short name T696
Test name
Test status
Simulation time 905916317 ps
CPU time 2.21 seconds
Started Jul 26 06:49:08 PM PDT 24
Finished Jul 26 06:49:11 PM PDT 24
Peak memory 196872 kb
Host smart-ca9f48d0-3b77-48f4-a372-e6a4e2ebad8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31255236 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_errors.31255236
Directory /workspace/9.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.3711310758
Short name T85
Test name
Test status
Simulation time 253262062 ps
CPU time 1.56 seconds
Started Jul 26 06:49:13 PM PDT 24
Finished Jul 26 06:49:15 PM PDT 24
Peak memory 201176 kb
Host smart-ad959465-51ef-4af9-8d30-92aacaf198bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711310758 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_intg_err
.3711310758
Directory /workspace/9.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.pwrmgr_aborted_low_power.540788708
Short name T342
Test name
Test status
Simulation time 94686725 ps
CPU time 0.79 seconds
Started Jul 26 06:57:19 PM PDT 24
Finished Jul 26 06:57:20 PM PDT 24
Peak memory 200136 kb
Host smart-f91e905a-df98-4ad1-9a63-7cfb748cfea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540788708 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_aborted_low_power.540788708
Directory /workspace/0.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/0.pwrmgr_disable_rom_integrity_check.1998735745
Short name T393
Test name
Test status
Simulation time 85871559 ps
CPU time 0.66 seconds
Started Jul 26 06:57:29 PM PDT 24
Finished Jul 26 06:57:30 PM PDT 24
Peak memory 198492 kb
Host smart-fee2621b-ab49-43f8-a8ce-7e7a0496b646
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998735745 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_disa
ble_rom_integrity_check.1998735745
Directory /workspace/0.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/0.pwrmgr_esc_clk_rst_malfunc.2552080992
Short name T275
Test name
Test status
Simulation time 33374613 ps
CPU time 0.62 seconds
Started Jul 26 06:57:21 PM PDT 24
Finished Jul 26 06:57:22 PM PDT 24
Peak memory 197328 kb
Host smart-7dbf0a51-4e47-4a50-b530-6decccb46d38
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552080992 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_esc_clk_rst_
malfunc.2552080992
Directory /workspace/0.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/0.pwrmgr_escalation_timeout.3292570153
Short name T134
Test name
Test status
Simulation time 160310162 ps
CPU time 0.94 seconds
Started Jul 26 06:57:27 PM PDT 24
Finished Jul 26 06:57:28 PM PDT 24
Peak memory 198108 kb
Host smart-b2c6b74c-9dff-460e-88b6-6f8899cc0b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292570153 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_escalation_timeout.3292570153
Directory /workspace/0.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/0.pwrmgr_global_esc.2276996919
Short name T623
Test name
Test status
Simulation time 20621380 ps
CPU time 0.59 seconds
Started Jul 26 06:57:23 PM PDT 24
Finished Jul 26 06:57:24 PM PDT 24
Peak memory 198464 kb
Host smart-2b4ad9fb-5fed-4030-958e-c5eeac6ab6d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276996919 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_global_esc.2276996919
Directory /workspace/0.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/0.pwrmgr_lowpower_invalid.2969357707
Short name T182
Test name
Test status
Simulation time 70125565 ps
CPU time 0.67 seconds
Started Jul 26 06:57:29 PM PDT 24
Finished Jul 26 06:57:30 PM PDT 24
Peak memory 201464 kb
Host smart-2623c4ce-9251-4312-9862-70b34a6272eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969357707 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_lowpower_invali
d.2969357707
Directory /workspace/0.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/0.pwrmgr_reset.146647170
Short name T489
Test name
Test status
Simulation time 94008114 ps
CPU time 0.64 seconds
Started Jul 26 06:57:23 PM PDT 24
Finished Jul 26 06:57:24 PM PDT 24
Peak memory 198372 kb
Host smart-c3b79cba-9af5-45fc-9062-75a58acab249
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146647170 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset.146647170
Directory /workspace/0.pwrmgr_reset/latest

Test location /workspace/coverage/default/0.pwrmgr_reset_invalid.3691772603
Short name T283
Test name
Test status
Simulation time 100209663 ps
CPU time 0.96 seconds
Started Jul 26 06:57:28 PM PDT 24
Finished Jul 26 06:57:29 PM PDT 24
Peak memory 209560 kb
Host smart-248694aa-51b9-48b3-bb4f-1fda1bfcfcbb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691772603 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset_invalid.3691772603
Directory /workspace/0.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm_rstmgr_intersig_mubi.2267932892
Short name T374
Test name
Test status
Simulation time 124787283 ps
CPU time 0.68 seconds
Started Jul 26 06:57:23 PM PDT 24
Finished Jul 26 06:57:24 PM PDT 24
Peak memory 198324 kb
Host smart-a10f45f2-a017-42c0-bcd5-eadb7b41b257
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267932892 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2267932892
Directory /workspace/0.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/0.pwrmgr_smoke.866994835
Short name T356
Test name
Test status
Simulation time 42783886 ps
CPU time 0.63 seconds
Started Jul 26 06:57:23 PM PDT 24
Finished Jul 26 06:57:24 PM PDT 24
Peak memory 198556 kb
Host smart-885f8995-d7c4-4ac5-a300-4f650f6e6f75
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866994835 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_smoke.866994835
Directory /workspace/0.pwrmgr_smoke/latest

Test location /workspace/coverage/default/1.pwrmgr_aborted_low_power.3634729067
Short name T533
Test name
Test status
Simulation time 81909079 ps
CPU time 0.85 seconds
Started Jul 26 06:57:29 PM PDT 24
Finished Jul 26 06:57:30 PM PDT 24
Peak memory 200116 kb
Host smart-f4d09355-3d2a-4339-b7cb-647dbcafd68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634729067 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_aborted_low_power.3634729067
Directory /workspace/1.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/1.pwrmgr_esc_clk_rst_malfunc.1316043722
Short name T336
Test name
Test status
Simulation time 38997464 ps
CPU time 0.59 seconds
Started Jul 26 06:57:39 PM PDT 24
Finished Jul 26 06:57:39 PM PDT 24
Peak memory 198008 kb
Host smart-e874819b-cb63-474a-b73c-e9d473d1ff64
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316043722 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_esc_clk_rst_
malfunc.1316043722
Directory /workspace/1.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/1.pwrmgr_glitch.1989772601
Short name T493
Test name
Test status
Simulation time 69105348 ps
CPU time 0.6 seconds
Started Jul 26 06:57:38 PM PDT 24
Finished Jul 26 06:57:39 PM PDT 24
Peak memory 197336 kb
Host smart-d65d1664-4277-4dc6-9e38-606374c8ec4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989772601 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_glitch.1989772601
Directory /workspace/1.pwrmgr_glitch/latest

Test location /workspace/coverage/default/1.pwrmgr_global_esc.447375371
Short name T310
Test name
Test status
Simulation time 35223468 ps
CPU time 0.63 seconds
Started Jul 26 06:57:37 PM PDT 24
Finished Jul 26 06:57:38 PM PDT 24
Peak memory 198220 kb
Host smart-18b0f1ce-dbc7-454a-9d5a-16b84231fba2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447375371 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_global_esc.447375371
Directory /workspace/1.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/1.pwrmgr_lowpower_wakeup_race.1736768746
Short name T201
Test name
Test status
Simulation time 61058985 ps
CPU time 0.77 seconds
Started Jul 26 06:57:28 PM PDT 24
Finished Jul 26 06:57:29 PM PDT 24
Peak memory 198432 kb
Host smart-6effdbd6-bd1d-4c36-85cb-39984989ad25
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736768746 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_lowpower_wa
keup_race.1736768746
Directory /workspace/1.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/1.pwrmgr_reset.2778367115
Short name T483
Test name
Test status
Simulation time 86085915 ps
CPU time 0.77 seconds
Started Jul 26 06:57:29 PM PDT 24
Finished Jul 26 06:57:30 PM PDT 24
Peak memory 199148 kb
Host smart-84fe5652-2667-4a46-8dcd-0e6f15508d7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778367115 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset.2778367115
Directory /workspace/1.pwrmgr_reset/latest

Test location /workspace/coverage/default/1.pwrmgr_reset_invalid.4064005698
Short name T280
Test name
Test status
Simulation time 102563802 ps
CPU time 0.96 seconds
Started Jul 26 06:57:38 PM PDT 24
Finished Jul 26 06:57:40 PM PDT 24
Peak memory 209652 kb
Host smart-ecc37ab6-e6df-41a9-a841-c15e938fe25d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064005698 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset_invalid.4064005698
Directory /workspace/1.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm.1274362234
Short name T19
Test name
Test status
Simulation time 537706461 ps
CPU time 1.09 seconds
Started Jul 26 06:57:36 PM PDT 24
Finished Jul 26 06:57:38 PM PDT 24
Peak memory 216904 kb
Host smart-ab46467f-c44a-47c7-9eb1-12576aad8cf7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274362234 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm.1274362234
Directory /workspace/1.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm_rstmgr_intersig_mubi.4000812904
Short name T311
Test name
Test status
Simulation time 62309829 ps
CPU time 0.76 seconds
Started Jul 26 06:57:27 PM PDT 24
Finished Jul 26 06:57:28 PM PDT 24
Peak memory 198340 kb
Host smart-9cce4340-f51c-411a-9267-9f08c244c908
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000812904 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_rstmgr_intersig_
mubi.4000812904
Directory /workspace/1.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/1.pwrmgr_smoke.2957688576
Short name T215
Test name
Test status
Simulation time 31526181 ps
CPU time 0.7 seconds
Started Jul 26 06:57:28 PM PDT 24
Finished Jul 26 06:57:29 PM PDT 24
Peak memory 199376 kb
Host smart-0ab370c6-1fcf-4f2f-86d6-a8c25a38bf3c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957688576 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_smoke.2957688576
Directory /workspace/1.pwrmgr_smoke/latest

Test location /workspace/coverage/default/10.pwrmgr_aborted_low_power.1476354862
Short name T101
Test name
Test status
Simulation time 34081259 ps
CPU time 1.02 seconds
Started Jul 26 06:58:18 PM PDT 24
Finished Jul 26 06:58:20 PM PDT 24
Peak memory 200976 kb
Host smart-9f415997-a1a6-4e03-8834-26327c1d594b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476354862 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_aborted_low_power.1476354862
Directory /workspace/10.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/10.pwrmgr_disable_rom_integrity_check.2623184660
Short name T139
Test name
Test status
Simulation time 144601677 ps
CPU time 0.64 seconds
Started Jul 26 06:58:26 PM PDT 24
Finished Jul 26 06:58:27 PM PDT 24
Peak memory 199216 kb
Host smart-7b48a874-cadf-4d3a-a501-fc0b2841dc69
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623184660 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_dis
able_rom_integrity_check.2623184660
Directory /workspace/10.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/10.pwrmgr_esc_clk_rst_malfunc.1073778510
Short name T50
Test name
Test status
Simulation time 38676260 ps
CPU time 0.65 seconds
Started Jul 26 06:58:21 PM PDT 24
Finished Jul 26 06:58:21 PM PDT 24
Peak memory 198020 kb
Host smart-959ada06-f439-48d6-997a-c0f0f12722f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073778510 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_esc_clk_rst
_malfunc.1073778510
Directory /workspace/10.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/10.pwrmgr_escalation_timeout.4063805716
Short name T357
Test name
Test status
Simulation time 157553805 ps
CPU time 0.96 seconds
Started Jul 26 06:58:18 PM PDT 24
Finished Jul 26 06:58:19 PM PDT 24
Peak memory 198432 kb
Host smart-31b21c9f-5b9c-4b5f-9961-690c4a1909ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063805716 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_escalation_timeout.4063805716
Directory /workspace/10.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/10.pwrmgr_glitch.1899054777
Short name T212
Test name
Test status
Simulation time 44581545 ps
CPU time 0.62 seconds
Started Jul 26 06:58:28 PM PDT 24
Finished Jul 26 06:58:29 PM PDT 24
Peak memory 197372 kb
Host smart-3e24ab38-d5e3-4b82-8056-b50d60183276
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899054777 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_glitch.1899054777
Directory /workspace/10.pwrmgr_glitch/latest

Test location /workspace/coverage/default/10.pwrmgr_global_esc.496517138
Short name T260
Test name
Test status
Simulation time 43715118 ps
CPU time 0.63 seconds
Started Jul 26 06:58:18 PM PDT 24
Finished Jul 26 06:58:19 PM PDT 24
Peak memory 198436 kb
Host smart-e878c77a-76c6-4bf1-a155-33a8d7e43901
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496517138 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_global_esc.496517138
Directory /workspace/10.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/10.pwrmgr_reset.935959754
Short name T382
Test name
Test status
Simulation time 87067164 ps
CPU time 0.73 seconds
Started Jul 26 06:58:18 PM PDT 24
Finished Jul 26 06:58:19 PM PDT 24
Peak memory 198488 kb
Host smart-67d4db7b-8acd-43cc-b416-245b51726406
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935959754 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset.935959754
Directory /workspace/10.pwrmgr_reset/latest

Test location /workspace/coverage/default/10.pwrmgr_reset_invalid.2072687646
Short name T39
Test name
Test status
Simulation time 194427725 ps
CPU time 0.83 seconds
Started Jul 26 06:58:25 PM PDT 24
Finished Jul 26 06:58:26 PM PDT 24
Peak memory 209592 kb
Host smart-5cc32305-1f5e-405e-81f2-c7d50823df90
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072687646 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset_invalid.2072687646
Directory /workspace/10.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/10.pwrmgr_sec_cm_rstmgr_intersig_mubi.1106140633
Short name T279
Test name
Test status
Simulation time 57646978 ps
CPU time 0.8 seconds
Started Jul 26 06:58:20 PM PDT 24
Finished Jul 26 06:58:21 PM PDT 24
Peak memory 198096 kb
Host smart-61a32b2c-66bf-4d30-b8b5-2064f6e771cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106140633 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1106140633
Directory /workspace/10.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/10.pwrmgr_smoke.100154276
Short name T604
Test name
Test status
Simulation time 71610736 ps
CPU time 0.62 seconds
Started Jul 26 06:58:20 PM PDT 24
Finished Jul 26 06:58:21 PM PDT 24
Peak memory 198428 kb
Host smart-675cc10b-da37-402c-915d-99b16c1f3c39
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100154276 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_smoke.100154276
Directory /workspace/10.pwrmgr_smoke/latest

Test location /workspace/coverage/default/11.pwrmgr_aborted_low_power.2310641490
Short name T99
Test name
Test status
Simulation time 53322010 ps
CPU time 0.75 seconds
Started Jul 26 06:58:28 PM PDT 24
Finished Jul 26 06:58:28 PM PDT 24
Peak memory 200088 kb
Host smart-11730e28-4643-4d13-80f8-1beb044cfd83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310641490 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_aborted_low_power.2310641490
Directory /workspace/11.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/11.pwrmgr_esc_clk_rst_malfunc.2694517958
Short name T440
Test name
Test status
Simulation time 31197654 ps
CPU time 0.64 seconds
Started Jul 26 06:58:25 PM PDT 24
Finished Jul 26 06:58:26 PM PDT 24
Peak memory 198048 kb
Host smart-4fb7e8b8-7c72-478d-aa9b-fc955133fa4d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694517958 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_esc_clk_rst
_malfunc.2694517958
Directory /workspace/11.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/11.pwrmgr_escalation_timeout.469522211
Short name T453
Test name
Test status
Simulation time 1164017592 ps
CPU time 0.99 seconds
Started Jul 26 06:58:26 PM PDT 24
Finished Jul 26 06:58:27 PM PDT 24
Peak memory 198460 kb
Host smart-acb74974-507a-4153-8b9f-0aa6d2ac4777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469522211 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_escalation_timeout.469522211
Directory /workspace/11.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/11.pwrmgr_glitch.1930592964
Short name T500
Test name
Test status
Simulation time 57899057 ps
CPU time 0.7 seconds
Started Jul 26 06:58:27 PM PDT 24
Finished Jul 26 06:58:28 PM PDT 24
Peak memory 197988 kb
Host smart-ca3fbee2-4d6b-4ca3-b85a-d4310ec90c7e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930592964 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_glitch.1930592964
Directory /workspace/11.pwrmgr_glitch/latest

Test location /workspace/coverage/default/11.pwrmgr_global_esc.2544951596
Short name T269
Test name
Test status
Simulation time 44951131 ps
CPU time 0.61 seconds
Started Jul 26 06:58:26 PM PDT 24
Finished Jul 26 06:58:27 PM PDT 24
Peak memory 198500 kb
Host smart-41f1840f-bba2-4d1a-add2-41a8ae7ba5b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544951596 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_global_esc.2544951596
Directory /workspace/11.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/11.pwrmgr_reset.3632075661
Short name T350
Test name
Test status
Simulation time 72016599 ps
CPU time 0.86 seconds
Started Jul 26 06:58:24 PM PDT 24
Finished Jul 26 06:58:25 PM PDT 24
Peak memory 199180 kb
Host smart-42f26ebc-3f24-4d0a-b806-a0d17218f22a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632075661 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset.3632075661
Directory /workspace/11.pwrmgr_reset/latest

Test location /workspace/coverage/default/11.pwrmgr_reset_invalid.1008976727
Short name T552
Test name
Test status
Simulation time 99453654 ps
CPU time 1.02 seconds
Started Jul 26 06:58:25 PM PDT 24
Finished Jul 26 06:58:26 PM PDT 24
Peak memory 209496 kb
Host smart-684b984a-ca45-4d0c-9c9a-a08d8e22124a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008976727 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset_invalid.1008976727
Directory /workspace/11.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/11.pwrmgr_sec_cm_rstmgr_intersig_mubi.1062733902
Short name T518
Test name
Test status
Simulation time 118733919 ps
CPU time 0.77 seconds
Started Jul 26 06:58:23 PM PDT 24
Finished Jul 26 06:58:23 PM PDT 24
Peak memory 198220 kb
Host smart-921079ad-b66b-4380-a650-74e339edafbd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062733902 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1062733902
Directory /workspace/11.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/11.pwrmgr_smoke.1369310339
Short name T465
Test name
Test status
Simulation time 33771582 ps
CPU time 0.67 seconds
Started Jul 26 06:58:27 PM PDT 24
Finished Jul 26 06:58:28 PM PDT 24
Peak memory 199508 kb
Host smart-ab8ac2d0-da0f-4b91-87da-0e45625b7b06
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369310339 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_smoke.1369310339
Directory /workspace/11.pwrmgr_smoke/latest

Test location /workspace/coverage/default/12.pwrmgr_aborted_low_power.283115516
Short name T545
Test name
Test status
Simulation time 20711223 ps
CPU time 0.73 seconds
Started Jul 26 06:58:28 PM PDT 24
Finished Jul 26 06:58:29 PM PDT 24
Peak memory 199232 kb
Host smart-6bf1288c-debb-4620-83b6-c60b8da23185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283115516 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_aborted_low_power.283115516
Directory /workspace/12.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/12.pwrmgr_disable_rom_integrity_check.414948047
Short name T323
Test name
Test status
Simulation time 63339791 ps
CPU time 0.78 seconds
Started Jul 26 06:58:36 PM PDT 24
Finished Jul 26 06:58:37 PM PDT 24
Peak memory 199100 kb
Host smart-dd62181b-681e-4ed8-b28f-acf03bc92288
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414948047 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_disa
ble_rom_integrity_check.414948047
Directory /workspace/12.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/12.pwrmgr_esc_clk_rst_malfunc.3507681620
Short name T338
Test name
Test status
Simulation time 30428564 ps
CPU time 0.64 seconds
Started Jul 26 06:58:26 PM PDT 24
Finished Jul 26 06:58:27 PM PDT 24
Peak memory 197364 kb
Host smart-64f1eb8e-3184-4732-93dd-2e96d48b97b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507681620 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_esc_clk_rst
_malfunc.3507681620
Directory /workspace/12.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/12.pwrmgr_escalation_timeout.2782948337
Short name T257
Test name
Test status
Simulation time 160743616 ps
CPU time 0.94 seconds
Started Jul 26 06:58:35 PM PDT 24
Finished Jul 26 06:58:36 PM PDT 24
Peak memory 198408 kb
Host smart-717d3ae5-c80f-4b15-bdb6-6a3d79317029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782948337 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_escalation_timeout.2782948337
Directory /workspace/12.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/12.pwrmgr_glitch.3070926138
Short name T539
Test name
Test status
Simulation time 47119269 ps
CPU time 0.67 seconds
Started Jul 26 06:58:34 PM PDT 24
Finished Jul 26 06:58:35 PM PDT 24
Peak memory 198092 kb
Host smart-502a582d-128e-40e2-912d-d352dc5337f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070926138 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_glitch.3070926138
Directory /workspace/12.pwrmgr_glitch/latest

Test location /workspace/coverage/default/12.pwrmgr_global_esc.444457008
Short name T503
Test name
Test status
Simulation time 38909031 ps
CPU time 0.67 seconds
Started Jul 26 06:58:34 PM PDT 24
Finished Jul 26 06:58:35 PM PDT 24
Peak memory 198220 kb
Host smart-caa70ceb-05e0-453a-b0b1-c6c6ff8e8689
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444457008 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_global_esc.444457008
Directory /workspace/12.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/12.pwrmgr_lowpower_invalid.2601832918
Short name T166
Test name
Test status
Simulation time 43727924 ps
CPU time 0.72 seconds
Started Jul 26 06:58:32 PM PDT 24
Finished Jul 26 06:58:33 PM PDT 24
Peak memory 201440 kb
Host smart-a13c5f34-a669-452a-a83f-15158cddc572
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601832918 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_lowpower_inval
id.2601832918
Directory /workspace/12.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/12.pwrmgr_reset.2900664108
Short name T383
Test name
Test status
Simulation time 62348488 ps
CPU time 0.83 seconds
Started Jul 26 06:58:26 PM PDT 24
Finished Jul 26 06:58:27 PM PDT 24
Peak memory 198484 kb
Host smart-e7890461-f40e-4355-b233-dc1a99b1de89
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900664108 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset.2900664108
Directory /workspace/12.pwrmgr_reset/latest

Test location /workspace/coverage/default/12.pwrmgr_reset_invalid.2577357523
Short name T232
Test name
Test status
Simulation time 120314803 ps
CPU time 0.83 seconds
Started Jul 26 06:58:32 PM PDT 24
Finished Jul 26 06:58:33 PM PDT 24
Peak memory 209568 kb
Host smart-f45da57e-6407-4ea4-8cdf-aeee3ec5490c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577357523 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset_invalid.2577357523
Directory /workspace/12.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/12.pwrmgr_sec_cm_rstmgr_intersig_mubi.1646098701
Short name T329
Test name
Test status
Simulation time 72350572 ps
CPU time 0.87 seconds
Started Jul 26 06:58:26 PM PDT 24
Finished Jul 26 06:58:27 PM PDT 24
Peak memory 199356 kb
Host smart-77f94ce7-9162-4615-925f-65d951d2cf2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646098701 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1646098701
Directory /workspace/12.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/12.pwrmgr_smoke.661467902
Short name T333
Test name
Test status
Simulation time 31510280 ps
CPU time 0.69 seconds
Started Jul 26 06:58:27 PM PDT 24
Finished Jul 26 06:58:28 PM PDT 24
Peak memory 199436 kb
Host smart-2e2c591b-590b-48d4-88ee-139ab2dad8f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661467902 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_smoke.661467902
Directory /workspace/12.pwrmgr_smoke/latest

Test location /workspace/coverage/default/13.pwrmgr_aborted_low_power.648910113
Short name T471
Test name
Test status
Simulation time 28370202 ps
CPU time 0.69 seconds
Started Jul 26 06:58:33 PM PDT 24
Finished Jul 26 06:58:34 PM PDT 24
Peak memory 198600 kb
Host smart-5e48daf6-554d-4ad1-8ed5-d3a7a4cc1c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648910113 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_aborted_low_power.648910113
Directory /workspace/13.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/13.pwrmgr_esc_clk_rst_malfunc.680786657
Short name T220
Test name
Test status
Simulation time 38766115 ps
CPU time 0.57 seconds
Started Jul 26 06:58:33 PM PDT 24
Finished Jul 26 06:58:33 PM PDT 24
Peak memory 197276 kb
Host smart-67090666-f12c-4bb5-8015-902b3ea8b9fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680786657 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_esc_clk_rst_
malfunc.680786657
Directory /workspace/13.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/13.pwrmgr_escalation_timeout.4288499675
Short name T252
Test name
Test status
Simulation time 660155308 ps
CPU time 0.95 seconds
Started Jul 26 06:58:33 PM PDT 24
Finished Jul 26 06:58:34 PM PDT 24
Peak memory 198436 kb
Host smart-5d5a4684-f663-4ad8-9443-4f564fcac655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288499675 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_escalation_timeout.4288499675
Directory /workspace/13.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/13.pwrmgr_glitch.2976421510
Short name T608
Test name
Test status
Simulation time 29233253 ps
CPU time 0.64 seconds
Started Jul 26 06:58:36 PM PDT 24
Finished Jul 26 06:58:37 PM PDT 24
Peak memory 197436 kb
Host smart-d1cd0f2e-f7fe-42b6-9d0c-825fadf1c06f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976421510 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_glitch.2976421510
Directory /workspace/13.pwrmgr_glitch/latest

Test location /workspace/coverage/default/13.pwrmgr_global_esc.2391489358
Short name T457
Test name
Test status
Simulation time 45840381 ps
CPU time 0.59 seconds
Started Jul 26 06:58:33 PM PDT 24
Finished Jul 26 06:58:33 PM PDT 24
Peak memory 198152 kb
Host smart-7c963915-ce16-41a8-89df-10f08d3f0d35
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391489358 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_global_esc.2391489358
Directory /workspace/13.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/13.pwrmgr_lowpower_invalid.280558072
Short name T61
Test name
Test status
Simulation time 44110896 ps
CPU time 0.74 seconds
Started Jul 26 06:58:33 PM PDT 24
Finished Jul 26 06:58:34 PM PDT 24
Peak memory 201468 kb
Host smart-7cc456aa-824d-45f8-af57-b6c7e2cf71e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280558072 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_lowpower_invali
d.280558072
Directory /workspace/13.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/13.pwrmgr_reset.3678576869
Short name T430
Test name
Test status
Simulation time 36621029 ps
CPU time 0.67 seconds
Started Jul 26 06:58:32 PM PDT 24
Finished Jul 26 06:58:32 PM PDT 24
Peak memory 199220 kb
Host smart-1400b09a-cfee-43dd-996c-c94acf657c69
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678576869 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset.3678576869
Directory /workspace/13.pwrmgr_reset/latest

Test location /workspace/coverage/default/13.pwrmgr_reset_invalid.1691446393
Short name T446
Test name
Test status
Simulation time 151698520 ps
CPU time 0.75 seconds
Started Jul 26 06:58:35 PM PDT 24
Finished Jul 26 06:58:36 PM PDT 24
Peak memory 209480 kb
Host smart-8a2d36cf-19d9-4ed3-8d55-9ff52036f9f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691446393 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset_invalid.1691446393
Directory /workspace/13.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/13.pwrmgr_sec_cm_rstmgr_intersig_mubi.2719347748
Short name T592
Test name
Test status
Simulation time 65070045 ps
CPU time 0.95 seconds
Started Jul 26 06:58:37 PM PDT 24
Finished Jul 26 06:58:39 PM PDT 24
Peak memory 199008 kb
Host smart-f98c7466-1063-4c51-86d9-942777a494eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719347748 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2719347748
Directory /workspace/13.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/13.pwrmgr_smoke.3304020092
Short name T91
Test name
Test status
Simulation time 60398137 ps
CPU time 0.63 seconds
Started Jul 26 06:58:32 PM PDT 24
Finished Jul 26 06:58:33 PM PDT 24
Peak memory 198616 kb
Host smart-3942d310-8d59-4633-a289-f72bcaefebd5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304020092 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_smoke.3304020092
Directory /workspace/13.pwrmgr_smoke/latest

Test location /workspace/coverage/default/14.pwrmgr_disable_rom_integrity_check.3870981292
Short name T46
Test name
Test status
Simulation time 50208496 ps
CPU time 0.74 seconds
Started Jul 26 06:58:43 PM PDT 24
Finished Jul 26 06:58:44 PM PDT 24
Peak memory 198576 kb
Host smart-f673a876-07bb-47e9-8faf-6e62300c5d0a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870981292 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_dis
able_rom_integrity_check.3870981292
Directory /workspace/14.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/14.pwrmgr_esc_clk_rst_malfunc.2222193565
Short name T454
Test name
Test status
Simulation time 38376692 ps
CPU time 0.6 seconds
Started Jul 26 06:58:42 PM PDT 24
Finished Jul 26 06:58:43 PM PDT 24
Peak memory 198072 kb
Host smart-c74a4695-09f6-4cdf-8c17-7c9b6b280e86
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222193565 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_esc_clk_rst
_malfunc.2222193565
Directory /workspace/14.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/14.pwrmgr_escalation_timeout.1491199778
Short name T444
Test name
Test status
Simulation time 309761850 ps
CPU time 0.98 seconds
Started Jul 26 06:58:42 PM PDT 24
Finished Jul 26 06:58:43 PM PDT 24
Peak memory 198248 kb
Host smart-e909c8e2-92be-4f2f-9632-ef5ee7b4be45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491199778 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_escalation_timeout.1491199778
Directory /workspace/14.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/14.pwrmgr_glitch.2825536888
Short name T266
Test name
Test status
Simulation time 58493937 ps
CPU time 0.61 seconds
Started Jul 26 06:58:42 PM PDT 24
Finished Jul 26 06:58:43 PM PDT 24
Peak memory 198112 kb
Host smart-81101cee-6279-4b3b-9f76-306c3922d1db
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825536888 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_glitch.2825536888
Directory /workspace/14.pwrmgr_glitch/latest

Test location /workspace/coverage/default/14.pwrmgr_global_esc.4145310317
Short name T558
Test name
Test status
Simulation time 91476225 ps
CPU time 0.6 seconds
Started Jul 26 06:58:43 PM PDT 24
Finished Jul 26 06:58:44 PM PDT 24
Peak memory 198544 kb
Host smart-20944225-5d03-487f-9308-061b598ebf0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145310317 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_global_esc.4145310317
Directory /workspace/14.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/14.pwrmgr_lowpower_invalid.3127358883
Short name T89
Test name
Test status
Simulation time 48333001 ps
CPU time 0.78 seconds
Started Jul 26 06:58:43 PM PDT 24
Finished Jul 26 06:58:44 PM PDT 24
Peak memory 201416 kb
Host smart-b1fe0586-4b23-4a70-891d-dd8776d2efa8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127358883 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_lowpower_inval
id.3127358883
Directory /workspace/14.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/14.pwrmgr_reset.3222175131
Short name T371
Test name
Test status
Simulation time 41168538 ps
CPU time 0.75 seconds
Started Jul 26 06:58:35 PM PDT 24
Finished Jul 26 06:58:36 PM PDT 24
Peak memory 199132 kb
Host smart-2c61fdf2-1716-43a7-b68a-25f74a2234f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222175131 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset.3222175131
Directory /workspace/14.pwrmgr_reset/latest

Test location /workspace/coverage/default/14.pwrmgr_reset_invalid.601316520
Short name T511
Test name
Test status
Simulation time 118421089 ps
CPU time 0.96 seconds
Started Jul 26 06:58:41 PM PDT 24
Finished Jul 26 06:58:42 PM PDT 24
Peak memory 209628 kb
Host smart-13428a2b-a5f6-4f01-b7fe-4e4d76d5e87f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601316520 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset_invalid.601316520
Directory /workspace/14.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/14.pwrmgr_sec_cm_rstmgr_intersig_mubi.2243297339
Short name T268
Test name
Test status
Simulation time 107754621 ps
CPU time 0.79 seconds
Started Jul 26 06:58:42 PM PDT 24
Finished Jul 26 06:58:43 PM PDT 24
Peak memory 198160 kb
Host smart-be13c312-4f76-42f6-8c39-0cfc8fd1a3e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243297339 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2243297339
Directory /workspace/14.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/14.pwrmgr_smoke.2132908522
Short name T293
Test name
Test status
Simulation time 38765412 ps
CPU time 0.64 seconds
Started Jul 26 06:58:34 PM PDT 24
Finished Jul 26 06:58:35 PM PDT 24
Peak memory 198532 kb
Host smart-2588f652-4fa2-4b4a-91d8-643a49b407d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132908522 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_smoke.2132908522
Directory /workspace/14.pwrmgr_smoke/latest

Test location /workspace/coverage/default/15.pwrmgr_aborted_low_power.1746808892
Short name T16
Test name
Test status
Simulation time 47361987 ps
CPU time 0.68 seconds
Started Jul 26 06:58:41 PM PDT 24
Finished Jul 26 06:58:42 PM PDT 24
Peak memory 198628 kb
Host smart-4cabd82f-0f9e-4f1f-8ff3-9691ebc8fbe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746808892 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_aborted_low_power.1746808892
Directory /workspace/15.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/15.pwrmgr_disable_rom_integrity_check.2478165823
Short name T593
Test name
Test status
Simulation time 55269150 ps
CPU time 0.66 seconds
Started Jul 26 06:58:48 PM PDT 24
Finished Jul 26 06:58:49 PM PDT 24
Peak memory 199332 kb
Host smart-2a832108-f679-4020-8587-9b1f4eea7095
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478165823 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_dis
able_rom_integrity_check.2478165823
Directory /workspace/15.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/15.pwrmgr_esc_clk_rst_malfunc.915240790
Short name T412
Test name
Test status
Simulation time 31675357 ps
CPU time 0.6 seconds
Started Jul 26 06:58:43 PM PDT 24
Finished Jul 26 06:58:44 PM PDT 24
Peak memory 198064 kb
Host smart-db630d79-1d77-485a-b1fb-8b31b5aa8045
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915240790 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_esc_clk_rst_
malfunc.915240790
Directory /workspace/15.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/15.pwrmgr_escalation_timeout.2287641606
Short name T433
Test name
Test status
Simulation time 157977112 ps
CPU time 0.92 seconds
Started Jul 26 06:58:48 PM PDT 24
Finished Jul 26 06:58:50 PM PDT 24
Peak memory 198124 kb
Host smart-ccd1963d-cd8b-4b20-965e-063288a0ac04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287641606 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_escalation_timeout.2287641606
Directory /workspace/15.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/15.pwrmgr_glitch.3412360247
Short name T368
Test name
Test status
Simulation time 89031954 ps
CPU time 0.62 seconds
Started Jul 26 06:58:49 PM PDT 24
Finished Jul 26 06:58:50 PM PDT 24
Peak memory 198112 kb
Host smart-ab0de0fc-40dc-4c8b-be91-73ae9f11d3fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412360247 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_glitch.3412360247
Directory /workspace/15.pwrmgr_glitch/latest

Test location /workspace/coverage/default/15.pwrmgr_global_esc.1376511673
Short name T334
Test name
Test status
Simulation time 42750796 ps
CPU time 0.64 seconds
Started Jul 26 06:58:42 PM PDT 24
Finished Jul 26 06:58:43 PM PDT 24
Peak memory 198100 kb
Host smart-f333e09b-928b-4d0b-a072-681a65dcad0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376511673 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_global_esc.1376511673
Directory /workspace/15.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/15.pwrmgr_lowpower_invalid.3632961739
Short name T588
Test name
Test status
Simulation time 43938220 ps
CPU time 0.74 seconds
Started Jul 26 06:58:56 PM PDT 24
Finished Jul 26 06:58:57 PM PDT 24
Peak memory 201264 kb
Host smart-b1610dad-5857-4703-9497-49e739a65312
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632961739 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_lowpower_inval
id.3632961739
Directory /workspace/15.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/15.pwrmgr_reset.3205785711
Short name T486
Test name
Test status
Simulation time 111368368 ps
CPU time 0.75 seconds
Started Jul 26 06:58:43 PM PDT 24
Finished Jul 26 06:58:44 PM PDT 24
Peak memory 198544 kb
Host smart-f7c2e11c-1413-4507-a45f-14ed2980f256
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205785711 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset.3205785711
Directory /workspace/15.pwrmgr_reset/latest

Test location /workspace/coverage/default/15.pwrmgr_reset_invalid.2636638352
Short name T355
Test name
Test status
Simulation time 123188987 ps
CPU time 0.87 seconds
Started Jul 26 06:58:54 PM PDT 24
Finished Jul 26 06:58:55 PM PDT 24
Peak memory 209588 kb
Host smart-c15feea5-5351-4103-99d9-f21bb4b264c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636638352 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset_invalid.2636638352
Directory /workspace/15.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/15.pwrmgr_sec_cm_rstmgr_intersig_mubi.310032748
Short name T273
Test name
Test status
Simulation time 69158773 ps
CPU time 0.94 seconds
Started Jul 26 06:58:44 PM PDT 24
Finished Jul 26 06:58:45 PM PDT 24
Peak memory 199188 kb
Host smart-177948b2-b709-477f-891c-9b61ad354f23
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310032748 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_rstmgr_intersig_
mubi.310032748
Directory /workspace/15.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/15.pwrmgr_smoke.4056005741
Short name T322
Test name
Test status
Simulation time 29962896 ps
CPU time 0.68 seconds
Started Jul 26 06:58:42 PM PDT 24
Finished Jul 26 06:58:42 PM PDT 24
Peak memory 199400 kb
Host smart-96663fea-7c80-45c3-8e58-3bcf3b0e4ed4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056005741 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_smoke.4056005741
Directory /workspace/15.pwrmgr_smoke/latest

Test location /workspace/coverage/default/16.pwrmgr_aborted_low_power.1730618163
Short name T597
Test name
Test status
Simulation time 20530354 ps
CPU time 0.64 seconds
Started Jul 26 06:58:56 PM PDT 24
Finished Jul 26 06:58:57 PM PDT 24
Peak memory 198660 kb
Host smart-c19e35d8-17ab-4629-a323-2ad782ad74c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730618163 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_aborted_low_power.1730618163
Directory /workspace/16.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/16.pwrmgr_disable_rom_integrity_check.926637225
Short name T305
Test name
Test status
Simulation time 70021905 ps
CPU time 0.73 seconds
Started Jul 26 06:58:51 PM PDT 24
Finished Jul 26 06:58:52 PM PDT 24
Peak memory 199100 kb
Host smart-50f5bf59-2783-4a55-8b85-e23801b84128
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926637225 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_disa
ble_rom_integrity_check.926637225
Directory /workspace/16.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/16.pwrmgr_esc_clk_rst_malfunc.2818249825
Short name T431
Test name
Test status
Simulation time 44303739 ps
CPU time 0.58 seconds
Started Jul 26 06:58:51 PM PDT 24
Finished Jul 26 06:58:51 PM PDT 24
Peak memory 198044 kb
Host smart-10c50d37-d19a-477d-a19f-42d578d2624f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818249825 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_esc_clk_rst
_malfunc.2818249825
Directory /workspace/16.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/16.pwrmgr_escalation_timeout.4171566706
Short name T401
Test name
Test status
Simulation time 166697425 ps
CPU time 1.04 seconds
Started Jul 26 06:58:51 PM PDT 24
Finished Jul 26 06:58:52 PM PDT 24
Peak memory 198444 kb
Host smart-738b7954-f9e8-4d35-a549-0167543ac9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171566706 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_escalation_timeout.4171566706
Directory /workspace/16.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/16.pwrmgr_glitch.666986336
Short name T264
Test name
Test status
Simulation time 109810424 ps
CPU time 0.6 seconds
Started Jul 26 06:58:50 PM PDT 24
Finished Jul 26 06:58:51 PM PDT 24
Peak memory 197948 kb
Host smart-6096d3f2-7a08-4eba-9182-161a0585fbd6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666986336 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_glitch.666986336
Directory /workspace/16.pwrmgr_glitch/latest

Test location /workspace/coverage/default/16.pwrmgr_global_esc.563881409
Short name T234
Test name
Test status
Simulation time 64291129 ps
CPU time 0.58 seconds
Started Jul 26 06:58:50 PM PDT 24
Finished Jul 26 06:58:51 PM PDT 24
Peak memory 198080 kb
Host smart-d3448cf4-91cd-490f-8da2-c17659fdd7b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563881409 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_global_esc.563881409
Directory /workspace/16.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/16.pwrmgr_lowpower_invalid.4097250744
Short name T179
Test name
Test status
Simulation time 42699507 ps
CPU time 0.71 seconds
Started Jul 26 06:58:49 PM PDT 24
Finished Jul 26 06:58:50 PM PDT 24
Peak memory 201420 kb
Host smart-4707928e-a5e9-471c-9f7a-5e0d1d608ffe
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097250744 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_lowpower_inval
id.4097250744
Directory /workspace/16.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/16.pwrmgr_reset.2124468288
Short name T576
Test name
Test status
Simulation time 70070404 ps
CPU time 0.81 seconds
Started Jul 26 06:58:48 PM PDT 24
Finished Jul 26 06:58:49 PM PDT 24
Peak memory 199164 kb
Host smart-9a9fe911-8bed-4c69-964a-868a3fbbb544
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124468288 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset.2124468288
Directory /workspace/16.pwrmgr_reset/latest

Test location /workspace/coverage/default/16.pwrmgr_reset_invalid.1808871819
Short name T569
Test name
Test status
Simulation time 107693794 ps
CPU time 1.06 seconds
Started Jul 26 06:58:50 PM PDT 24
Finished Jul 26 06:58:52 PM PDT 24
Peak memory 209456 kb
Host smart-2efa05f7-9310-476c-b6f6-2f942ad6daeb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808871819 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset_invalid.1808871819
Directory /workspace/16.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/16.pwrmgr_sec_cm_rstmgr_intersig_mubi.4292334239
Short name T325
Test name
Test status
Simulation time 60117119 ps
CPU time 0.91 seconds
Started Jul 26 06:58:49 PM PDT 24
Finished Jul 26 06:58:50 PM PDT 24
Peak memory 199240 kb
Host smart-5a96e75a-ae9b-45cd-9e87-9fcfe308a9cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292334239 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4292334239
Directory /workspace/16.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/16.pwrmgr_smoke.3231620074
Short name T391
Test name
Test status
Simulation time 29572850 ps
CPU time 0.73 seconds
Started Jul 26 06:58:54 PM PDT 24
Finished Jul 26 06:58:55 PM PDT 24
Peak memory 199416 kb
Host smart-7051789a-0ce5-45ad-9a11-de903b126acb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231620074 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_smoke.3231620074
Directory /workspace/16.pwrmgr_smoke/latest

Test location /workspace/coverage/default/17.pwrmgr_aborted_low_power.3714187363
Short name T501
Test name
Test status
Simulation time 50624306 ps
CPU time 0.78 seconds
Started Jul 26 06:58:51 PM PDT 24
Finished Jul 26 06:58:53 PM PDT 24
Peak memory 200108 kb
Host smart-76aa1eb2-1a90-42ae-8672-76cc6d0cb197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714187363 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_aborted_low_power.3714187363
Directory /workspace/17.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/17.pwrmgr_disable_rom_integrity_check.1333451147
Short name T413
Test name
Test status
Simulation time 62456464 ps
CPU time 0.77 seconds
Started Jul 26 06:58:56 PM PDT 24
Finished Jul 26 06:58:57 PM PDT 24
Peak memory 199152 kb
Host smart-707ed22d-110c-41c7-9ecd-3bbea8f15ae2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333451147 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_dis
able_rom_integrity_check.1333451147
Directory /workspace/17.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/17.pwrmgr_esc_clk_rst_malfunc.2024605336
Short name T348
Test name
Test status
Simulation time 30585169 ps
CPU time 0.65 seconds
Started Jul 26 06:58:51 PM PDT 24
Finished Jul 26 06:58:51 PM PDT 24
Peak memory 198024 kb
Host smart-4f34d837-78d4-49fd-af14-5e62c3ff0af2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024605336 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_esc_clk_rst
_malfunc.2024605336
Directory /workspace/17.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/17.pwrmgr_escalation_timeout.4050218688
Short name T219
Test name
Test status
Simulation time 756199599 ps
CPU time 0.99 seconds
Started Jul 26 06:58:51 PM PDT 24
Finished Jul 26 06:58:52 PM PDT 24
Peak memory 198140 kb
Host smart-1de8c871-4fdd-4cf3-8694-dbd36794d018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050218688 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_escalation_timeout.4050218688
Directory /workspace/17.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/17.pwrmgr_glitch.3235409865
Short name T376
Test name
Test status
Simulation time 63098520 ps
CPU time 0.69 seconds
Started Jul 26 06:58:56 PM PDT 24
Finished Jul 26 06:58:57 PM PDT 24
Peak memory 197380 kb
Host smart-f0ac47e6-8ff1-4a67-ad17-a6c70ee9d8c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235409865 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_glitch.3235409865
Directory /workspace/17.pwrmgr_glitch/latest

Test location /workspace/coverage/default/17.pwrmgr_global_esc.3126712408
Short name T340
Test name
Test status
Simulation time 41477543 ps
CPU time 0.62 seconds
Started Jul 26 06:58:49 PM PDT 24
Finished Jul 26 06:58:50 PM PDT 24
Peak memory 198152 kb
Host smart-1fc92a5f-207e-4730-8071-cc535f4e7b9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126712408 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_global_esc.3126712408
Directory /workspace/17.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/17.pwrmgr_lowpower_invalid.4063675811
Short name T195
Test name
Test status
Simulation time 44226635 ps
CPU time 0.7 seconds
Started Jul 26 06:58:51 PM PDT 24
Finished Jul 26 06:58:52 PM PDT 24
Peak memory 201392 kb
Host smart-3e254025-09f9-4538-a8a5-fde08cf7dc20
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063675811 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_lowpower_inval
id.4063675811
Directory /workspace/17.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/17.pwrmgr_reset.2176329726
Short name T217
Test name
Test status
Simulation time 102080443 ps
CPU time 0.79 seconds
Started Jul 26 06:58:50 PM PDT 24
Finished Jul 26 06:58:51 PM PDT 24
Peak memory 199168 kb
Host smart-3b168b83-ea43-4bbe-ba0d-2e392f1b6ba0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176329726 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset.2176329726
Directory /workspace/17.pwrmgr_reset/latest

Test location /workspace/coverage/default/17.pwrmgr_reset_invalid.2803952225
Short name T317
Test name
Test status
Simulation time 288553188 ps
CPU time 0.79 seconds
Started Jul 26 06:58:49 PM PDT 24
Finished Jul 26 06:58:50 PM PDT 24
Peak memory 209432 kb
Host smart-0b46ef99-f772-4a3c-a704-7e7e6aa3db0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803952225 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset_invalid.2803952225
Directory /workspace/17.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/17.pwrmgr_sec_cm_ctrl_config_regwen.2655409704
Short name T60
Test name
Test status
Simulation time 78784489 ps
CPU time 0.66 seconds
Started Jul 26 06:58:49 PM PDT 24
Finished Jul 26 06:58:50 PM PDT 24
Peak memory 198628 kb
Host smart-486227ab-3463-4e33-85c5-fecd5426de51
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655409704 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_
cm_ctrl_config_regwen.2655409704
Directory /workspace/17.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/17.pwrmgr_sec_cm_rstmgr_intersig_mubi.2886267738
Short name T407
Test name
Test status
Simulation time 167950261 ps
CPU time 0.79 seconds
Started Jul 26 06:58:57 PM PDT 24
Finished Jul 26 06:58:58 PM PDT 24
Peak memory 198220 kb
Host smart-0468dce4-6dbe-4347-a52e-b70d6bdf20ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886267738 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2886267738
Directory /workspace/17.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/17.pwrmgr_smoke.3962417374
Short name T388
Test name
Test status
Simulation time 28535618 ps
CPU time 0.68 seconds
Started Jul 26 06:58:48 PM PDT 24
Finished Jul 26 06:58:49 PM PDT 24
Peak memory 199496 kb
Host smart-5ee5becf-05ce-4858-bd88-d8617fbd1215
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962417374 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_smoke.3962417374
Directory /workspace/17.pwrmgr_smoke/latest

Test location /workspace/coverage/default/18.pwrmgr_aborted_low_power.207481664
Short name T100
Test name
Test status
Simulation time 64322940 ps
CPU time 0.81 seconds
Started Jul 26 06:58:59 PM PDT 24
Finished Jul 26 06:59:00 PM PDT 24
Peak memory 200216 kb
Host smart-98f5a3e6-0011-4e25-b4e2-e4d483b18d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207481664 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_aborted_low_power.207481664
Directory /workspace/18.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/18.pwrmgr_disable_rom_integrity_check.878542764
Short name T162
Test name
Test status
Simulation time 63178084 ps
CPU time 0.84 seconds
Started Jul 26 06:58:57 PM PDT 24
Finished Jul 26 06:58:58 PM PDT 24
Peak memory 199112 kb
Host smart-c5cbed57-b9c5-412c-b91b-96d8e2cfc253
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878542764 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_disa
ble_rom_integrity_check.878542764
Directory /workspace/18.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/18.pwrmgr_esc_clk_rst_malfunc.849504499
Short name T328
Test name
Test status
Simulation time 28767945 ps
CPU time 0.64 seconds
Started Jul 26 06:58:57 PM PDT 24
Finished Jul 26 06:58:58 PM PDT 24
Peak memory 198028 kb
Host smart-bfb78111-1269-4acc-8057-c5ff22c40a28
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849504499 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_esc_clk_rst_
malfunc.849504499
Directory /workspace/18.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/18.pwrmgr_escalation_timeout.3372795587
Short name T617
Test name
Test status
Simulation time 163108255 ps
CPU time 1 seconds
Started Jul 26 06:58:59 PM PDT 24
Finished Jul 26 06:59:00 PM PDT 24
Peak memory 198352 kb
Host smart-47868cc0-ce64-434f-b62b-17739ce00ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372795587 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_escalation_timeout.3372795587
Directory /workspace/18.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/18.pwrmgr_glitch.3437675092
Short name T206
Test name
Test status
Simulation time 35805603 ps
CPU time 0.66 seconds
Started Jul 26 06:59:00 PM PDT 24
Finished Jul 26 06:59:00 PM PDT 24
Peak memory 198160 kb
Host smart-f56987e9-a379-4c88-bb7b-4ef4cf87ba78
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437675092 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_glitch.3437675092
Directory /workspace/18.pwrmgr_glitch/latest

Test location /workspace/coverage/default/18.pwrmgr_global_esc.1283362413
Short name T48
Test name
Test status
Simulation time 56015805 ps
CPU time 0.6 seconds
Started Jul 26 06:58:59 PM PDT 24
Finished Jul 26 06:59:00 PM PDT 24
Peak memory 198144 kb
Host smart-b2afba99-1c2a-44a3-947b-08d258c59793
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283362413 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_global_esc.1283362413
Directory /workspace/18.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/18.pwrmgr_reset.4066182689
Short name T417
Test name
Test status
Simulation time 151585157 ps
CPU time 0.74 seconds
Started Jul 26 06:58:56 PM PDT 24
Finished Jul 26 06:58:57 PM PDT 24
Peak memory 198344 kb
Host smart-c643fea0-9fae-4b23-88d4-ee3a4a618816
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066182689 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset.4066182689
Directory /workspace/18.pwrmgr_reset/latest

Test location /workspace/coverage/default/18.pwrmgr_reset_invalid.3877294242
Short name T405
Test name
Test status
Simulation time 162386147 ps
CPU time 0.78 seconds
Started Jul 26 06:58:59 PM PDT 24
Finished Jul 26 06:59:00 PM PDT 24
Peak memory 209584 kb
Host smart-44daab04-913e-46cf-80cc-dcd71a57ddd1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877294242 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset_invalid.3877294242
Directory /workspace/18.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/18.pwrmgr_sec_cm_rstmgr_intersig_mubi.277507292
Short name T589
Test name
Test status
Simulation time 262062434 ps
CPU time 0.79 seconds
Started Jul 26 06:58:56 PM PDT 24
Finished Jul 26 06:58:57 PM PDT 24
Peak memory 199284 kb
Host smart-9476ce34-ce62-4669-bd39-3b4003fc56eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277507292 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_rstmgr_intersig_
mubi.277507292
Directory /workspace/18.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/18.pwrmgr_smoke.2412854878
Short name T618
Test name
Test status
Simulation time 101068209 ps
CPU time 0.63 seconds
Started Jul 26 06:58:52 PM PDT 24
Finished Jul 26 06:58:53 PM PDT 24
Peak memory 198548 kb
Host smart-b1119cce-563d-46e5-9ab2-3d023273f84d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412854878 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_smoke.2412854878
Directory /workspace/18.pwrmgr_smoke/latest

Test location /workspace/coverage/default/19.pwrmgr_aborted_low_power.1548970809
Short name T510
Test name
Test status
Simulation time 62666652 ps
CPU time 0.87 seconds
Started Jul 26 06:58:57 PM PDT 24
Finished Jul 26 06:58:58 PM PDT 24
Peak memory 200756 kb
Host smart-a13542a4-ef4e-489e-9aca-73cc7a8d3de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548970809 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_aborted_low_power.1548970809
Directory /workspace/19.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/19.pwrmgr_esc_clk_rst_malfunc.3326425832
Short name T584
Test name
Test status
Simulation time 28536021 ps
CPU time 0.64 seconds
Started Jul 26 06:58:58 PM PDT 24
Finished Jul 26 06:58:59 PM PDT 24
Peak memory 198120 kb
Host smart-97cfce9f-7d03-444e-b9f3-954de515b2c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326425832 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_esc_clk_rst
_malfunc.3326425832
Directory /workspace/19.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/19.pwrmgr_escalation_timeout.1495913273
Short name T136
Test name
Test status
Simulation time 320392882 ps
CPU time 0.99 seconds
Started Jul 26 06:59:03 PM PDT 24
Finished Jul 26 06:59:04 PM PDT 24
Peak memory 198160 kb
Host smart-240a20ea-a1e9-4010-97f3-7b16f1291e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495913273 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_escalation_timeout.1495913273
Directory /workspace/19.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/19.pwrmgr_glitch.357985898
Short name T612
Test name
Test status
Simulation time 55998025 ps
CPU time 0.69 seconds
Started Jul 26 06:59:03 PM PDT 24
Finished Jul 26 06:59:04 PM PDT 24
Peak memory 198084 kb
Host smart-22ca2ff8-8ba7-4792-b51e-43c884389505
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357985898 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_glitch.357985898
Directory /workspace/19.pwrmgr_glitch/latest

Test location /workspace/coverage/default/19.pwrmgr_global_esc.641003283
Short name T420
Test name
Test status
Simulation time 70731398 ps
CPU time 0.64 seconds
Started Jul 26 06:58:59 PM PDT 24
Finished Jul 26 06:59:00 PM PDT 24
Peak memory 198384 kb
Host smart-8de86e16-09f5-4f40-98b3-3a7eddeba312
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641003283 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_global_esc.641003283
Directory /workspace/19.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/19.pwrmgr_lowpower_invalid.1073352357
Short name T193
Test name
Test status
Simulation time 48450409 ps
CPU time 0.69 seconds
Started Jul 26 06:58:59 PM PDT 24
Finished Jul 26 06:59:00 PM PDT 24
Peak memory 201168 kb
Host smart-1c8e3b77-1fba-4af4-b442-fbf58be09663
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073352357 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_lowpower_inval
id.1073352357
Directory /workspace/19.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/19.pwrmgr_reset.3974400874
Short name T358
Test name
Test status
Simulation time 77234640 ps
CPU time 0.81 seconds
Started Jul 26 06:58:59 PM PDT 24
Finished Jul 26 06:59:00 PM PDT 24
Peak memory 199216 kb
Host smart-c603adca-cef3-48b3-a96b-e93af073cb98
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974400874 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset.3974400874
Directory /workspace/19.pwrmgr_reset/latest

Test location /workspace/coverage/default/19.pwrmgr_reset_invalid.156129500
Short name T262
Test name
Test status
Simulation time 110874116 ps
CPU time 0.98 seconds
Started Jul 26 06:58:58 PM PDT 24
Finished Jul 26 06:59:00 PM PDT 24
Peak memory 209460 kb
Host smart-10f740d8-a3c7-42f9-ad83-04251056360b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156129500 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset_invalid.156129500
Directory /workspace/19.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/19.pwrmgr_sec_cm_rstmgr_intersig_mubi.3944908567
Short name T359
Test name
Test status
Simulation time 76728911 ps
CPU time 0.77 seconds
Started Jul 26 06:59:03 PM PDT 24
Finished Jul 26 06:59:03 PM PDT 24
Peak memory 198164 kb
Host smart-95c94e4b-de85-4ca4-bfea-d3d3fae11aa4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944908567 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3944908567
Directory /workspace/19.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/19.pwrmgr_smoke.1548644222
Short name T458
Test name
Test status
Simulation time 56231208 ps
CPU time 0.69 seconds
Started Jul 26 06:58:58 PM PDT 24
Finished Jul 26 06:58:59 PM PDT 24
Peak memory 198644 kb
Host smart-7e6f28fa-7308-4748-9f89-3c077e66d64f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548644222 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_smoke.1548644222
Directory /workspace/19.pwrmgr_smoke/latest

Test location /workspace/coverage/default/2.pwrmgr_aborted_low_power.250101796
Short name T562
Test name
Test status
Simulation time 75086519 ps
CPU time 0.78 seconds
Started Jul 26 06:57:38 PM PDT 24
Finished Jul 26 06:57:39 PM PDT 24
Peak memory 200108 kb
Host smart-b8a49343-ec0c-41ae-b6c9-a8e251898152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250101796 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_aborted_low_power.250101796
Directory /workspace/2.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/2.pwrmgr_disable_rom_integrity_check.2422314937
Short name T337
Test name
Test status
Simulation time 67252655 ps
CPU time 0.66 seconds
Started Jul 26 06:57:37 PM PDT 24
Finished Jul 26 06:57:38 PM PDT 24
Peak memory 199156 kb
Host smart-b0b8a152-ad25-497a-8c37-f89c170bd98b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422314937 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_disa
ble_rom_integrity_check.2422314937
Directory /workspace/2.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/2.pwrmgr_esc_clk_rst_malfunc.1477690580
Short name T315
Test name
Test status
Simulation time 38200120 ps
CPU time 0.59 seconds
Started Jul 26 06:57:39 PM PDT 24
Finished Jul 26 06:57:39 PM PDT 24
Peak memory 198004 kb
Host smart-02468a9d-b66d-43d1-bb28-ab6395d8d1c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477690580 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_esc_clk_rst_
malfunc.1477690580
Directory /workspace/2.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/2.pwrmgr_escalation_timeout.3374304141
Short name T370
Test name
Test status
Simulation time 1678336386 ps
CPU time 1 seconds
Started Jul 26 06:57:38 PM PDT 24
Finished Jul 26 06:57:39 PM PDT 24
Peak memory 198200 kb
Host smart-3a33595f-e081-4c3c-8278-ddb71b26fa50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374304141 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_escalation_timeout.3374304141
Directory /workspace/2.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/2.pwrmgr_glitch.2761942865
Short name T351
Test name
Test status
Simulation time 42632009 ps
CPU time 0.63 seconds
Started Jul 26 06:57:37 PM PDT 24
Finished Jul 26 06:57:38 PM PDT 24
Peak memory 197356 kb
Host smart-d55a5341-4bb9-4666-afbb-8e436a6c6e57
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761942865 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_glitch.2761942865
Directory /workspace/2.pwrmgr_glitch/latest

Test location /workspace/coverage/default/2.pwrmgr_global_esc.3957828413
Short name T459
Test name
Test status
Simulation time 44036186 ps
CPU time 0.58 seconds
Started Jul 26 06:57:36 PM PDT 24
Finished Jul 26 06:57:37 PM PDT 24
Peak memory 198148 kb
Host smart-7369d383-b561-4986-b17e-c8341767d9a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957828413 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_global_esc.3957828413
Directory /workspace/2.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/2.pwrmgr_lowpower_invalid.607064797
Short name T183
Test name
Test status
Simulation time 74901317 ps
CPU time 0.65 seconds
Started Jul 26 06:57:37 PM PDT 24
Finished Jul 26 06:57:38 PM PDT 24
Peak memory 201400 kb
Host smart-ad16ddd3-28df-43d4-adba-38db6c788fb8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607064797 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_lowpower_invalid
.607064797
Directory /workspace/2.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/2.pwrmgr_reset.1795251308
Short name T513
Test name
Test status
Simulation time 44438889 ps
CPU time 0.76 seconds
Started Jul 26 06:57:38 PM PDT 24
Finished Jul 26 06:57:39 PM PDT 24
Peak memory 199188 kb
Host smart-091e896e-f8d8-454f-9e3d-c1e24554e379
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795251308 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset.1795251308
Directory /workspace/2.pwrmgr_reset/latest

Test location /workspace/coverage/default/2.pwrmgr_reset_invalid.649182755
Short name T463
Test name
Test status
Simulation time 101143513 ps
CPU time 0.96 seconds
Started Jul 26 06:57:39 PM PDT 24
Finished Jul 26 06:57:40 PM PDT 24
Peak memory 209572 kb
Host smart-86be596c-4cac-4cbb-beee-f0a1e2aa4034
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649182755 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset_invalid.649182755
Directory /workspace/2.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm.3982086185
Short name T30
Test name
Test status
Simulation time 324986356 ps
CPU time 1.35 seconds
Started Jul 26 06:57:38 PM PDT 24
Finished Jul 26 06:57:40 PM PDT 24
Peak memory 216940 kb
Host smart-7b1d73f4-315d-44c1-9381-b055f602b1f8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982086185 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm.3982086185
Directory /workspace/2.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm_rstmgr_intersig_mubi.1963651309
Short name T235
Test name
Test status
Simulation time 253568199 ps
CPU time 0.79 seconds
Started Jul 26 06:57:39 PM PDT 24
Finished Jul 26 06:57:40 PM PDT 24
Peak memory 199580 kb
Host smart-48828734-0df0-4fb0-b7aa-19d704aac3e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963651309 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_rstmgr_intersig_
mubi.1963651309
Directory /workspace/2.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/2.pwrmgr_smoke.4030588557
Short name T583
Test name
Test status
Simulation time 29856383 ps
CPU time 0.63 seconds
Started Jul 26 06:57:39 PM PDT 24
Finished Jul 26 06:57:39 PM PDT 24
Peak memory 198540 kb
Host smart-3d87030e-9c3e-4e88-8881-48b907854208
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030588557 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_smoke.4030588557
Directory /workspace/2.pwrmgr_smoke/latest

Test location /workspace/coverage/default/20.pwrmgr_aborted_low_power.1084052912
Short name T461
Test name
Test status
Simulation time 27966815 ps
CPU time 0.62 seconds
Started Jul 26 06:58:58 PM PDT 24
Finished Jul 26 06:58:59 PM PDT 24
Peak memory 199220 kb
Host smart-bf247178-34d2-43f5-b066-11d46db16dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084052912 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_aborted_low_power.1084052912
Directory /workspace/20.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/20.pwrmgr_esc_clk_rst_malfunc.2256107122
Short name T369
Test name
Test status
Simulation time 30394714 ps
CPU time 0.63 seconds
Started Jul 26 06:58:57 PM PDT 24
Finished Jul 26 06:58:58 PM PDT 24
Peak memory 197332 kb
Host smart-ea30e74a-7fbc-4bea-abfd-3e110c3b9d1d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256107122 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_esc_clk_rst
_malfunc.2256107122
Directory /workspace/20.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/20.pwrmgr_escalation_timeout.2402749446
Short name T396
Test name
Test status
Simulation time 630297201 ps
CPU time 0.99 seconds
Started Jul 26 06:59:05 PM PDT 24
Finished Jul 26 06:59:06 PM PDT 24
Peak memory 198428 kb
Host smart-f4890644-c9c4-462c-aac6-207d7ecd4b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402749446 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_escalation_timeout.2402749446
Directory /workspace/20.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/20.pwrmgr_glitch.4032348453
Short name T361
Test name
Test status
Simulation time 40000696 ps
CPU time 0.64 seconds
Started Jul 26 06:59:05 PM PDT 24
Finished Jul 26 06:59:05 PM PDT 24
Peak memory 198180 kb
Host smart-0e73541a-13e3-454a-afef-831e8df10ce0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032348453 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_glitch.4032348453
Directory /workspace/20.pwrmgr_glitch/latest

Test location /workspace/coverage/default/20.pwrmgr_global_esc.3119675487
Short name T563
Test name
Test status
Simulation time 84042440 ps
CPU time 0.62 seconds
Started Jul 26 06:58:57 PM PDT 24
Finished Jul 26 06:58:58 PM PDT 24
Peak memory 198416 kb
Host smart-3645d0e9-7b31-4180-bf06-53f8eae60829
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119675487 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_global_esc.3119675487
Directory /workspace/20.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/20.pwrmgr_lowpower_invalid.4156227501
Short name T194
Test name
Test status
Simulation time 42935947 ps
CPU time 0.69 seconds
Started Jul 26 06:59:08 PM PDT 24
Finished Jul 26 06:59:09 PM PDT 24
Peak memory 201416 kb
Host smart-edd0f161-a218-48ed-905f-642a67a67677
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156227501 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_lowpower_inval
id.4156227501
Directory /workspace/20.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/20.pwrmgr_reset.1383975586
Short name T302
Test name
Test status
Simulation time 44567456 ps
CPU time 0.61 seconds
Started Jul 26 06:59:00 PM PDT 24
Finished Jul 26 06:59:00 PM PDT 24
Peak memory 198264 kb
Host smart-fb0d8849-3762-49f8-9612-ec2b93cc4cee
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383975586 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset.1383975586
Directory /workspace/20.pwrmgr_reset/latest

Test location /workspace/coverage/default/20.pwrmgr_reset_invalid.3594618833
Short name T451
Test name
Test status
Simulation time 94350117 ps
CPU time 0.95 seconds
Started Jul 26 06:59:03 PM PDT 24
Finished Jul 26 06:59:04 PM PDT 24
Peak memory 209548 kb
Host smart-2d4d1ae0-2c9a-47ee-a035-7d9345b9aa52
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594618833 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset_invalid.3594618833
Directory /workspace/20.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/20.pwrmgr_sec_cm_rstmgr_intersig_mubi.220470629
Short name T226
Test name
Test status
Simulation time 54959734 ps
CPU time 0.75 seconds
Started Jul 26 06:58:58 PM PDT 24
Finished Jul 26 06:58:59 PM PDT 24
Peak memory 198008 kb
Host smart-18bc0278-d475-4c5c-bab3-d7f0b7c5d7be
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220470629 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm_rstmgr_intersig_
mubi.220470629
Directory /workspace/20.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/20.pwrmgr_smoke.1856913918
Short name T499
Test name
Test status
Simulation time 28397143 ps
CPU time 0.68 seconds
Started Jul 26 06:58:58 PM PDT 24
Finished Jul 26 06:58:59 PM PDT 24
Peak memory 199428 kb
Host smart-c3bcb2c1-905d-46ec-8692-16d83a209dff
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856913918 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_smoke.1856913918
Directory /workspace/20.pwrmgr_smoke/latest

Test location /workspace/coverage/default/21.pwrmgr_aborted_low_power.1191105893
Short name T543
Test name
Test status
Simulation time 49455459 ps
CPU time 0.9 seconds
Started Jul 26 06:59:06 PM PDT 24
Finished Jul 26 06:59:07 PM PDT 24
Peak memory 200352 kb
Host smart-2303b3c6-8c82-4def-a61e-c07d6ec342f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191105893 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_aborted_low_power.1191105893
Directory /workspace/21.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/21.pwrmgr_disable_rom_integrity_check.2889169108
Short name T304
Test name
Test status
Simulation time 75788099 ps
CPU time 0.67 seconds
Started Jul 26 06:59:08 PM PDT 24
Finished Jul 26 06:59:09 PM PDT 24
Peak memory 199180 kb
Host smart-c8011b1b-6aa0-422a-be63-9e82d62bd92e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889169108 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_dis
able_rom_integrity_check.2889169108
Directory /workspace/21.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/21.pwrmgr_esc_clk_rst_malfunc.1240647728
Short name T614
Test name
Test status
Simulation time 29978474 ps
CPU time 0.62 seconds
Started Jul 26 06:59:04 PM PDT 24
Finished Jul 26 06:59:05 PM PDT 24
Peak memory 198092 kb
Host smart-03faba14-0d03-4814-ba8e-bff38a041bf5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240647728 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_esc_clk_rst
_malfunc.1240647728
Directory /workspace/21.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/21.pwrmgr_escalation_timeout.1526879901
Short name T566
Test name
Test status
Simulation time 319990011 ps
CPU time 0.93 seconds
Started Jul 26 06:59:04 PM PDT 24
Finished Jul 26 06:59:05 PM PDT 24
Peak memory 198440 kb
Host smart-26b84f5f-de26-4286-91c7-19cef181021d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526879901 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_escalation_timeout.1526879901
Directory /workspace/21.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/21.pwrmgr_glitch.535597047
Short name T386
Test name
Test status
Simulation time 57255231 ps
CPU time 0.6 seconds
Started Jul 26 06:59:04 PM PDT 24
Finished Jul 26 06:59:04 PM PDT 24
Peak memory 198208 kb
Host smart-b3f8c79a-e7c8-4f95-a91e-6aec605d1d1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535597047 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_glitch.535597047
Directory /workspace/21.pwrmgr_glitch/latest

Test location /workspace/coverage/default/21.pwrmgr_global_esc.3238814350
Short name T270
Test name
Test status
Simulation time 29329595 ps
CPU time 0.61 seconds
Started Jul 26 06:59:05 PM PDT 24
Finished Jul 26 06:59:06 PM PDT 24
Peak memory 198420 kb
Host smart-73017afe-6fb9-4ca3-b9ba-1fdeb4d44982
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238814350 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_global_esc.3238814350
Directory /workspace/21.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/21.pwrmgr_reset.1330880209
Short name T24
Test name
Test status
Simulation time 72523266 ps
CPU time 0.9 seconds
Started Jul 26 06:59:05 PM PDT 24
Finished Jul 26 06:59:06 PM PDT 24
Peak memory 199116 kb
Host smart-d735b0d8-0c12-4cc8-b3ad-36cc254762f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330880209 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset.1330880209
Directory /workspace/21.pwrmgr_reset/latest

Test location /workspace/coverage/default/21.pwrmgr_reset_invalid.3288488484
Short name T411
Test name
Test status
Simulation time 160049332 ps
CPU time 0.84 seconds
Started Jul 26 06:59:07 PM PDT 24
Finished Jul 26 06:59:08 PM PDT 24
Peak memory 209528 kb
Host smart-7bd2a46f-30ed-4b36-9e9a-ed9a89d6b436
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288488484 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset_invalid.3288488484
Directory /workspace/21.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/21.pwrmgr_sec_cm_rstmgr_intersig_mubi.910405713
Short name T204
Test name
Test status
Simulation time 69037295 ps
CPU time 0.74 seconds
Started Jul 26 06:59:06 PM PDT 24
Finished Jul 26 06:59:07 PM PDT 24
Peak memory 198180 kb
Host smart-9d7b486b-f4df-4a91-a532-35cd8638edcd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910405713 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_rstmgr_intersig_
mubi.910405713
Directory /workspace/21.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/21.pwrmgr_smoke.1088234898
Short name T90
Test name
Test status
Simulation time 27962700 ps
CPU time 0.68 seconds
Started Jul 26 06:59:03 PM PDT 24
Finished Jul 26 06:59:04 PM PDT 24
Peak memory 199408 kb
Host smart-e3c8cf4d-6854-4af9-abcb-1fd9434919d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088234898 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_smoke.1088234898
Directory /workspace/21.pwrmgr_smoke/latest

Test location /workspace/coverage/default/22.pwrmgr_aborted_low_power.3530713564
Short name T308
Test name
Test status
Simulation time 130765103 ps
CPU time 0.68 seconds
Started Jul 26 06:59:04 PM PDT 24
Finished Jul 26 06:59:05 PM PDT 24
Peak memory 198860 kb
Host smart-6bfd82a8-46b5-4386-a5fa-64d65cfa27ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530713564 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_aborted_low_power.3530713564
Directory /workspace/22.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/22.pwrmgr_disable_rom_integrity_check.1346247834
Short name T37
Test name
Test status
Simulation time 57862882 ps
CPU time 0.7 seconds
Started Jul 26 06:59:08 PM PDT 24
Finished Jul 26 06:59:09 PM PDT 24
Peak memory 199140 kb
Host smart-5b19dbc5-3eb8-45d4-9cfa-9bdcb32d249b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346247834 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_dis
able_rom_integrity_check.1346247834
Directory /workspace/22.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/22.pwrmgr_esc_clk_rst_malfunc.2022611341
Short name T587
Test name
Test status
Simulation time 43554041 ps
CPU time 0.58 seconds
Started Jul 26 06:59:04 PM PDT 24
Finished Jul 26 06:59:05 PM PDT 24
Peak memory 198032 kb
Host smart-066b0e7c-b2eb-489f-8a9c-8155029447e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022611341 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_esc_clk_rst
_malfunc.2022611341
Directory /workspace/22.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/22.pwrmgr_escalation_timeout.1711025430
Short name T137
Test name
Test status
Simulation time 174770288 ps
CPU time 1.01 seconds
Started Jul 26 06:59:05 PM PDT 24
Finished Jul 26 06:59:06 PM PDT 24
Peak memory 198164 kb
Host smart-e63a419f-de1a-4eae-a200-c130d934d836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711025430 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_escalation_timeout.1711025430
Directory /workspace/22.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/22.pwrmgr_glitch.2551869458
Short name T211
Test name
Test status
Simulation time 59049145 ps
CPU time 0.64 seconds
Started Jul 26 06:59:05 PM PDT 24
Finished Jul 26 06:59:06 PM PDT 24
Peak memory 198068 kb
Host smart-af783985-641d-40dd-932f-0ae116ae1477
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551869458 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_glitch.2551869458
Directory /workspace/22.pwrmgr_glitch/latest

Test location /workspace/coverage/default/22.pwrmgr_global_esc.891719475
Short name T495
Test name
Test status
Simulation time 50684048 ps
CPU time 0.66 seconds
Started Jul 26 06:59:08 PM PDT 24
Finished Jul 26 06:59:09 PM PDT 24
Peak memory 198128 kb
Host smart-abf0948c-9fa7-44ea-be68-53afd6ff62af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891719475 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_global_esc.891719475
Directory /workspace/22.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/22.pwrmgr_lowpower_invalid.721640365
Short name T603
Test name
Test status
Simulation time 57127376 ps
CPU time 0.72 seconds
Started Jul 26 06:59:04 PM PDT 24
Finished Jul 26 06:59:05 PM PDT 24
Peak memory 201480 kb
Host smart-9b7d8fab-4ab9-4e3e-a9cb-5352e41fd83d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721640365 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_lowpower_invali
d.721640365
Directory /workspace/22.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/22.pwrmgr_reset.150960258
Short name T509
Test name
Test status
Simulation time 76686706 ps
CPU time 0.9 seconds
Started Jul 26 06:59:05 PM PDT 24
Finished Jul 26 06:59:06 PM PDT 24
Peak memory 199204 kb
Host smart-660a2be9-10dd-440c-b44e-903d92ff51f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150960258 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset.150960258
Directory /workspace/22.pwrmgr_reset/latest

Test location /workspace/coverage/default/22.pwrmgr_reset_invalid.4107667188
Short name T44
Test name
Test status
Simulation time 91991504 ps
CPU time 0.91 seconds
Started Jul 26 06:59:09 PM PDT 24
Finished Jul 26 06:59:10 PM PDT 24
Peak memory 209560 kb
Host smart-66318b5c-9c44-4878-bd34-9967c6330232
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107667188 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset_invalid.4107667188
Directory /workspace/22.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/22.pwrmgr_sec_cm_ctrl_config_regwen.434881384
Short name T69
Test name
Test status
Simulation time 72492224 ps
CPU time 0.68 seconds
Started Jul 26 06:59:09 PM PDT 24
Finished Jul 26 06:59:10 PM PDT 24
Peak memory 198604 kb
Host smart-c068e176-0bb5-414f-869f-5a0f94f0a545
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434881384 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_c
m_ctrl_config_regwen.434881384
Directory /workspace/22.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/22.pwrmgr_sec_cm_rstmgr_intersig_mubi.1669626431
Short name T475
Test name
Test status
Simulation time 66920603 ps
CPU time 0.86 seconds
Started Jul 26 06:59:05 PM PDT 24
Finished Jul 26 06:59:06 PM PDT 24
Peak memory 199228 kb
Host smart-17c8a0e9-dc48-49c3-a5f2-e73e59acebf1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669626431 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1669626431
Directory /workspace/22.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/22.pwrmgr_smoke.1614142534
Short name T300
Test name
Test status
Simulation time 38215567 ps
CPU time 0.65 seconds
Started Jul 26 06:59:08 PM PDT 24
Finished Jul 26 06:59:09 PM PDT 24
Peak memory 199384 kb
Host smart-838998cc-982a-44c9-8d7c-aba7627480d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614142534 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_smoke.1614142534
Directory /workspace/22.pwrmgr_smoke/latest

Test location /workspace/coverage/default/23.pwrmgr_aborted_low_power.1665553173
Short name T559
Test name
Test status
Simulation time 22741909 ps
CPU time 0.65 seconds
Started Jul 26 06:59:17 PM PDT 24
Finished Jul 26 06:59:18 PM PDT 24
Peak memory 198696 kb
Host smart-6dfc0687-fea8-40ec-9fec-d0e68fe048a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665553173 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_aborted_low_power.1665553173
Directory /workspace/23.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/23.pwrmgr_disable_rom_integrity_check.88822120
Short name T155
Test name
Test status
Simulation time 69225422 ps
CPU time 0.68 seconds
Started Jul 26 06:59:16 PM PDT 24
Finished Jul 26 06:59:16 PM PDT 24
Peak memory 199364 kb
Host smart-9354ab11-5261-46b8-92f0-3bc994e46987
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88822120 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_int
egrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_disab
le_rom_integrity_check.88822120
Directory /workspace/23.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/23.pwrmgr_esc_clk_rst_malfunc.205663692
Short name T404
Test name
Test status
Simulation time 93177891 ps
CPU time 0.58 seconds
Started Jul 26 06:59:14 PM PDT 24
Finished Jul 26 06:59:14 PM PDT 24
Peak memory 198104 kb
Host smart-48f8fae0-bd45-4ecf-bb5c-87ae5b267045
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205663692 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_esc_clk_rst_
malfunc.205663692
Directory /workspace/23.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/23.pwrmgr_escalation_timeout.2777363408
Short name T605
Test name
Test status
Simulation time 653775937 ps
CPU time 0.95 seconds
Started Jul 26 06:59:15 PM PDT 24
Finished Jul 26 06:59:17 PM PDT 24
Peak memory 198112 kb
Host smart-259ee201-38ca-4249-9c77-16019068134f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777363408 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_escalation_timeout.2777363408
Directory /workspace/23.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/23.pwrmgr_glitch.2697691973
Short name T403
Test name
Test status
Simulation time 34568377 ps
CPU time 0.62 seconds
Started Jul 26 06:59:18 PM PDT 24
Finished Jul 26 06:59:19 PM PDT 24
Peak memory 198084 kb
Host smart-f889a48d-844d-42fb-8727-d4642e07b3cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697691973 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_glitch.2697691973
Directory /workspace/23.pwrmgr_glitch/latest

Test location /workspace/coverage/default/23.pwrmgr_global_esc.3660152954
Short name T346
Test name
Test status
Simulation time 52043120 ps
CPU time 0.65 seconds
Started Jul 26 06:59:18 PM PDT 24
Finished Jul 26 06:59:19 PM PDT 24
Peak memory 198096 kb
Host smart-f166a9a3-88b9-4f33-8fc3-73761a9f80fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660152954 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_global_esc.3660152954
Directory /workspace/23.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/23.pwrmgr_lowpower_invalid.2687449483
Short name T176
Test name
Test status
Simulation time 40010969 ps
CPU time 0.73 seconds
Started Jul 26 06:59:20 PM PDT 24
Finished Jul 26 06:59:20 PM PDT 24
Peak memory 201416 kb
Host smart-55bd2b79-38b9-4821-a502-0968ab140b9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687449483 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_lowpower_inval
id.2687449483
Directory /workspace/23.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/23.pwrmgr_reset.2341860687
Short name T498
Test name
Test status
Simulation time 93062231 ps
CPU time 0.78 seconds
Started Jul 26 06:59:17 PM PDT 24
Finished Jul 26 06:59:17 PM PDT 24
Peak memory 199156 kb
Host smart-f3bcb5e6-0fa8-4fbb-86d7-def4ce18221b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341860687 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset.2341860687
Directory /workspace/23.pwrmgr_reset/latest

Test location /workspace/coverage/default/23.pwrmgr_reset_invalid.1709336026
Short name T506
Test name
Test status
Simulation time 106216813 ps
CPU time 1.01 seconds
Started Jul 26 06:59:18 PM PDT 24
Finished Jul 26 06:59:19 PM PDT 24
Peak memory 209496 kb
Host smart-c8f1306d-0b6d-49b7-ac6f-27af20541281
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709336026 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset_invalid.1709336026
Directory /workspace/23.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/23.pwrmgr_sec_cm_rstmgr_intersig_mubi.254068409
Short name T502
Test name
Test status
Simulation time 58910856 ps
CPU time 0.83 seconds
Started Jul 26 06:59:13 PM PDT 24
Finished Jul 26 06:59:14 PM PDT 24
Peak memory 198380 kb
Host smart-3c9aed4a-945c-4155-a5e0-17617e5eeaf1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254068409 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_rstmgr_intersig_
mubi.254068409
Directory /workspace/23.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/23.pwrmgr_smoke.4147389970
Short name T312
Test name
Test status
Simulation time 31177839 ps
CPU time 0.67 seconds
Started Jul 26 06:59:29 PM PDT 24
Finished Jul 26 06:59:30 PM PDT 24
Peak memory 199448 kb
Host smart-7f3e589a-20e1-4c00-83f7-ff0f00a50935
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147389970 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_smoke.4147389970
Directory /workspace/23.pwrmgr_smoke/latest

Test location /workspace/coverage/default/24.pwrmgr_aborted_low_power.2255517664
Short name T326
Test name
Test status
Simulation time 23954569 ps
CPU time 0.65 seconds
Started Jul 26 06:59:15 PM PDT 24
Finished Jul 26 06:59:15 PM PDT 24
Peak memory 198644 kb
Host smart-274babb5-65e6-47b1-aa72-33f9c5a56272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255517664 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_aborted_low_power.2255517664
Directory /workspace/24.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/24.pwrmgr_esc_clk_rst_malfunc.3844781744
Short name T462
Test name
Test status
Simulation time 31792731 ps
CPU time 0.58 seconds
Started Jul 26 06:59:16 PM PDT 24
Finished Jul 26 06:59:17 PM PDT 24
Peak memory 198048 kb
Host smart-0f0152d3-443c-4da4-841b-c6af8e341d09
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844781744 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_esc_clk_rst
_malfunc.3844781744
Directory /workspace/24.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/24.pwrmgr_escalation_timeout.3237718019
Short name T380
Test name
Test status
Simulation time 520422833 ps
CPU time 0.97 seconds
Started Jul 26 06:59:15 PM PDT 24
Finished Jul 26 06:59:17 PM PDT 24
Peak memory 198396 kb
Host smart-a35f012d-49e8-45df-8c9f-e408d9e8ae9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237718019 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_escalation_timeout.3237718019
Directory /workspace/24.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/24.pwrmgr_glitch.462025590
Short name T294
Test name
Test status
Simulation time 38717200 ps
CPU time 0.61 seconds
Started Jul 26 06:59:15 PM PDT 24
Finished Jul 26 06:59:16 PM PDT 24
Peak memory 198020 kb
Host smart-26b8f9e9-33f7-4577-957c-93522605bcae
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462025590 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_glitch.462025590
Directory /workspace/24.pwrmgr_glitch/latest

Test location /workspace/coverage/default/24.pwrmgr_global_esc.2551889106
Short name T490
Test name
Test status
Simulation time 27882768 ps
CPU time 0.64 seconds
Started Jul 26 06:59:15 PM PDT 24
Finished Jul 26 06:59:16 PM PDT 24
Peak memory 198456 kb
Host smart-075a454d-f610-4c68-8e2f-f296922c6f51
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551889106 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_global_esc.2551889106
Directory /workspace/24.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/24.pwrmgr_lowpower_invalid.1648835451
Short name T178
Test name
Test status
Simulation time 82056314 ps
CPU time 0.66 seconds
Started Jul 26 06:59:25 PM PDT 24
Finished Jul 26 06:59:26 PM PDT 24
Peak memory 201452 kb
Host smart-9bb0820a-28d0-4fc6-a5a0-051716ecbced
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648835451 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_lowpower_inval
id.1648835451
Directory /workspace/24.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/24.pwrmgr_reset.949768442
Short name T344
Test name
Test status
Simulation time 91030563 ps
CPU time 0.71 seconds
Started Jul 26 06:59:17 PM PDT 24
Finished Jul 26 06:59:18 PM PDT 24
Peak memory 198276 kb
Host smart-0eca9163-22a5-4bd4-8092-8616d87d6f5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949768442 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset.949768442
Directory /workspace/24.pwrmgr_reset/latest

Test location /workspace/coverage/default/24.pwrmgr_reset_invalid.2654809328
Short name T381
Test name
Test status
Simulation time 258370622 ps
CPU time 0.76 seconds
Started Jul 26 06:59:24 PM PDT 24
Finished Jul 26 06:59:25 PM PDT 24
Peak memory 209588 kb
Host smart-3b281ad9-c413-4553-a6d3-6228e4d2a62f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654809328 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset_invalid.2654809328
Directory /workspace/24.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/24.pwrmgr_sec_cm_rstmgr_intersig_mubi.1314518830
Short name T414
Test name
Test status
Simulation time 124688180 ps
CPU time 0.77 seconds
Started Jul 26 06:59:15 PM PDT 24
Finished Jul 26 06:59:16 PM PDT 24
Peak memory 198220 kb
Host smart-0572dd42-42db-46d4-8b8a-6e4339d43963
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314518830 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1314518830
Directory /workspace/24.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/25.pwrmgr_aborted_low_power.3631342427
Short name T105
Test name
Test status
Simulation time 122690483 ps
CPU time 0.81 seconds
Started Jul 26 06:59:30 PM PDT 24
Finished Jul 26 06:59:31 PM PDT 24
Peak memory 200124 kb
Host smart-b3bb2b8f-8692-4566-9763-b9a4f3839bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631342427 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_aborted_low_power.3631342427
Directory /workspace/25.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/25.pwrmgr_disable_rom_integrity_check.1351480928
Short name T47
Test name
Test status
Simulation time 68352794 ps
CPU time 0.75 seconds
Started Jul 26 06:59:30 PM PDT 24
Finished Jul 26 06:59:31 PM PDT 24
Peak memory 198644 kb
Host smart-af321745-e7f4-4611-9866-a0eae962a9af
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351480928 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_dis
able_rom_integrity_check.1351480928
Directory /workspace/25.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/25.pwrmgr_esc_clk_rst_malfunc.2277380474
Short name T378
Test name
Test status
Simulation time 32026355 ps
CPU time 0.59 seconds
Started Jul 26 06:59:30 PM PDT 24
Finished Jul 26 06:59:31 PM PDT 24
Peak memory 198100 kb
Host smart-d5a61e63-77cf-40db-9416-f0d408acf279
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277380474 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_esc_clk_rst
_malfunc.2277380474
Directory /workspace/25.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/25.pwrmgr_escalation_timeout.2930283525
Short name T49
Test name
Test status
Simulation time 165401055 ps
CPU time 0.99 seconds
Started Jul 26 06:59:25 PM PDT 24
Finished Jul 26 06:59:26 PM PDT 24
Peak memory 198156 kb
Host smart-4a624ac6-87e1-46c9-b69a-7d22639650c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930283525 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_escalation_timeout.2930283525
Directory /workspace/25.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/25.pwrmgr_glitch.2984926341
Short name T289
Test name
Test status
Simulation time 37779348 ps
CPU time 0.61 seconds
Started Jul 26 06:59:24 PM PDT 24
Finished Jul 26 06:59:24 PM PDT 24
Peak memory 198156 kb
Host smart-b26bfe52-3684-4903-8cbb-2c71d4e23970
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984926341 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_glitch.2984926341
Directory /workspace/25.pwrmgr_glitch/latest

Test location /workspace/coverage/default/25.pwrmgr_global_esc.3717378094
Short name T7
Test name
Test status
Simulation time 23501155 ps
CPU time 0.64 seconds
Started Jul 26 06:59:30 PM PDT 24
Finished Jul 26 06:59:31 PM PDT 24
Peak memory 198224 kb
Host smart-b33efab5-ba71-4079-9dcf-403d6e37c8f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717378094 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_global_esc.3717378094
Directory /workspace/25.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/25.pwrmgr_lowpower_invalid.2781664238
Short name T173
Test name
Test status
Simulation time 40532872 ps
CPU time 0.71 seconds
Started Jul 26 06:59:27 PM PDT 24
Finished Jul 26 06:59:28 PM PDT 24
Peak memory 201424 kb
Host smart-ac5bb2e6-c205-49e9-9ea5-37b6a2fe1731
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781664238 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_lowpower_inval
id.2781664238
Directory /workspace/25.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/25.pwrmgr_reset.1040202095
Short name T572
Test name
Test status
Simulation time 65848587 ps
CPU time 0.85 seconds
Started Jul 26 06:59:24 PM PDT 24
Finished Jul 26 06:59:25 PM PDT 24
Peak memory 198604 kb
Host smart-1cd4d202-4be2-4111-b4c4-1a6e22c6bc4f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040202095 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset.1040202095
Directory /workspace/25.pwrmgr_reset/latest

Test location /workspace/coverage/default/25.pwrmgr_reset_invalid.1618069666
Short name T425
Test name
Test status
Simulation time 104895791 ps
CPU time 1.06 seconds
Started Jul 26 06:59:24 PM PDT 24
Finished Jul 26 06:59:25 PM PDT 24
Peak memory 209556 kb
Host smart-36f19d36-9935-447a-874b-2048343a1f50
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618069666 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset_invalid.1618069666
Directory /workspace/25.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/25.pwrmgr_sec_cm_rstmgr_intersig_mubi.2788641641
Short name T313
Test name
Test status
Simulation time 115409956 ps
CPU time 0.91 seconds
Started Jul 26 06:59:28 PM PDT 24
Finished Jul 26 06:59:29 PM PDT 24
Peak memory 199368 kb
Host smart-5fa5faa0-de8d-42ac-9535-413050736e9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788641641 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2788641641
Directory /workspace/25.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/25.pwrmgr_smoke.1208533752
Short name T487
Test name
Test status
Simulation time 42383883 ps
CPU time 0.63 seconds
Started Jul 26 06:59:23 PM PDT 24
Finished Jul 26 06:59:24 PM PDT 24
Peak memory 198524 kb
Host smart-970a507e-3e68-4bc7-bc5c-9f1a9cedb48e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208533752 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_smoke.1208533752
Directory /workspace/25.pwrmgr_smoke/latest

Test location /workspace/coverage/default/26.pwrmgr_aborted_low_power.777477217
Short name T496
Test name
Test status
Simulation time 42453737 ps
CPU time 0.81 seconds
Started Jul 26 06:59:24 PM PDT 24
Finished Jul 26 06:59:25 PM PDT 24
Peak memory 199936 kb
Host smart-c5f87508-4941-4230-ba74-36b10d792d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777477217 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_aborted_low_power.777477217
Directory /workspace/26.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/26.pwrmgr_disable_rom_integrity_check.1698823164
Short name T42
Test name
Test status
Simulation time 50730642 ps
CPU time 0.77 seconds
Started Jul 26 06:59:26 PM PDT 24
Finished Jul 26 06:59:27 PM PDT 24
Peak memory 198596 kb
Host smart-d3d0fd91-051e-4d34-96de-e0d78a5fcdeb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698823164 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_dis
able_rom_integrity_check.1698823164
Directory /workspace/26.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/26.pwrmgr_esc_clk_rst_malfunc.2954351997
Short name T390
Test name
Test status
Simulation time 59107552 ps
CPU time 0.58 seconds
Started Jul 26 06:59:27 PM PDT 24
Finished Jul 26 06:59:28 PM PDT 24
Peak memory 198100 kb
Host smart-86564b2d-3983-46e7-8792-3afa790f9b5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954351997 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_esc_clk_rst
_malfunc.2954351997
Directory /workspace/26.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/26.pwrmgr_escalation_timeout.3506719421
Short name T389
Test name
Test status
Simulation time 160820996 ps
CPU time 0.99 seconds
Started Jul 26 06:59:26 PM PDT 24
Finished Jul 26 06:59:27 PM PDT 24
Peak memory 198448 kb
Host smart-fc8ac271-e70f-49c9-b628-042551ab779a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506719421 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_escalation_timeout.3506719421
Directory /workspace/26.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/26.pwrmgr_glitch.2344670271
Short name T330
Test name
Test status
Simulation time 73750546 ps
CPU time 0.66 seconds
Started Jul 26 06:59:29 PM PDT 24
Finished Jul 26 06:59:30 PM PDT 24
Peak memory 198148 kb
Host smart-e9795193-4741-44f7-9116-89fce5ae5186
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344670271 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_glitch.2344670271
Directory /workspace/26.pwrmgr_glitch/latest

Test location /workspace/coverage/default/26.pwrmgr_global_esc.1590957076
Short name T331
Test name
Test status
Simulation time 57268106 ps
CPU time 0.63 seconds
Started Jul 26 06:59:25 PM PDT 24
Finished Jul 26 06:59:25 PM PDT 24
Peak memory 197996 kb
Host smart-a8708ae6-601a-4407-8622-182d24813632
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590957076 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_global_esc.1590957076
Directory /workspace/26.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/26.pwrmgr_lowpower_invalid.1789150098
Short name T196
Test name
Test status
Simulation time 58832238 ps
CPU time 0.7 seconds
Started Jul 26 06:59:23 PM PDT 24
Finished Jul 26 06:59:24 PM PDT 24
Peak memory 201432 kb
Host smart-693e703d-c18f-4a96-8587-561e6eceb09b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789150098 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_lowpower_inval
id.1789150098
Directory /workspace/26.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/26.pwrmgr_reset.390149861
Short name T236
Test name
Test status
Simulation time 41602504 ps
CPU time 0.76 seconds
Started Jul 26 06:59:24 PM PDT 24
Finished Jul 26 06:59:25 PM PDT 24
Peak memory 198408 kb
Host smart-cd08f639-d399-4ac7-b503-828a3bdfea89
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390149861 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset.390149861
Directory /workspace/26.pwrmgr_reset/latest

Test location /workspace/coverage/default/26.pwrmgr_reset_invalid.3687107083
Short name T228
Test name
Test status
Simulation time 166043238 ps
CPU time 0.81 seconds
Started Jul 26 06:59:24 PM PDT 24
Finished Jul 26 06:59:25 PM PDT 24
Peak memory 209460 kb
Host smart-028b6688-8d17-47d2-9413-c02d0fca7faa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687107083 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset_invalid.3687107083
Directory /workspace/26.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/26.pwrmgr_sec_cm_rstmgr_intersig_mubi.1344065549
Short name T611
Test name
Test status
Simulation time 53616202 ps
CPU time 0.86 seconds
Started Jul 26 06:59:25 PM PDT 24
Finished Jul 26 06:59:26 PM PDT 24
Peak memory 198184 kb
Host smart-4cfca89a-783b-4e56-b80e-961bc5940806
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344065549 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1344065549
Directory /workspace/26.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/26.pwrmgr_smoke.209472626
Short name T542
Test name
Test status
Simulation time 54947186 ps
CPU time 0.64 seconds
Started Jul 26 06:59:26 PM PDT 24
Finished Jul 26 06:59:27 PM PDT 24
Peak memory 199432 kb
Host smart-5cdfb8b8-328a-44bf-ad48-61a319e92327
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209472626 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_smoke.209472626
Directory /workspace/26.pwrmgr_smoke/latest

Test location /workspace/coverage/default/27.pwrmgr_aborted_low_power.1871861999
Short name T95
Test name
Test status
Simulation time 75775522 ps
CPU time 0.92 seconds
Started Jul 26 06:59:34 PM PDT 24
Finished Jul 26 06:59:35 PM PDT 24
Peak memory 200412 kb
Host smart-1404d22b-ccd9-4ad8-80a2-471b70cc75a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871861999 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_aborted_low_power.1871861999
Directory /workspace/27.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/27.pwrmgr_disable_rom_integrity_check.3718492949
Short name T28
Test name
Test status
Simulation time 67326430 ps
CPU time 0.62 seconds
Started Jul 26 06:59:30 PM PDT 24
Finished Jul 26 06:59:31 PM PDT 24
Peak memory 198592 kb
Host smart-bcd00f28-5cc9-45aa-bd67-88909f0ec855
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718492949 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_dis
able_rom_integrity_check.3718492949
Directory /workspace/27.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/27.pwrmgr_esc_clk_rst_malfunc.4019314248
Short name T224
Test name
Test status
Simulation time 29584594 ps
CPU time 0.64 seconds
Started Jul 26 06:59:30 PM PDT 24
Finished Jul 26 06:59:31 PM PDT 24
Peak memory 197344 kb
Host smart-4b19c71c-eeb9-4954-a9ca-02ecfe7d36c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019314248 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_esc_clk_rst
_malfunc.4019314248
Directory /workspace/27.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/27.pwrmgr_escalation_timeout.2122472123
Short name T256
Test name
Test status
Simulation time 159575320 ps
CPU time 0.94 seconds
Started Jul 26 06:59:33 PM PDT 24
Finished Jul 26 06:59:34 PM PDT 24
Peak memory 198132 kb
Host smart-42011d2b-a2dd-49d1-86be-49ada9ec505b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122472123 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_escalation_timeout.2122472123
Directory /workspace/27.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/27.pwrmgr_glitch.984279174
Short name T441
Test name
Test status
Simulation time 59862050 ps
CPU time 0.73 seconds
Started Jul 26 06:59:31 PM PDT 24
Finished Jul 26 06:59:32 PM PDT 24
Peak memory 197356 kb
Host smart-d8391b37-f430-48d9-9ccf-ccf900ede6c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984279174 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_glitch.984279174
Directory /workspace/27.pwrmgr_glitch/latest

Test location /workspace/coverage/default/27.pwrmgr_global_esc.1698271468
Short name T508
Test name
Test status
Simulation time 25402404 ps
CPU time 0.6 seconds
Started Jul 26 06:59:30 PM PDT 24
Finished Jul 26 06:59:31 PM PDT 24
Peak memory 198436 kb
Host smart-26c5759e-684d-4f84-a76f-d42e8881e1f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698271468 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_global_esc.1698271468
Directory /workspace/27.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/27.pwrmgr_reset.347265597
Short name T210
Test name
Test status
Simulation time 23468533 ps
CPU time 0.66 seconds
Started Jul 26 06:59:34 PM PDT 24
Finished Jul 26 06:59:35 PM PDT 24
Peak memory 198236 kb
Host smart-eeb28fa9-ad38-4ed7-bc18-4674fc3bc144
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347265597 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset.347265597
Directory /workspace/27.pwrmgr_reset/latest

Test location /workspace/coverage/default/27.pwrmgr_reset_invalid.816793341
Short name T327
Test name
Test status
Simulation time 195597794 ps
CPU time 0.82 seconds
Started Jul 26 06:59:35 PM PDT 24
Finished Jul 26 06:59:36 PM PDT 24
Peak memory 209656 kb
Host smart-933230ad-1213-46bf-9b61-74150d534f2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816793341 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset_invalid.816793341
Directory /workspace/27.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/27.pwrmgr_sec_cm_ctrl_config_regwen.512108143
Short name T145
Test name
Test status
Simulation time 37930228 ps
CPU time 0.7 seconds
Started Jul 26 06:59:32 PM PDT 24
Finished Jul 26 06:59:32 PM PDT 24
Peak memory 199132 kb
Host smart-1163ccdc-103b-4e47-967c-4a04f4efea9d
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512108143 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_c
m_ctrl_config_regwen.512108143
Directory /workspace/27.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/27.pwrmgr_sec_cm_rstmgr_intersig_mubi.3073113945
Short name T549
Test name
Test status
Simulation time 137424299 ps
CPU time 0.76 seconds
Started Jul 26 06:59:30 PM PDT 24
Finished Jul 26 06:59:31 PM PDT 24
Peak memory 197968 kb
Host smart-df26d52c-3f32-45a3-9a8b-ee422f4e26aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073113945 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3073113945
Directory /workspace/27.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/27.pwrmgr_smoke.2205798912
Short name T221
Test name
Test status
Simulation time 28953171 ps
CPU time 0.66 seconds
Started Jul 26 06:59:31 PM PDT 24
Finished Jul 26 06:59:32 PM PDT 24
Peak memory 199420 kb
Host smart-1dfd095b-f67d-472e-b7a7-833cf87080d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205798912 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_smoke.2205798912
Directory /workspace/27.pwrmgr_smoke/latest

Test location /workspace/coverage/default/28.pwrmgr_aborted_low_power.1228868085
Short name T354
Test name
Test status
Simulation time 48389032 ps
CPU time 0.71 seconds
Started Jul 26 06:59:30 PM PDT 24
Finished Jul 26 06:59:31 PM PDT 24
Peak memory 198740 kb
Host smart-077c17e2-4ad7-499c-9a10-1599ecc501cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228868085 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_aborted_low_power.1228868085
Directory /workspace/28.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/28.pwrmgr_disable_rom_integrity_check.2325268438
Short name T353
Test name
Test status
Simulation time 65743739 ps
CPU time 0.68 seconds
Started Jul 26 06:59:31 PM PDT 24
Finished Jul 26 06:59:32 PM PDT 24
Peak memory 198276 kb
Host smart-0ee467a3-bf3b-448d-a4da-ff92e5ccc91f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325268438 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_dis
able_rom_integrity_check.2325268438
Directory /workspace/28.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/28.pwrmgr_esc_clk_rst_malfunc.381641397
Short name T452
Test name
Test status
Simulation time 44529789 ps
CPU time 0.6 seconds
Started Jul 26 06:59:30 PM PDT 24
Finished Jul 26 06:59:31 PM PDT 24
Peak memory 198072 kb
Host smart-1be26008-1b1c-4d97-b4a1-e5f902a626bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381641397 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_esc_clk_rst_
malfunc.381641397
Directory /workspace/28.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/28.pwrmgr_escalation_timeout.3964717411
Short name T314
Test name
Test status
Simulation time 556330201 ps
CPU time 0.96 seconds
Started Jul 26 06:59:33 PM PDT 24
Finished Jul 26 06:59:34 PM PDT 24
Peak memory 198148 kb
Host smart-33ef0b80-c855-449c-88a4-b052506c7f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964717411 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_escalation_timeout.3964717411
Directory /workspace/28.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/28.pwrmgr_glitch.105068616
Short name T98
Test name
Test status
Simulation time 139718934 ps
CPU time 0.58 seconds
Started Jul 26 06:59:34 PM PDT 24
Finished Jul 26 06:59:35 PM PDT 24
Peak memory 197440 kb
Host smart-7f53e647-e685-459b-a8cd-6aee3f61de22
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105068616 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_glitch.105068616
Directory /workspace/28.pwrmgr_glitch/latest

Test location /workspace/coverage/default/28.pwrmgr_global_esc.4080227887
Short name T479
Test name
Test status
Simulation time 67299370 ps
CPU time 0.66 seconds
Started Jul 26 06:59:35 PM PDT 24
Finished Jul 26 06:59:35 PM PDT 24
Peak memory 198428 kb
Host smart-9e92b651-344d-4195-a43a-b6982c2cfc53
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080227887 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_global_esc.4080227887
Directory /workspace/28.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/28.pwrmgr_lowpower_invalid.910166348
Short name T177
Test name
Test status
Simulation time 79060554 ps
CPU time 0.68 seconds
Started Jul 26 06:59:33 PM PDT 24
Finished Jul 26 06:59:34 PM PDT 24
Peak memory 201472 kb
Host smart-680131c6-e0f1-4e4e-9f7a-ae4b2a546533
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910166348 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_lowpower_invali
d.910166348
Directory /workspace/28.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/28.pwrmgr_reset.967433867
Short name T478
Test name
Test status
Simulation time 64153172 ps
CPU time 0.85 seconds
Started Jul 26 06:59:30 PM PDT 24
Finished Jul 26 06:59:31 PM PDT 24
Peak memory 199200 kb
Host smart-a982944a-0d4a-4b77-945c-82ec28df2c80
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967433867 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset.967433867
Directory /workspace/28.pwrmgr_reset/latest

Test location /workspace/coverage/default/28.pwrmgr_reset_invalid.639649358
Short name T223
Test name
Test status
Simulation time 103369544 ps
CPU time 1.03 seconds
Started Jul 26 06:59:33 PM PDT 24
Finished Jul 26 06:59:35 PM PDT 24
Peak memory 209460 kb
Host smart-7dfdf367-7c3d-45d0-93a5-50b42747a53d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639649358 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset_invalid.639649358
Directory /workspace/28.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/28.pwrmgr_sec_cm_rstmgr_intersig_mubi.4036449464
Short name T400
Test name
Test status
Simulation time 100491553 ps
CPU time 0.78 seconds
Started Jul 26 06:59:32 PM PDT 24
Finished Jul 26 06:59:33 PM PDT 24
Peak memory 199404 kb
Host smart-c3e64fc0-c8ab-4bc4-b56d-3c61dbb79bc5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036449464 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4036449464
Directory /workspace/28.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/28.pwrmgr_smoke.3896136405
Short name T379
Test name
Test status
Simulation time 152420846 ps
CPU time 0.61 seconds
Started Jul 26 06:59:32 PM PDT 24
Finished Jul 26 06:59:33 PM PDT 24
Peak memory 198572 kb
Host smart-07770235-2257-48f0-8e9c-01b77d163344
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896136405 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_smoke.3896136405
Directory /workspace/28.pwrmgr_smoke/latest

Test location /workspace/coverage/default/29.pwrmgr_aborted_low_power.464488417
Short name T423
Test name
Test status
Simulation time 26957781 ps
CPU time 0.72 seconds
Started Jul 26 06:59:31 PM PDT 24
Finished Jul 26 06:59:32 PM PDT 24
Peak memory 198668 kb
Host smart-0b14a148-56ba-4b95-ab8b-58c0a11f38a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464488417 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_aborted_low_power.464488417
Directory /workspace/29.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/29.pwrmgr_disable_rom_integrity_check.2195759400
Short name T141
Test name
Test status
Simulation time 49043499 ps
CPU time 0.8 seconds
Started Jul 26 06:59:44 PM PDT 24
Finished Jul 26 06:59:45 PM PDT 24
Peak memory 199220 kb
Host smart-6faba838-fbb0-4768-a8fe-bed28b81cbda
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195759400 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_dis
able_rom_integrity_check.2195759400
Directory /workspace/29.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/29.pwrmgr_esc_clk_rst_malfunc.454290608
Short name T397
Test name
Test status
Simulation time 43387090 ps
CPU time 0.64 seconds
Started Jul 26 06:59:40 PM PDT 24
Finished Jul 26 06:59:41 PM PDT 24
Peak memory 197608 kb
Host smart-8539c024-d005-4c41-910e-a6bcec628aec
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454290608 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_esc_clk_rst_
malfunc.454290608
Directory /workspace/29.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/29.pwrmgr_escalation_timeout.1072994564
Short name T422
Test name
Test status
Simulation time 208553423 ps
CPU time 0.94 seconds
Started Jul 26 06:59:42 PM PDT 24
Finished Jul 26 06:59:43 PM PDT 24
Peak memory 198164 kb
Host smart-3ae0ba6b-d496-4b41-9198-28c351b90f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072994564 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_escalation_timeout.1072994564
Directory /workspace/29.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/29.pwrmgr_glitch.297004637
Short name T4
Test name
Test status
Simulation time 47087407 ps
CPU time 0.58 seconds
Started Jul 26 06:59:41 PM PDT 24
Finished Jul 26 06:59:42 PM PDT 24
Peak memory 197972 kb
Host smart-ddfd5b32-519c-498e-97b3-516f0289b805
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297004637 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_glitch.297004637
Directory /workspace/29.pwrmgr_glitch/latest

Test location /workspace/coverage/default/29.pwrmgr_global_esc.32455408
Short name T481
Test name
Test status
Simulation time 72486032 ps
CPU time 0.6 seconds
Started Jul 26 06:59:43 PM PDT 24
Finished Jul 26 06:59:44 PM PDT 24
Peak memory 198076 kb
Host smart-334eef4f-4879-472a-810d-5094663f69d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32455408 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_global_esc.32455408
Directory /workspace/29.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/29.pwrmgr_lowpower_invalid.2619793922
Short name T491
Test name
Test status
Simulation time 52926272 ps
CPU time 0.66 seconds
Started Jul 26 06:59:45 PM PDT 24
Finished Jul 26 06:59:46 PM PDT 24
Peak memory 201460 kb
Host smart-797e4ee6-4904-43ee-a9a1-dda3f608fd0d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619793922 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_lowpower_inval
id.2619793922
Directory /workspace/29.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/29.pwrmgr_reset.2258332046
Short name T214
Test name
Test status
Simulation time 83619286 ps
CPU time 0.86 seconds
Started Jul 26 06:59:31 PM PDT 24
Finished Jul 26 06:59:32 PM PDT 24
Peak memory 198292 kb
Host smart-05f11d4c-4ed4-4973-9823-8f06f4fbb716
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258332046 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset.2258332046
Directory /workspace/29.pwrmgr_reset/latest

Test location /workspace/coverage/default/29.pwrmgr_reset_invalid.1211036196
Short name T585
Test name
Test status
Simulation time 403480563 ps
CPU time 0.78 seconds
Started Jul 26 06:59:42 PM PDT 24
Finished Jul 26 06:59:43 PM PDT 24
Peak memory 209588 kb
Host smart-00346ed7-bf27-413c-9a3d-94c524708a2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211036196 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset_invalid.1211036196
Directory /workspace/29.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/29.pwrmgr_sec_cm_rstmgr_intersig_mubi.2526740162
Short name T474
Test name
Test status
Simulation time 194480398 ps
CPU time 0.75 seconds
Started Jul 26 06:59:31 PM PDT 24
Finished Jul 26 06:59:32 PM PDT 24
Peak memory 198084 kb
Host smart-504d9bf8-6f32-4746-9e1b-e2bd7339ab38
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526740162 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2526740162
Directory /workspace/29.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/29.pwrmgr_smoke.383809548
Short name T34
Test name
Test status
Simulation time 56512179 ps
CPU time 0.64 seconds
Started Jul 26 06:59:30 PM PDT 24
Finished Jul 26 06:59:31 PM PDT 24
Peak memory 198536 kb
Host smart-5a52b6c0-512f-461d-8bb7-53bbb9491e6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383809548 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_smoke.383809548
Directory /workspace/29.pwrmgr_smoke/latest

Test location /workspace/coverage/default/3.pwrmgr_aborted_low_power.2431724558
Short name T343
Test name
Test status
Simulation time 20940423 ps
CPU time 0.65 seconds
Started Jul 26 06:57:45 PM PDT 24
Finished Jul 26 06:57:46 PM PDT 24
Peak memory 199192 kb
Host smart-8db79868-f904-4a6a-8299-bc71623b200d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431724558 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_aborted_low_power.2431724558
Directory /workspace/3.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/3.pwrmgr_disable_rom_integrity_check.1197965341
Short name T473
Test name
Test status
Simulation time 76924625 ps
CPU time 0.64 seconds
Started Jul 26 06:57:47 PM PDT 24
Finished Jul 26 06:57:48 PM PDT 24
Peak memory 198564 kb
Host smart-a27c0e14-cd8c-4d1a-bdd8-89ed7c00a790
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197965341 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_disa
ble_rom_integrity_check.1197965341
Directory /workspace/3.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/3.pwrmgr_esc_clk_rst_malfunc.1431578615
Short name T468
Test name
Test status
Simulation time 38681295 ps
CPU time 0.59 seconds
Started Jul 26 06:57:47 PM PDT 24
Finished Jul 26 06:57:48 PM PDT 24
Peak memory 197352 kb
Host smart-0ab4c091-6cf8-40de-90f8-92c0ef1d3483
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431578615 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_esc_clk_rst_
malfunc.1431578615
Directory /workspace/3.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/3.pwrmgr_escalation_timeout.3507713794
Short name T606
Test name
Test status
Simulation time 578956957 ps
CPU time 0.99 seconds
Started Jul 26 06:57:48 PM PDT 24
Finished Jul 26 06:57:49 PM PDT 24
Peak memory 198108 kb
Host smart-d9b6b2ec-51f3-4a55-9244-69136f02b1a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507713794 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_escalation_timeout.3507713794
Directory /workspace/3.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/3.pwrmgr_glitch.187712397
Short name T466
Test name
Test status
Simulation time 34748470 ps
CPU time 0.59 seconds
Started Jul 26 06:57:45 PM PDT 24
Finished Jul 26 06:57:46 PM PDT 24
Peak memory 198048 kb
Host smart-ac304dfe-bff9-44f7-a3ef-8526f5715c23
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187712397 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_glitch.187712397
Directory /workspace/3.pwrmgr_glitch/latest

Test location /workspace/coverage/default/3.pwrmgr_global_esc.42147318
Short name T577
Test name
Test status
Simulation time 67151785 ps
CPU time 0.6 seconds
Started Jul 26 06:57:47 PM PDT 24
Finished Jul 26 06:57:48 PM PDT 24
Peak memory 198164 kb
Host smart-9199dea7-6bbc-4d08-b669-5b11f921365a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42147318 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_global_esc.42147318
Directory /workspace/3.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/3.pwrmgr_lowpower_invalid.1143100664
Short name T172
Test name
Test status
Simulation time 43776344 ps
CPU time 0.69 seconds
Started Jul 26 06:57:45 PM PDT 24
Finished Jul 26 06:57:46 PM PDT 24
Peak memory 201456 kb
Host smart-1d697d3a-004a-4354-b9a3-889205848649
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143100664 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_lowpower_invali
d.1143100664
Directory /workspace/3.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/3.pwrmgr_reset.492083469
Short name T243
Test name
Test status
Simulation time 54858317 ps
CPU time 0.65 seconds
Started Jul 26 06:57:47 PM PDT 24
Finished Jul 26 06:57:47 PM PDT 24
Peak memory 198300 kb
Host smart-eaa2011e-2a68-4af0-b903-8351be16237b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492083469 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset.492083469
Directory /workspace/3.pwrmgr_reset/latest

Test location /workspace/coverage/default/3.pwrmgr_reset_invalid.2450324009
Short name T306
Test name
Test status
Simulation time 119109517 ps
CPU time 0.88 seconds
Started Jul 26 06:57:46 PM PDT 24
Finished Jul 26 06:57:47 PM PDT 24
Peak memory 209592 kb
Host smart-ded99cd3-ac44-40eb-99c3-a740e07bfe9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450324009 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset_invalid.2450324009
Directory /workspace/3.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm.317588716
Short name T20
Test name
Test status
Simulation time 365438006 ps
CPU time 1.24 seconds
Started Jul 26 06:57:46 PM PDT 24
Finished Jul 26 06:57:48 PM PDT 24
Peak memory 216960 kb
Host smart-d98c5556-0005-45b2-80be-ffb85980c9c4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317588716 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm.317588716
Directory /workspace/3.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm_rstmgr_intersig_mubi.851856358
Short name T32
Test name
Test status
Simulation time 82932911 ps
CPU time 0.69 seconds
Started Jul 26 06:57:47 PM PDT 24
Finished Jul 26 06:57:48 PM PDT 24
Peak memory 198164 kb
Host smart-4ff4e682-d555-4f64-b0a5-7f4b3c456434
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851856358 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.851856358
Directory /workspace/3.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/3.pwrmgr_smoke.1819771542
Short name T321
Test name
Test status
Simulation time 29543401 ps
CPU time 0.69 seconds
Started Jul 26 06:57:48 PM PDT 24
Finished Jul 26 06:57:49 PM PDT 24
Peak memory 199424 kb
Host smart-417d80d8-b439-4f06-b83f-95d02ee160b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819771542 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_smoke.1819771542
Directory /workspace/3.pwrmgr_smoke/latest

Test location /workspace/coverage/default/30.pwrmgr_aborted_low_power.370033450
Short name T103
Test name
Test status
Simulation time 21759502 ps
CPU time 0.64 seconds
Started Jul 26 06:59:41 PM PDT 24
Finished Jul 26 06:59:42 PM PDT 24
Peak memory 198636 kb
Host smart-359d5252-020f-49ea-8c9f-67369e410215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370033450 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_aborted_low_power.370033450
Directory /workspace/30.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/30.pwrmgr_disable_rom_integrity_check.1706007163
Short name T415
Test name
Test status
Simulation time 63431057 ps
CPU time 0.66 seconds
Started Jul 26 06:59:47 PM PDT 24
Finished Jul 26 06:59:48 PM PDT 24
Peak memory 198532 kb
Host smart-a5a59930-33c8-4379-bd14-e77abe0b77eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706007163 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_dis
able_rom_integrity_check.1706007163
Directory /workspace/30.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/30.pwrmgr_esc_clk_rst_malfunc.3930370447
Short name T523
Test name
Test status
Simulation time 38859566 ps
CPU time 0.57 seconds
Started Jul 26 06:59:44 PM PDT 24
Finished Jul 26 06:59:45 PM PDT 24
Peak memory 197468 kb
Host smart-667833d5-82d0-4381-bbee-99d46a76efa9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930370447 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_esc_clk_rst
_malfunc.3930370447
Directory /workspace/30.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/30.pwrmgr_escalation_timeout.1243716599
Short name T363
Test name
Test status
Simulation time 693191425 ps
CPU time 0.97 seconds
Started Jul 26 06:59:45 PM PDT 24
Finished Jul 26 06:59:46 PM PDT 24
Peak memory 198136 kb
Host smart-c7f36eb2-415c-415d-9d8c-7a583ac23c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243716599 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_escalation_timeout.1243716599
Directory /workspace/30.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/30.pwrmgr_glitch.176866808
Short name T288
Test name
Test status
Simulation time 32023936 ps
CPU time 0.65 seconds
Started Jul 26 06:59:40 PM PDT 24
Finished Jul 26 06:59:41 PM PDT 24
Peak memory 197436 kb
Host smart-db37e787-3e93-4d14-8c8b-e7e93ed294b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176866808 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_glitch.176866808
Directory /workspace/30.pwrmgr_glitch/latest

Test location /workspace/coverage/default/30.pwrmgr_global_esc.2752287313
Short name T470
Test name
Test status
Simulation time 28570140 ps
CPU time 0.62 seconds
Started Jul 26 06:59:43 PM PDT 24
Finished Jul 26 06:59:44 PM PDT 24
Peak memory 198496 kb
Host smart-103ffb57-2c43-491b-88f4-5d4e34f5347b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752287313 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_global_esc.2752287313
Directory /workspace/30.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/30.pwrmgr_reset.3861298425
Short name T394
Test name
Test status
Simulation time 142236141 ps
CPU time 0.74 seconds
Started Jul 26 06:59:45 PM PDT 24
Finished Jul 26 06:59:45 PM PDT 24
Peak memory 199244 kb
Host smart-a46f95a9-b531-4b3c-9f18-4be3185836b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861298425 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset.3861298425
Directory /workspace/30.pwrmgr_reset/latest

Test location /workspace/coverage/default/30.pwrmgr_reset_invalid.1252243878
Short name T230
Test name
Test status
Simulation time 168510682 ps
CPU time 0.76 seconds
Started Jul 26 06:59:42 PM PDT 24
Finished Jul 26 06:59:43 PM PDT 24
Peak memory 201300 kb
Host smart-c1bd6ec8-fda6-469e-9c46-357c59949c86
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252243878 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset_invalid.1252243878
Directory /workspace/30.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/30.pwrmgr_sec_cm_rstmgr_intersig_mubi.2709126678
Short name T248
Test name
Test status
Simulation time 57929743 ps
CPU time 0.83 seconds
Started Jul 26 06:59:41 PM PDT 24
Finished Jul 26 06:59:42 PM PDT 24
Peak memory 198428 kb
Host smart-0198bc21-f473-47d6-b3fd-07540a3978ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709126678 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2709126678
Directory /workspace/30.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/30.pwrmgr_smoke.2783742182
Short name T565
Test name
Test status
Simulation time 116054866 ps
CPU time 0.64 seconds
Started Jul 26 06:59:45 PM PDT 24
Finished Jul 26 06:59:46 PM PDT 24
Peak memory 198592 kb
Host smart-0781b2ed-4c2f-46e0-be9b-bd02de9855a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783742182 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_smoke.2783742182
Directory /workspace/30.pwrmgr_smoke/latest

Test location /workspace/coverage/default/31.pwrmgr_aborted_low_power.2927106883
Short name T17
Test name
Test status
Simulation time 101940885 ps
CPU time 0.8 seconds
Started Jul 26 06:59:43 PM PDT 24
Finished Jul 26 06:59:44 PM PDT 24
Peak memory 200104 kb
Host smart-78a51b65-87fe-4985-91f9-2f66a44288b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927106883 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_aborted_low_power.2927106883
Directory /workspace/31.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/31.pwrmgr_disable_rom_integrity_check.2460723847
Short name T408
Test name
Test status
Simulation time 65175391 ps
CPU time 0.67 seconds
Started Jul 26 06:59:42 PM PDT 24
Finished Jul 26 06:59:43 PM PDT 24
Peak memory 198396 kb
Host smart-d609d50d-1022-474a-a656-9bf5673d4503
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460723847 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_dis
able_rom_integrity_check.2460723847
Directory /workspace/31.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/31.pwrmgr_esc_clk_rst_malfunc.2358728718
Short name T521
Test name
Test status
Simulation time 58455787 ps
CPU time 0.57 seconds
Started Jul 26 06:59:42 PM PDT 24
Finished Jul 26 06:59:43 PM PDT 24
Peak memory 198084 kb
Host smart-3d70f89e-88d8-4d56-966a-18fd1d9a3ad5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358728718 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_esc_clk_rst
_malfunc.2358728718
Directory /workspace/31.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/31.pwrmgr_escalation_timeout.3817515767
Short name T282
Test name
Test status
Simulation time 836189499 ps
CPU time 0.95 seconds
Started Jul 26 06:59:44 PM PDT 24
Finished Jul 26 06:59:45 PM PDT 24
Peak memory 198172 kb
Host smart-9e4dca15-f64f-40f6-aeda-277227dbc459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817515767 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_escalation_timeout.3817515767
Directory /workspace/31.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/31.pwrmgr_glitch.3518084272
Short name T594
Test name
Test status
Simulation time 40515700 ps
CPU time 0.59 seconds
Started Jul 26 06:59:45 PM PDT 24
Finished Jul 26 06:59:45 PM PDT 24
Peak memory 198252 kb
Host smart-7a6d6f19-4e81-4423-bdfa-4e501676912d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518084272 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_glitch.3518084272
Directory /workspace/31.pwrmgr_glitch/latest

Test location /workspace/coverage/default/31.pwrmgr_global_esc.4145775500
Short name T607
Test name
Test status
Simulation time 49965572 ps
CPU time 0.64 seconds
Started Jul 26 06:59:40 PM PDT 24
Finished Jul 26 06:59:41 PM PDT 24
Peak memory 198148 kb
Host smart-2ded9a5e-ae31-46f9-8cbc-7c46e8d49611
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145775500 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_global_esc.4145775500
Directory /workspace/31.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/31.pwrmgr_lowpower_invalid.643260042
Short name T198
Test name
Test status
Simulation time 50792673 ps
CPU time 0.66 seconds
Started Jul 26 06:59:43 PM PDT 24
Finished Jul 26 06:59:44 PM PDT 24
Peak memory 201408 kb
Host smart-323fa400-c054-4bc2-9b63-01deaa229b49
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643260042 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_lowpower_invali
d.643260042
Directory /workspace/31.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/31.pwrmgr_reset.219247243
Short name T240
Test name
Test status
Simulation time 70771483 ps
CPU time 0.66 seconds
Started Jul 26 06:59:44 PM PDT 24
Finished Jul 26 06:59:45 PM PDT 24
Peak memory 199152 kb
Host smart-8b4af43f-f0ab-41a6-a6c3-50619362ce4f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219247243 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset.219247243
Directory /workspace/31.pwrmgr_reset/latest

Test location /workspace/coverage/default/31.pwrmgr_reset_invalid.1759807416
Short name T546
Test name
Test status
Simulation time 194635142 ps
CPU time 0.79 seconds
Started Jul 26 06:59:44 PM PDT 24
Finished Jul 26 06:59:45 PM PDT 24
Peak memory 209524 kb
Host smart-31f75951-2ad5-4a06-9eae-8745cd0da629
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759807416 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset_invalid.1759807416
Directory /workspace/31.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/31.pwrmgr_sec_cm_rstmgr_intersig_mubi.4077496625
Short name T301
Test name
Test status
Simulation time 153481466 ps
CPU time 0.84 seconds
Started Jul 26 06:59:41 PM PDT 24
Finished Jul 26 06:59:42 PM PDT 24
Peak memory 199392 kb
Host smart-a180693c-4953-4601-b697-45fb2b573d89
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077496625 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4077496625
Directory /workspace/31.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/31.pwrmgr_smoke.3405353378
Short name T318
Test name
Test status
Simulation time 34321403 ps
CPU time 0.64 seconds
Started Jul 26 06:59:44 PM PDT 24
Finished Jul 26 06:59:44 PM PDT 24
Peak memory 199416 kb
Host smart-a0b697f6-a4df-400c-acbc-edd7959c64d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405353378 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_smoke.3405353378
Directory /workspace/31.pwrmgr_smoke/latest

Test location /workspace/coverage/default/32.pwrmgr_aborted_low_power.326018803
Short name T285
Test name
Test status
Simulation time 145446205 ps
CPU time 0.69 seconds
Started Jul 26 06:59:52 PM PDT 24
Finished Jul 26 06:59:53 PM PDT 24
Peak memory 198716 kb
Host smart-656b1474-5a1e-4fd2-9ef9-4289418123ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326018803 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_aborted_low_power.326018803
Directory /workspace/32.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/32.pwrmgr_disable_rom_integrity_check.774203465
Short name T165
Test name
Test status
Simulation time 79399852 ps
CPU time 0.66 seconds
Started Jul 26 06:59:53 PM PDT 24
Finished Jul 26 06:59:54 PM PDT 24
Peak memory 198536 kb
Host smart-c30fdb67-32e5-404a-ad4d-cdc7c547e835
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774203465 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_disa
ble_rom_integrity_check.774203465
Directory /workspace/32.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/32.pwrmgr_esc_clk_rst_malfunc.1832519560
Short name T364
Test name
Test status
Simulation time 32079623 ps
CPU time 0.62 seconds
Started Jul 26 06:59:54 PM PDT 24
Finished Jul 26 06:59:55 PM PDT 24
Peak memory 198132 kb
Host smart-bf602bcf-2375-44a6-943f-78a44579280f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832519560 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_esc_clk_rst
_malfunc.1832519560
Directory /workspace/32.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/32.pwrmgr_escalation_timeout.2633882717
Short name T460
Test name
Test status
Simulation time 600942619 ps
CPU time 1.15 seconds
Started Jul 26 06:59:46 PM PDT 24
Finished Jul 26 06:59:47 PM PDT 24
Peak memory 198156 kb
Host smart-07ed8137-7293-40c2-96ce-9bae1c69dd8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633882717 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_escalation_timeout.2633882717
Directory /workspace/32.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/32.pwrmgr_glitch.1658080995
Short name T2
Test name
Test status
Simulation time 52098917 ps
CPU time 0.64 seconds
Started Jul 26 06:59:45 PM PDT 24
Finished Jul 26 06:59:46 PM PDT 24
Peak memory 197460 kb
Host smart-014be25a-bf41-477d-970d-3468b5e28f7e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658080995 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_glitch.1658080995
Directory /workspace/32.pwrmgr_glitch/latest

Test location /workspace/coverage/default/32.pwrmgr_global_esc.3666419174
Short name T410
Test name
Test status
Simulation time 52134368 ps
CPU time 0.68 seconds
Started Jul 26 06:59:46 PM PDT 24
Finished Jul 26 06:59:47 PM PDT 24
Peak memory 198108 kb
Host smart-f82b8dbc-647d-4a2e-96ff-6fba7bba552e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666419174 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_global_esc.3666419174
Directory /workspace/32.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/32.pwrmgr_reset.2983007013
Short name T485
Test name
Test status
Simulation time 75294880 ps
CPU time 0.74 seconds
Started Jul 26 06:59:43 PM PDT 24
Finished Jul 26 06:59:44 PM PDT 24
Peak memory 199124 kb
Host smart-b6324643-3c12-491f-8a60-a9272e7fd630
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983007013 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset.2983007013
Directory /workspace/32.pwrmgr_reset/latest

Test location /workspace/coverage/default/32.pwrmgr_reset_invalid.2951789816
Short name T626
Test name
Test status
Simulation time 163253584 ps
CPU time 0.82 seconds
Started Jul 26 06:59:46 PM PDT 24
Finished Jul 26 06:59:48 PM PDT 24
Peak memory 209528 kb
Host smart-e0ef4d50-dbae-4c55-8870-b70bd1e836ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951789816 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset_invalid.2951789816
Directory /workspace/32.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/32.pwrmgr_sec_cm_rstmgr_intersig_mubi.929767360
Short name T231
Test name
Test status
Simulation time 75348610 ps
CPU time 0.93 seconds
Started Jul 26 06:59:45 PM PDT 24
Finished Jul 26 06:59:47 PM PDT 24
Peak memory 199376 kb
Host smart-ddc0a8ef-c549-42c8-99af-2c51942e3965
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929767360 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_rstmgr_intersig_
mubi.929767360
Directory /workspace/32.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/32.pwrmgr_smoke.3972920423
Short name T529
Test name
Test status
Simulation time 59497105 ps
CPU time 0.64 seconds
Started Jul 26 06:59:45 PM PDT 24
Finished Jul 26 06:59:45 PM PDT 24
Peak memory 198580 kb
Host smart-d5225548-aed8-4a7f-950e-61ce0da822a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972920423 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_smoke.3972920423
Directory /workspace/32.pwrmgr_smoke/latest

Test location /workspace/coverage/default/33.pwrmgr_aborted_low_power.730276560
Short name T505
Test name
Test status
Simulation time 124868423 ps
CPU time 0.78 seconds
Started Jul 26 06:59:53 PM PDT 24
Finished Jul 26 06:59:54 PM PDT 24
Peak memory 200072 kb
Host smart-d7aaed7c-0af0-448e-b4eb-6c8b9fcc8802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730276560 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_aborted_low_power.730276560
Directory /workspace/33.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/33.pwrmgr_disable_rom_integrity_check.2761310096
Short name T148
Test name
Test status
Simulation time 75031176 ps
CPU time 0.68 seconds
Started Jul 26 06:59:46 PM PDT 24
Finished Jul 26 06:59:47 PM PDT 24
Peak memory 198496 kb
Host smart-2ab685e2-c3c9-47bc-90af-1a2c9364a48b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761310096 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_dis
able_rom_integrity_check.2761310096
Directory /workspace/33.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/33.pwrmgr_esc_clk_rst_malfunc.4058946002
Short name T426
Test name
Test status
Simulation time 44399497 ps
CPU time 0.63 seconds
Started Jul 26 06:59:54 PM PDT 24
Finished Jul 26 06:59:55 PM PDT 24
Peak memory 198144 kb
Host smart-e000d816-1916-469a-8b02-9049436a50a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058946002 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_esc_clk_rst
_malfunc.4058946002
Directory /workspace/33.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/33.pwrmgr_escalation_timeout.240458379
Short name T13
Test name
Test status
Simulation time 302817209 ps
CPU time 1.01 seconds
Started Jul 26 06:59:45 PM PDT 24
Finished Jul 26 06:59:47 PM PDT 24
Peak memory 198172 kb
Host smart-4b2e72a9-afbf-4811-91c5-22ac9f1d7ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240458379 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_escalation_timeout.240458379
Directory /workspace/33.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/33.pwrmgr_glitch.2636185592
Short name T620
Test name
Test status
Simulation time 79490421 ps
CPU time 0.61 seconds
Started Jul 26 06:59:52 PM PDT 24
Finished Jul 26 06:59:53 PM PDT 24
Peak memory 198096 kb
Host smart-fa384395-9827-4726-ab41-bef180b74e45
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636185592 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_glitch.2636185592
Directory /workspace/33.pwrmgr_glitch/latest

Test location /workspace/coverage/default/33.pwrmgr_global_esc.215004639
Short name T520
Test name
Test status
Simulation time 47159123 ps
CPU time 0.66 seconds
Started Jul 26 06:59:55 PM PDT 24
Finished Jul 26 06:59:56 PM PDT 24
Peak memory 198200 kb
Host smart-2ab076df-103e-4c17-b276-716beb7ddfb9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215004639 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_global_esc.215004639
Directory /workspace/33.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/33.pwrmgr_lowpower_invalid.4293028951
Short name T578
Test name
Test status
Simulation time 48308988 ps
CPU time 0.67 seconds
Started Jul 26 06:59:46 PM PDT 24
Finished Jul 26 06:59:47 PM PDT 24
Peak memory 201476 kb
Host smart-9e127f60-8266-4056-884b-21d0af98b03e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293028951 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_lowpower_inval
id.4293028951
Directory /workspace/33.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/33.pwrmgr_reset.2442295979
Short name T41
Test name
Test status
Simulation time 226099443 ps
CPU time 0.87 seconds
Started Jul 26 06:59:47 PM PDT 24
Finished Jul 26 06:59:48 PM PDT 24
Peak memory 199116 kb
Host smart-3055a01e-b97d-40dd-a6e6-95b0d06310ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442295979 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset.2442295979
Directory /workspace/33.pwrmgr_reset/latest

Test location /workspace/coverage/default/33.pwrmgr_reset_invalid.1010861961
Short name T277
Test name
Test status
Simulation time 100413187 ps
CPU time 0.93 seconds
Started Jul 26 06:59:50 PM PDT 24
Finished Jul 26 06:59:52 PM PDT 24
Peak memory 209376 kb
Host smart-cea0ea2d-6765-4046-908e-93987657e1b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010861961 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset_invalid.1010861961
Directory /workspace/33.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/33.pwrmgr_sec_cm_ctrl_config_regwen.3277012969
Short name T190
Test name
Test status
Simulation time 28818857 ps
CPU time 0.71 seconds
Started Jul 26 06:59:46 PM PDT 24
Finished Jul 26 06:59:46 PM PDT 24
Peak memory 198588 kb
Host smart-f4025b8b-ac64-4645-a1d7-90c6738fafca
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277012969 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_
cm_ctrl_config_regwen.3277012969
Directory /workspace/33.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/33.pwrmgr_sec_cm_rstmgr_intersig_mubi.3504018320
Short name T373
Test name
Test status
Simulation time 87115895 ps
CPU time 0.83 seconds
Started Jul 26 06:59:47 PM PDT 24
Finished Jul 26 06:59:48 PM PDT 24
Peak memory 199244 kb
Host smart-4fb70c51-9b71-440f-ad5e-b01ed4ffb438
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504018320 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3504018320
Directory /workspace/33.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/33.pwrmgr_smoke.3383260260
Short name T365
Test name
Test status
Simulation time 28112494 ps
CPU time 0.7 seconds
Started Jul 26 06:59:47 PM PDT 24
Finished Jul 26 06:59:48 PM PDT 24
Peak memory 199408 kb
Host smart-4f5eb027-bce2-416e-b83b-cc89c5f08f72
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383260260 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_smoke.3383260260
Directory /workspace/33.pwrmgr_smoke/latest

Test location /workspace/coverage/default/34.pwrmgr_aborted_low_power.1970330385
Short name T449
Test name
Test status
Simulation time 270491040 ps
CPU time 0.7 seconds
Started Jul 26 06:59:52 PM PDT 24
Finished Jul 26 06:59:53 PM PDT 24
Peak memory 198700 kb
Host smart-ceb0cf75-242a-404a-b09d-825d160f50c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970330385 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_aborted_low_power.1970330385
Directory /workspace/34.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/34.pwrmgr_disable_rom_integrity_check.2031231523
Short name T544
Test name
Test status
Simulation time 51988991 ps
CPU time 0.76 seconds
Started Jul 26 06:59:48 PM PDT 24
Finished Jul 26 06:59:49 PM PDT 24
Peak memory 198492 kb
Host smart-c2f7713c-0a31-4479-af43-936ed446d7b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031231523 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_dis
able_rom_integrity_check.2031231523
Directory /workspace/34.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/34.pwrmgr_esc_clk_rst_malfunc.3859466563
Short name T238
Test name
Test status
Simulation time 29467211 ps
CPU time 0.62 seconds
Started Jul 26 06:59:53 PM PDT 24
Finished Jul 26 06:59:54 PM PDT 24
Peak memory 198068 kb
Host smart-a2e022cb-aed2-4ff3-b785-510b55784a18
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859466563 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_esc_clk_rst
_malfunc.3859466563
Directory /workspace/34.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/34.pwrmgr_escalation_timeout.2889011043
Short name T455
Test name
Test status
Simulation time 476871950 ps
CPU time 0.97 seconds
Started Jul 26 06:59:52 PM PDT 24
Finished Jul 26 06:59:54 PM PDT 24
Peak memory 198140 kb
Host smart-1ca93fcd-6a10-4798-8d7f-912fa52ede9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889011043 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_escalation_timeout.2889011043
Directory /workspace/34.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/34.pwrmgr_glitch.3675639660
Short name T263
Test name
Test status
Simulation time 41021526 ps
CPU time 0.65 seconds
Started Jul 26 06:59:49 PM PDT 24
Finished Jul 26 06:59:50 PM PDT 24
Peak memory 198168 kb
Host smart-bfca08a4-da82-4562-aafe-25b9ec7dde8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675639660 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_glitch.3675639660
Directory /workspace/34.pwrmgr_glitch/latest

Test location /workspace/coverage/default/34.pwrmgr_global_esc.1085878878
Short name T580
Test name
Test status
Simulation time 28754944 ps
CPU time 0.6 seconds
Started Jul 26 06:59:47 PM PDT 24
Finished Jul 26 06:59:48 PM PDT 24
Peak memory 198092 kb
Host smart-4ce4f78e-532e-4fca-a4a1-accbae8c5309
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085878878 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_global_esc.1085878878
Directory /workspace/34.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/34.pwrmgr_lowpower_invalid.4074870193
Short name T202
Test name
Test status
Simulation time 99025658 ps
CPU time 0.64 seconds
Started Jul 26 06:59:54 PM PDT 24
Finished Jul 26 06:59:55 PM PDT 24
Peak memory 201396 kb
Host smart-d32317c8-a449-448c-a443-e2afd8d86dc4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074870193 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_lowpower_inval
id.4074870193
Directory /workspace/34.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/34.pwrmgr_reset.2660445712
Short name T307
Test name
Test status
Simulation time 71035259 ps
CPU time 0.89 seconds
Started Jul 26 06:59:48 PM PDT 24
Finished Jul 26 06:59:49 PM PDT 24
Peak memory 198532 kb
Host smart-4f6a5f38-9f68-413d-9ac3-3e8f47e7f55e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660445712 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset.2660445712
Directory /workspace/34.pwrmgr_reset/latest

Test location /workspace/coverage/default/34.pwrmgr_reset_invalid.601719949
Short name T392
Test name
Test status
Simulation time 105595492 ps
CPU time 0.89 seconds
Started Jul 26 06:59:46 PM PDT 24
Finished Jul 26 06:59:47 PM PDT 24
Peak memory 209584 kb
Host smart-acc9edb0-845c-4d3c-994e-2ef1648df90b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601719949 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset_invalid.601719949
Directory /workspace/34.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/34.pwrmgr_sec_cm_rstmgr_intersig_mubi.191222380
Short name T507
Test name
Test status
Simulation time 110381688 ps
CPU time 0.74 seconds
Started Jul 26 06:59:53 PM PDT 24
Finished Jul 26 06:59:54 PM PDT 24
Peak memory 198192 kb
Host smart-49d2c6f1-ad71-4a46-b50d-0434b2f3eb2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191222380 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_rstmgr_intersig_
mubi.191222380
Directory /workspace/34.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/34.pwrmgr_smoke.3477197946
Short name T58
Test name
Test status
Simulation time 42509048 ps
CPU time 0.66 seconds
Started Jul 26 06:59:47 PM PDT 24
Finished Jul 26 06:59:48 PM PDT 24
Peak memory 199488 kb
Host smart-60ed3c22-36a3-4a64-83ea-95a89f5793ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477197946 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_smoke.3477197946
Directory /workspace/34.pwrmgr_smoke/latest

Test location /workspace/coverage/default/35.pwrmgr_aborted_low_power.687587791
Short name T514
Test name
Test status
Simulation time 68899605 ps
CPU time 0.9 seconds
Started Jul 26 06:59:56 PM PDT 24
Finished Jul 26 06:59:58 PM PDT 24
Peak memory 200924 kb
Host smart-b975e272-1035-4b03-bde8-24c4c88c41d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687587791 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_aborted_low_power.687587791
Directory /workspace/35.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/35.pwrmgr_disable_rom_integrity_check.8750271
Short name T581
Test name
Test status
Simulation time 59602579 ps
CPU time 0.81 seconds
Started Jul 26 06:59:55 PM PDT 24
Finished Jul 26 06:59:56 PM PDT 24
Peak memory 198576 kb
Host smart-e200b428-7ff3-41b4-b1be-58d67f4a8df0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8750271 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_inte
grity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_disabl
e_rom_integrity_check.8750271
Directory /workspace/35.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/35.pwrmgr_esc_clk_rst_malfunc.1009809411
Short name T261
Test name
Test status
Simulation time 29749092 ps
CPU time 0.63 seconds
Started Jul 26 06:59:56 PM PDT 24
Finished Jul 26 06:59:57 PM PDT 24
Peak memory 198060 kb
Host smart-c1d2aa42-922e-4c7f-b985-62de8926fe6f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009809411 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_esc_clk_rst
_malfunc.1009809411
Directory /workspace/35.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/35.pwrmgr_escalation_timeout.1114908630
Short name T372
Test name
Test status
Simulation time 165409163 ps
CPU time 1.01 seconds
Started Jul 26 06:59:51 PM PDT 24
Finished Jul 26 06:59:52 PM PDT 24
Peak memory 198156 kb
Host smart-81796ac3-ca87-4615-ba2c-69dc85d7b146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114908630 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_escalation_timeout.1114908630
Directory /workspace/35.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/35.pwrmgr_glitch.1267710427
Short name T251
Test name
Test status
Simulation time 121888486 ps
CPU time 0.62 seconds
Started Jul 26 06:59:57 PM PDT 24
Finished Jul 26 06:59:57 PM PDT 24
Peak memory 198092 kb
Host smart-d6fb2401-07fc-4510-b91f-12874871bf9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267710427 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_glitch.1267710427
Directory /workspace/35.pwrmgr_glitch/latest

Test location /workspace/coverage/default/35.pwrmgr_global_esc.1156120609
Short name T480
Test name
Test status
Simulation time 58979337 ps
CPU time 0.69 seconds
Started Jul 26 06:59:58 PM PDT 24
Finished Jul 26 06:59:59 PM PDT 24
Peak memory 198464 kb
Host smart-ade6dc18-3b2d-4bdd-9e86-78fa876a0c1d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156120609 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_global_esc.1156120609
Directory /workspace/35.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/35.pwrmgr_lowpower_invalid.3309874037
Short name T590
Test name
Test status
Simulation time 81815844 ps
CPU time 0.67 seconds
Started Jul 26 06:59:56 PM PDT 24
Finished Jul 26 06:59:56 PM PDT 24
Peak memory 201352 kb
Host smart-c025dab8-9696-4ca6-a075-ab66568f0010
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309874037 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_lowpower_inval
id.3309874037
Directory /workspace/35.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/35.pwrmgr_reset.1385840337
Short name T574
Test name
Test status
Simulation time 88753901 ps
CPU time 0.78 seconds
Started Jul 26 06:59:55 PM PDT 24
Finished Jul 26 06:59:56 PM PDT 24
Peak memory 199188 kb
Host smart-cc4dfa6e-c911-4fa4-a042-8eb1025d4a6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385840337 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset.1385840337
Directory /workspace/35.pwrmgr_reset/latest

Test location /workspace/coverage/default/35.pwrmgr_reset_invalid.1340013821
Short name T537
Test name
Test status
Simulation time 105450523 ps
CPU time 1.02 seconds
Started Jul 26 06:59:53 PM PDT 24
Finished Jul 26 06:59:54 PM PDT 24
Peak memory 209496 kb
Host smart-ecbe684d-cbb0-4d5a-a39e-d7584573449d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340013821 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset_invalid.1340013821
Directory /workspace/35.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/35.pwrmgr_sec_cm_rstmgr_intersig_mubi.982573953
Short name T1
Test name
Test status
Simulation time 76482620 ps
CPU time 0.71 seconds
Started Jul 26 06:59:56 PM PDT 24
Finished Jul 26 06:59:57 PM PDT 24
Peak memory 198128 kb
Host smart-9712cdb4-d634-49fb-8460-e7e130e14a61
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982573953 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_rstmgr_intersig_
mubi.982573953
Directory /workspace/35.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/35.pwrmgr_smoke.3170086958
Short name T540
Test name
Test status
Simulation time 66306581 ps
CPU time 0.62 seconds
Started Jul 26 06:59:56 PM PDT 24
Finished Jul 26 06:59:56 PM PDT 24
Peak memory 198696 kb
Host smart-2843b0f8-5323-499e-91ae-1ebb184990cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170086958 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_smoke.3170086958
Directory /workspace/35.pwrmgr_smoke/latest

Test location /workspace/coverage/default/36.pwrmgr_aborted_low_power.2160955585
Short name T276
Test name
Test status
Simulation time 74420597 ps
CPU time 0.75 seconds
Started Jul 26 06:59:53 PM PDT 24
Finished Jul 26 06:59:54 PM PDT 24
Peak memory 200088 kb
Host smart-4fe1da78-92e6-4c1c-80bb-c605345dadc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160955585 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_aborted_low_power.2160955585
Directory /workspace/36.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/36.pwrmgr_disable_rom_integrity_check.1972253057
Short name T517
Test name
Test status
Simulation time 44378160 ps
CPU time 0.8 seconds
Started Jul 26 07:00:03 PM PDT 24
Finished Jul 26 07:00:07 PM PDT 24
Peak memory 199220 kb
Host smart-ca0ac28a-70f2-4dfb-810f-e13987ed117d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972253057 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_dis
able_rom_integrity_check.1972253057
Directory /workspace/36.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/36.pwrmgr_esc_clk_rst_malfunc.691658084
Short name T551
Test name
Test status
Simulation time 37772629 ps
CPU time 0.57 seconds
Started Jul 26 06:59:52 PM PDT 24
Finished Jul 26 06:59:53 PM PDT 24
Peak memory 198084 kb
Host smart-213e7361-e11c-4cb5-8b79-363b2ba9c3c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691658084 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_esc_clk_rst_
malfunc.691658084
Directory /workspace/36.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/36.pwrmgr_escalation_timeout.683624522
Short name T554
Test name
Test status
Simulation time 163402918 ps
CPU time 1 seconds
Started Jul 26 07:00:02 PM PDT 24
Finished Jul 26 07:00:07 PM PDT 24
Peak memory 198168 kb
Host smart-1e80ac80-46f0-4bfa-849e-f1aac0352d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683624522 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_escalation_timeout.683624522
Directory /workspace/36.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/36.pwrmgr_glitch.4242476464
Short name T239
Test name
Test status
Simulation time 50358233 ps
CPU time 0.7 seconds
Started Jul 26 07:00:03 PM PDT 24
Finished Jul 26 07:00:07 PM PDT 24
Peak memory 198248 kb
Host smart-b8c2fa2c-0dd0-48c4-a453-3938cdfa6dac
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242476464 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_glitch.4242476464
Directory /workspace/36.pwrmgr_glitch/latest

Test location /workspace/coverage/default/36.pwrmgr_global_esc.864284565
Short name T504
Test name
Test status
Simulation time 66532343 ps
CPU time 0.61 seconds
Started Jul 26 07:00:02 PM PDT 24
Finished Jul 26 07:00:07 PM PDT 24
Peak memory 198416 kb
Host smart-e9626382-88f1-4608-a8b6-ab2d7b93a793
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864284565 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_global_esc.864284565
Directory /workspace/36.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/36.pwrmgr_lowpower_invalid.1283488017
Short name T175
Test name
Test status
Simulation time 40234895 ps
CPU time 0.73 seconds
Started Jul 26 07:00:05 PM PDT 24
Finished Jul 26 07:00:07 PM PDT 24
Peak memory 201392 kb
Host smart-eec8de45-e3b9-43be-9d02-bd2df59f9346
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283488017 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_lowpower_inval
id.1283488017
Directory /workspace/36.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/36.pwrmgr_reset.14612774
Short name T497
Test name
Test status
Simulation time 54303379 ps
CPU time 0.76 seconds
Started Jul 26 06:59:54 PM PDT 24
Finished Jul 26 06:59:55 PM PDT 24
Peak memory 198364 kb
Host smart-108fcb3a-2106-4a04-a77c-33dfa20bb440
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14612774 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset.14612774
Directory /workspace/36.pwrmgr_reset/latest

Test location /workspace/coverage/default/36.pwrmgr_reset_invalid.2821989849
Short name T439
Test name
Test status
Simulation time 172150012 ps
CPU time 0.78 seconds
Started Jul 26 07:00:01 PM PDT 24
Finished Jul 26 07:00:02 PM PDT 24
Peak memory 209576 kb
Host smart-0a5b4a23-0cb3-4908-ade9-2ed4d96ed35c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821989849 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset_invalid.2821989849
Directory /workspace/36.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/36.pwrmgr_sec_cm_rstmgr_intersig_mubi.1937851297
Short name T477
Test name
Test status
Simulation time 51673626 ps
CPU time 0.82 seconds
Started Jul 26 06:59:52 PM PDT 24
Finished Jul 26 06:59:54 PM PDT 24
Peak memory 198124 kb
Host smart-653254f8-5dee-4a5e-9167-6e306ed988fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937851297 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1937851297
Directory /workspace/36.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/36.pwrmgr_smoke.2313914769
Short name T622
Test name
Test status
Simulation time 41693493 ps
CPU time 0.68 seconds
Started Jul 26 06:59:56 PM PDT 24
Finished Jul 26 06:59:57 PM PDT 24
Peak memory 198496 kb
Host smart-a6daafd0-7890-4036-91a9-3121a6535127
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313914769 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_smoke.2313914769
Directory /workspace/36.pwrmgr_smoke/latest

Test location /workspace/coverage/default/37.pwrmgr_aborted_low_power.1819834783
Short name T93
Test name
Test status
Simulation time 26333363 ps
CPU time 0.79 seconds
Started Jul 26 07:00:02 PM PDT 24
Finished Jul 26 07:00:07 PM PDT 24
Peak memory 198960 kb
Host smart-12e9161f-8acf-443b-95d9-487ab329ab8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819834783 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_aborted_low_power.1819834783
Directory /workspace/37.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/37.pwrmgr_disable_rom_integrity_check.3750128831
Short name T341
Test name
Test status
Simulation time 63933039 ps
CPU time 0.83 seconds
Started Jul 26 07:00:12 PM PDT 24
Finished Jul 26 07:00:13 PM PDT 24
Peak memory 199140 kb
Host smart-93fa1258-37cf-44cd-8d74-d943523a224c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750128831 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_dis
able_rom_integrity_check.3750128831
Directory /workspace/37.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/37.pwrmgr_esc_clk_rst_malfunc.3544347705
Short name T316
Test name
Test status
Simulation time 39778861 ps
CPU time 0.65 seconds
Started Jul 26 07:00:03 PM PDT 24
Finished Jul 26 07:00:07 PM PDT 24
Peak memory 197388 kb
Host smart-b7ca4abf-b3ec-48a1-94f7-3f8dc127df47
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544347705 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_esc_clk_rst
_malfunc.3544347705
Directory /workspace/37.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/37.pwrmgr_escalation_timeout.26931014
Short name T292
Test name
Test status
Simulation time 601181643 ps
CPU time 0.95 seconds
Started Jul 26 07:00:04 PM PDT 24
Finished Jul 26 07:00:07 PM PDT 24
Peak memory 198432 kb
Host smart-1653b25c-459b-4b57-bea3-c9d9ec84895e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26931014 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_escalation_timeout.26931014
Directory /workspace/37.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/37.pwrmgr_glitch.3529674722
Short name T303
Test name
Test status
Simulation time 42614462 ps
CPU time 0.6 seconds
Started Jul 26 07:00:04 PM PDT 24
Finished Jul 26 07:00:07 PM PDT 24
Peak memory 197420 kb
Host smart-83ef4d76-619d-432a-ada0-e7b3468ed289
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529674722 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_glitch.3529674722
Directory /workspace/37.pwrmgr_glitch/latest

Test location /workspace/coverage/default/37.pwrmgr_global_esc.3083494565
Short name T525
Test name
Test status
Simulation time 37576837 ps
CPU time 0.64 seconds
Started Jul 26 07:00:02 PM PDT 24
Finished Jul 26 07:00:07 PM PDT 24
Peak memory 198504 kb
Host smart-ee27192e-fa4c-48c1-adde-2013148ff028
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083494565 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_global_esc.3083494565
Directory /workspace/37.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/37.pwrmgr_lowpower_invalid.697209487
Short name T167
Test name
Test status
Simulation time 69858957 ps
CPU time 0.68 seconds
Started Jul 26 07:00:11 PM PDT 24
Finished Jul 26 07:00:12 PM PDT 24
Peak memory 201396 kb
Host smart-5aea8315-6169-40cb-b971-20aaed6352c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697209487 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_lowpower_invali
d.697209487
Directory /workspace/37.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/37.pwrmgr_reset.1455765558
Short name T406
Test name
Test status
Simulation time 64246422 ps
CPU time 0.84 seconds
Started Jul 26 07:00:01 PM PDT 24
Finished Jul 26 07:00:02 PM PDT 24
Peak memory 199132 kb
Host smart-0d0698fc-8f96-4c8e-a007-cdf083c44b83
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455765558 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset.1455765558
Directory /workspace/37.pwrmgr_reset/latest

Test location /workspace/coverage/default/37.pwrmgr_reset_invalid.1566023117
Short name T527
Test name
Test status
Simulation time 107972112 ps
CPU time 1.09 seconds
Started Jul 26 07:00:11 PM PDT 24
Finished Jul 26 07:00:12 PM PDT 24
Peak memory 209496 kb
Host smart-2c63bbba-3e81-4866-ab51-560c1aee1063
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566023117 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset_invalid.1566023117
Directory /workspace/37.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/37.pwrmgr_sec_cm_rstmgr_intersig_mubi.3603310652
Short name T366
Test name
Test status
Simulation time 80100190 ps
CPU time 0.85 seconds
Started Jul 26 07:00:03 PM PDT 24
Finished Jul 26 07:00:07 PM PDT 24
Peak memory 199580 kb
Host smart-ea69daca-cc33-4f01-8d3e-8689742aada1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603310652 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3603310652
Directory /workspace/37.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/37.pwrmgr_smoke.318403824
Short name T448
Test name
Test status
Simulation time 27446808 ps
CPU time 0.65 seconds
Started Jul 26 07:00:01 PM PDT 24
Finished Jul 26 07:00:02 PM PDT 24
Peak memory 199412 kb
Host smart-7991dfdd-89ef-4fe8-b757-d7b7b3c30a59
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318403824 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_smoke.318403824
Directory /workspace/37.pwrmgr_smoke/latest

Test location /workspace/coverage/default/38.pwrmgr_aborted_low_power.1031639196
Short name T553
Test name
Test status
Simulation time 46588284 ps
CPU time 0.96 seconds
Started Jul 26 07:00:13 PM PDT 24
Finished Jul 26 07:00:14 PM PDT 24
Peak memory 200708 kb
Host smart-8b98c067-dfb7-4ce9-9f55-d1aa4cd85489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031639196 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_aborted_low_power.1031639196
Directory /workspace/38.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/38.pwrmgr_disable_rom_integrity_check.1606358111
Short name T530
Test name
Test status
Simulation time 51883989 ps
CPU time 0.66 seconds
Started Jul 26 07:00:11 PM PDT 24
Finished Jul 26 07:00:12 PM PDT 24
Peak memory 198532 kb
Host smart-e48ba4f0-41bd-40de-a22d-72e41ac36140
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606358111 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_dis
able_rom_integrity_check.1606358111
Directory /workspace/38.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/38.pwrmgr_esc_clk_rst_malfunc.4062124198
Short name T11
Test name
Test status
Simulation time 29428047 ps
CPU time 0.62 seconds
Started Jul 26 07:00:11 PM PDT 24
Finished Jul 26 07:00:12 PM PDT 24
Peak memory 198000 kb
Host smart-4f1f36ea-a5f7-4898-8790-8719ba80750d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062124198 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_esc_clk_rst
_malfunc.4062124198
Directory /workspace/38.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/38.pwrmgr_escalation_timeout.1246986794
Short name T324
Test name
Test status
Simulation time 168811179 ps
CPU time 1.02 seconds
Started Jul 26 07:00:18 PM PDT 24
Finished Jul 26 07:00:19 PM PDT 24
Peak memory 198444 kb
Host smart-58b5b90a-1642-4c84-9af0-4f4bd2488104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246986794 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_escalation_timeout.1246986794
Directory /workspace/38.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/38.pwrmgr_glitch.475528241
Short name T320
Test name
Test status
Simulation time 47076263 ps
CPU time 0.58 seconds
Started Jul 26 07:00:13 PM PDT 24
Finished Jul 26 07:00:14 PM PDT 24
Peak memory 198140 kb
Host smart-1e9f1f62-37c5-4d42-a810-413b51bc547d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475528241 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_glitch.475528241
Directory /workspace/38.pwrmgr_glitch/latest

Test location /workspace/coverage/default/38.pwrmgr_global_esc.3214018230
Short name T6
Test name
Test status
Simulation time 49701440 ps
CPU time 0.59 seconds
Started Jul 26 07:00:17 PM PDT 24
Finished Jul 26 07:00:17 PM PDT 24
Peak memory 198164 kb
Host smart-bb30e98d-aed2-4cbf-85cc-14e4efec1304
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214018230 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_global_esc.3214018230
Directory /workspace/38.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/38.pwrmgr_lowpower_invalid.3239431191
Short name T447
Test name
Test status
Simulation time 45421440 ps
CPU time 0.78 seconds
Started Jul 26 07:00:17 PM PDT 24
Finished Jul 26 07:00:18 PM PDT 24
Peak memory 201464 kb
Host smart-82223584-aa2a-4bfa-b85d-9ee234701205
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239431191 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_lowpower_inval
id.3239431191
Directory /workspace/38.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/38.pwrmgr_reset.3980154336
Short name T216
Test name
Test status
Simulation time 110729023 ps
CPU time 0.73 seconds
Started Jul 26 07:00:11 PM PDT 24
Finished Jul 26 07:00:12 PM PDT 24
Peak memory 198240 kb
Host smart-37000fd9-466c-48c9-ae13-3109a6855d0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980154336 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset.3980154336
Directory /workspace/38.pwrmgr_reset/latest

Test location /workspace/coverage/default/38.pwrmgr_reset_invalid.1474146525
Short name T291
Test name
Test status
Simulation time 100029523 ps
CPU time 0.9 seconds
Started Jul 26 07:00:11 PM PDT 24
Finished Jul 26 07:00:12 PM PDT 24
Peak memory 209568 kb
Host smart-ddedbd2c-0183-47f8-a4a8-88ef374af88d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474146525 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset_invalid.1474146525
Directory /workspace/38.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/38.pwrmgr_sec_cm_rstmgr_intersig_mubi.2312615066
Short name T225
Test name
Test status
Simulation time 119370244 ps
CPU time 0.79 seconds
Started Jul 26 07:00:12 PM PDT 24
Finished Jul 26 07:00:13 PM PDT 24
Peak memory 199272 kb
Host smart-0fcd570b-b001-4c5e-ae60-c00b8eeddbf8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312615066 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2312615066
Directory /workspace/38.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/38.pwrmgr_smoke.2625672385
Short name T598
Test name
Test status
Simulation time 29843483 ps
CPU time 0.67 seconds
Started Jul 26 07:00:14 PM PDT 24
Finished Jul 26 07:00:15 PM PDT 24
Peak memory 199428 kb
Host smart-5ffd4757-afbc-40f1-a927-88f5dbcf52b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625672385 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_smoke.2625672385
Directory /workspace/38.pwrmgr_smoke/latest

Test location /workspace/coverage/default/39.pwrmgr_aborted_low_power.2872252025
Short name T602
Test name
Test status
Simulation time 46498805 ps
CPU time 0.78 seconds
Started Jul 26 07:00:15 PM PDT 24
Finished Jul 26 07:00:16 PM PDT 24
Peak memory 198796 kb
Host smart-98bdf2a1-dd82-49c5-9e66-f4cd559876d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872252025 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_aborted_low_power.2872252025
Directory /workspace/39.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/39.pwrmgr_disable_rom_integrity_check.2127767212
Short name T567
Test name
Test status
Simulation time 63099502 ps
CPU time 0.76 seconds
Started Jul 26 07:00:12 PM PDT 24
Finished Jul 26 07:00:14 PM PDT 24
Peak memory 198576 kb
Host smart-008ef212-6879-4bb4-85a1-96236092f323
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127767212 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_dis
able_rom_integrity_check.2127767212
Directory /workspace/39.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/39.pwrmgr_esc_clk_rst_malfunc.2668600812
Short name T254
Test name
Test status
Simulation time 41475426 ps
CPU time 0.62 seconds
Started Jul 26 07:00:15 PM PDT 24
Finished Jul 26 07:00:15 PM PDT 24
Peak memory 198044 kb
Host smart-cbe46601-d8d4-4e7e-adcb-4a4b2ed958e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668600812 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_esc_clk_rst
_malfunc.2668600812
Directory /workspace/39.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/39.pwrmgr_escalation_timeout.1252717059
Short name T233
Test name
Test status
Simulation time 1167447245 ps
CPU time 0.99 seconds
Started Jul 26 07:00:13 PM PDT 24
Finished Jul 26 07:00:15 PM PDT 24
Peak memory 198172 kb
Host smart-daefed6a-f0f8-433b-aed9-a4965b3e8185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252717059 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_escalation_timeout.1252717059
Directory /workspace/39.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/39.pwrmgr_glitch.2661704561
Short name T97
Test name
Test status
Simulation time 104100930 ps
CPU time 0.63 seconds
Started Jul 26 07:00:14 PM PDT 24
Finished Jul 26 07:00:15 PM PDT 24
Peak memory 197296 kb
Host smart-6ba57db3-7443-4ca2-888b-7aa5d5789b5e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661704561 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_glitch.2661704561
Directory /workspace/39.pwrmgr_glitch/latest

Test location /workspace/coverage/default/39.pwrmgr_global_esc.1652853309
Short name T352
Test name
Test status
Simulation time 35159482 ps
CPU time 0.66 seconds
Started Jul 26 07:00:15 PM PDT 24
Finished Jul 26 07:00:16 PM PDT 24
Peak memory 198136 kb
Host smart-3ddf10e8-44d7-45fa-85ae-afbfd27de330
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652853309 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_global_esc.1652853309
Directory /workspace/39.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/39.pwrmgr_reset.101723486
Short name T253
Test name
Test status
Simulation time 113386215 ps
CPU time 0.8 seconds
Started Jul 26 07:00:15 PM PDT 24
Finished Jul 26 07:00:16 PM PDT 24
Peak memory 199160 kb
Host smart-8432d53a-a969-4f0e-8aa3-69aa5e8a4ff3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101723486 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset.101723486
Directory /workspace/39.pwrmgr_reset/latest

Test location /workspace/coverage/default/39.pwrmgr_reset_invalid.3167568567
Short name T241
Test name
Test status
Simulation time 390451966 ps
CPU time 0.76 seconds
Started Jul 26 07:00:16 PM PDT 24
Finished Jul 26 07:00:17 PM PDT 24
Peak memory 209600 kb
Host smart-250e2fbb-93f4-4f99-b476-04a7d1d48bfa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167568567 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset_invalid.3167568567
Directory /workspace/39.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/39.pwrmgr_sec_cm_rstmgr_intersig_mubi.1412016609
Short name T556
Test name
Test status
Simulation time 121177778 ps
CPU time 0.83 seconds
Started Jul 26 07:00:12 PM PDT 24
Finished Jul 26 07:00:14 PM PDT 24
Peak memory 199276 kb
Host smart-9ef89fe6-364c-4346-a579-74d82d848375
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412016609 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1412016609
Directory /workspace/39.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/39.pwrmgr_smoke.1838486610
Short name T429
Test name
Test status
Simulation time 47446145 ps
CPU time 0.64 seconds
Started Jul 26 07:00:11 PM PDT 24
Finished Jul 26 07:00:12 PM PDT 24
Peak memory 198504 kb
Host smart-a17d2c95-7387-4160-8af9-159f71997e86
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838486610 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_smoke.1838486610
Directory /workspace/39.pwrmgr_smoke/latest

Test location /workspace/coverage/default/4.pwrmgr_aborted_low_power.2793125741
Short name T335
Test name
Test status
Simulation time 55697512 ps
CPU time 0.65 seconds
Started Jul 26 06:57:56 PM PDT 24
Finished Jul 26 06:57:57 PM PDT 24
Peak memory 198692 kb
Host smart-d90d0e1b-6a59-476b-8e57-4a6c4ca27ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793125741 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_aborted_low_power.2793125741
Directory /workspace/4.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/4.pwrmgr_disable_rom_integrity_check.3649729172
Short name T469
Test name
Test status
Simulation time 64554586 ps
CPU time 0.83 seconds
Started Jul 26 06:57:54 PM PDT 24
Finished Jul 26 06:57:55 PM PDT 24
Peak memory 198628 kb
Host smart-3bbf2b5d-862a-4995-8e83-b644fd8573ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649729172 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_disa
ble_rom_integrity_check.3649729172
Directory /workspace/4.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/4.pwrmgr_esc_clk_rst_malfunc.2334036986
Short name T450
Test name
Test status
Simulation time 31362702 ps
CPU time 0.64 seconds
Started Jul 26 06:57:54 PM PDT 24
Finished Jul 26 06:57:54 PM PDT 24
Peak memory 197440 kb
Host smart-fba37488-f209-4d3d-8666-76c7efa085d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334036986 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_esc_clk_rst_
malfunc.2334036986
Directory /workspace/4.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/4.pwrmgr_escalation_timeout.1189063144
Short name T610
Test name
Test status
Simulation time 650250125 ps
CPU time 0.92 seconds
Started Jul 26 06:57:53 PM PDT 24
Finished Jul 26 06:57:54 PM PDT 24
Peak memory 198108 kb
Host smart-a0835e85-4b42-4ead-95cf-11cfadd1c58a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189063144 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_escalation_timeout.1189063144
Directory /workspace/4.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/4.pwrmgr_glitch.2056911236
Short name T621
Test name
Test status
Simulation time 58221868 ps
CPU time 0.61 seconds
Started Jul 26 06:57:54 PM PDT 24
Finished Jul 26 06:57:55 PM PDT 24
Peak memory 197400 kb
Host smart-75989163-b781-4430-8b76-15f85a4a06db
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056911236 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_glitch.2056911236
Directory /workspace/4.pwrmgr_glitch/latest

Test location /workspace/coverage/default/4.pwrmgr_global_esc.948266463
Short name T561
Test name
Test status
Simulation time 58072702 ps
CPU time 0.62 seconds
Started Jul 26 06:57:55 PM PDT 24
Finished Jul 26 06:57:56 PM PDT 24
Peak memory 198092 kb
Host smart-bcd771a0-aea9-4777-a522-ccf2ce809d93
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948266463 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_global_esc.948266463
Directory /workspace/4.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/4.pwrmgr_lowpower_invalid.835206605
Short name T87
Test name
Test status
Simulation time 44537819 ps
CPU time 0.74 seconds
Started Jul 26 06:57:56 PM PDT 24
Finished Jul 26 06:57:57 PM PDT 24
Peak memory 201460 kb
Host smart-0f5328b9-98ac-4816-b01e-54827897421f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835206605 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_lowpower_invalid
.835206605
Directory /workspace/4.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/4.pwrmgr_reset.1557773103
Short name T272
Test name
Test status
Simulation time 70557421 ps
CPU time 0.66 seconds
Started Jul 26 06:57:56 PM PDT 24
Finished Jul 26 06:57:57 PM PDT 24
Peak memory 199120 kb
Host smart-ddcaa4d7-84cc-4b36-ae76-b4a654cc3e14
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557773103 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset.1557773103
Directory /workspace/4.pwrmgr_reset/latest

Test location /workspace/coverage/default/4.pwrmgr_reset_invalid.3982912809
Short name T548
Test name
Test status
Simulation time 114927991 ps
CPU time 1 seconds
Started Jul 26 06:57:54 PM PDT 24
Finished Jul 26 06:57:55 PM PDT 24
Peak memory 209448 kb
Host smart-0444a7ee-6d8c-49b0-a1d4-33f4173238fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982912809 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset_invalid.3982912809
Directory /workspace/4.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm_rstmgr_intersig_mubi.1466915538
Short name T250
Test name
Test status
Simulation time 94302739 ps
CPU time 0.71 seconds
Started Jul 26 06:57:56 PM PDT 24
Finished Jul 26 06:57:57 PM PDT 24
Peak memory 198220 kb
Host smart-00caba00-8ad2-450e-aab4-f45da931af6a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466915538 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_rstmgr_intersig_
mubi.1466915538
Directory /workspace/4.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/4.pwrmgr_smoke.693286150
Short name T560
Test name
Test status
Simulation time 29492289 ps
CPU time 0.65 seconds
Started Jul 26 06:57:47 PM PDT 24
Finished Jul 26 06:57:48 PM PDT 24
Peak memory 199464 kb
Host smart-26d53664-d320-4150-8f28-218d6fe2568b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693286150 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_smoke.693286150
Directory /workspace/4.pwrmgr_smoke/latest

Test location /workspace/coverage/default/40.pwrmgr_aborted_low_power.2488959660
Short name T246
Test name
Test status
Simulation time 60540810 ps
CPU time 0.87 seconds
Started Jul 26 07:00:12 PM PDT 24
Finished Jul 26 07:00:13 PM PDT 24
Peak memory 200356 kb
Host smart-94a4f811-3c58-4ffd-a9e2-06a9dc24dcb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488959660 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_aborted_low_power.2488959660
Directory /workspace/40.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/40.pwrmgr_disable_rom_integrity_check.2100071766
Short name T150
Test name
Test status
Simulation time 59015787 ps
CPU time 0.68 seconds
Started Jul 26 07:00:13 PM PDT 24
Finished Jul 26 07:00:14 PM PDT 24
Peak memory 198084 kb
Host smart-dbb94ced-4673-4c32-b3cc-8a2255632b02
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100071766 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_dis
able_rom_integrity_check.2100071766
Directory /workspace/40.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/40.pwrmgr_esc_clk_rst_malfunc.878289495
Short name T347
Test name
Test status
Simulation time 30054664 ps
CPU time 0.64 seconds
Started Jul 26 07:00:12 PM PDT 24
Finished Jul 26 07:00:12 PM PDT 24
Peak memory 197312 kb
Host smart-933b97cf-949e-4207-9d41-b6480f69ed57
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878289495 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_esc_clk_rst_
malfunc.878289495
Directory /workspace/40.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/40.pwrmgr_escalation_timeout.3679693377
Short name T600
Test name
Test status
Simulation time 611936215 ps
CPU time 0.97 seconds
Started Jul 26 07:00:14 PM PDT 24
Finished Jul 26 07:00:15 PM PDT 24
Peak memory 198460 kb
Host smart-f543a013-3fe2-40b9-941e-d37d3ed1be66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679693377 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_escalation_timeout.3679693377
Directory /workspace/40.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/40.pwrmgr_glitch.897019136
Short name T345
Test name
Test status
Simulation time 46387941 ps
CPU time 0.6 seconds
Started Jul 26 07:00:11 PM PDT 24
Finished Jul 26 07:00:12 PM PDT 24
Peak memory 198092 kb
Host smart-4a8e99ad-2ad2-4150-8034-6ab2a7b27898
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897019136 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_glitch.897019136
Directory /workspace/40.pwrmgr_glitch/latest

Test location /workspace/coverage/default/40.pwrmgr_global_esc.2007752818
Short name T568
Test name
Test status
Simulation time 31827774 ps
CPU time 0.64 seconds
Started Jul 26 07:00:13 PM PDT 24
Finished Jul 26 07:00:14 PM PDT 24
Peak memory 198428 kb
Host smart-73e24c53-025e-4a01-b2db-121e27b0729c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007752818 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_global_esc.2007752818
Directory /workspace/40.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/40.pwrmgr_lowpower_invalid.1692083694
Short name T181
Test name
Test status
Simulation time 43385521 ps
CPU time 0.74 seconds
Started Jul 26 07:00:12 PM PDT 24
Finished Jul 26 07:00:13 PM PDT 24
Peak memory 201424 kb
Host smart-202cf97a-1e4a-47a4-a4b5-25c7a6e04dc0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692083694 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_lowpower_inval
id.1692083694
Directory /workspace/40.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/40.pwrmgr_reset.4216213948
Short name T395
Test name
Test status
Simulation time 96298517 ps
CPU time 0.81 seconds
Started Jul 26 07:00:14 PM PDT 24
Finished Jul 26 07:00:15 PM PDT 24
Peak memory 198256 kb
Host smart-a0935542-dde3-4987-9cc9-5dd829cc3c2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216213948 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset.4216213948
Directory /workspace/40.pwrmgr_reset/latest

Test location /workspace/coverage/default/40.pwrmgr_reset_invalid.3509585931
Short name T531
Test name
Test status
Simulation time 97948955 ps
CPU time 1.12 seconds
Started Jul 26 07:00:12 PM PDT 24
Finished Jul 26 07:00:14 PM PDT 24
Peak memory 209544 kb
Host smart-b319f7f1-1d63-4140-bcb5-547b2553088b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509585931 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset_invalid.3509585931
Directory /workspace/40.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/40.pwrmgr_sec_cm_rstmgr_intersig_mubi.2515509362
Short name T271
Test name
Test status
Simulation time 59533642 ps
CPU time 0.82 seconds
Started Jul 26 07:00:13 PM PDT 24
Finished Jul 26 07:00:14 PM PDT 24
Peak memory 198148 kb
Host smart-d7762259-2122-4eeb-a535-bef503004bd4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515509362 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2515509362
Directory /workspace/40.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/40.pwrmgr_smoke.1806377869
Short name T35
Test name
Test status
Simulation time 61404814 ps
CPU time 0.67 seconds
Started Jul 26 07:00:12 PM PDT 24
Finished Jul 26 07:00:13 PM PDT 24
Peak memory 199372 kb
Host smart-33edc64f-81eb-4342-9381-5aeb60bc7b74
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806377869 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_smoke.1806377869
Directory /workspace/40.pwrmgr_smoke/latest

Test location /workspace/coverage/default/40.pwrmgr_wakeup.2044812530
Short name T15
Test name
Test status
Simulation time 57922825 ps
CPU time 0.71 seconds
Started Jul 26 07:00:14 PM PDT 24
Finished Jul 26 07:00:15 PM PDT 24
Peak memory 199032 kb
Host smart-59189691-d3aa-45b6-8785-e4de5c315510
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044812530 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_wakeup.2044812530
Directory /workspace/40.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/41.pwrmgr_aborted_low_power.246755408
Short name T128
Test name
Test status
Simulation time 42838180 ps
CPU time 0.92 seconds
Started Jul 26 07:00:16 PM PDT 24
Finished Jul 26 07:00:17 PM PDT 24
Peak memory 200260 kb
Host smart-0ced2a2f-597f-4ce8-a651-6790721cf6f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246755408 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_aborted_low_power.246755408
Directory /workspace/41.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/41.pwrmgr_disable_rom_integrity_check.4076334198
Short name T163
Test name
Test status
Simulation time 60594196 ps
CPU time 0.68 seconds
Started Jul 26 07:00:16 PM PDT 24
Finished Jul 26 07:00:17 PM PDT 24
Peak memory 198344 kb
Host smart-1678d56c-bb26-4243-abc4-ee77b2672373
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076334198 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_dis
able_rom_integrity_check.4076334198
Directory /workspace/41.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/41.pwrmgr_esc_clk_rst_malfunc.1983533599
Short name T237
Test name
Test status
Simulation time 32385355 ps
CPU time 0.61 seconds
Started Jul 26 07:00:14 PM PDT 24
Finished Jul 26 07:00:15 PM PDT 24
Peak memory 198040 kb
Host smart-bb58ee97-b9ed-4bc9-a5cd-67e4af69a476
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983533599 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_esc_clk_rst
_malfunc.1983533599
Directory /workspace/41.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/41.pwrmgr_escalation_timeout.1344144376
Short name T297
Test name
Test status
Simulation time 167791770 ps
CPU time 1 seconds
Started Jul 26 07:00:14 PM PDT 24
Finished Jul 26 07:00:15 PM PDT 24
Peak memory 198144 kb
Host smart-7661441c-98bc-4751-93ac-05077d8041c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344144376 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_escalation_timeout.1344144376
Directory /workspace/41.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/41.pwrmgr_glitch.3746282973
Short name T286
Test name
Test status
Simulation time 28966418 ps
CPU time 0.62 seconds
Started Jul 26 07:00:13 PM PDT 24
Finished Jul 26 07:00:14 PM PDT 24
Peak memory 197976 kb
Host smart-1563774b-fa9a-468d-a480-cf7fde6f1934
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746282973 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_glitch.3746282973
Directory /workspace/41.pwrmgr_glitch/latest

Test location /workspace/coverage/default/41.pwrmgr_global_esc.492664728
Short name T596
Test name
Test status
Simulation time 25380880 ps
CPU time 0.7 seconds
Started Jul 26 07:00:16 PM PDT 24
Finished Jul 26 07:00:17 PM PDT 24
Peak memory 198228 kb
Host smart-387db81d-ad97-4c99-9076-d9958fcc4666
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492664728 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_global_esc.492664728
Directory /workspace/41.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/41.pwrmgr_lowpower_invalid.3063815915
Short name T188
Test name
Test status
Simulation time 163388236 ps
CPU time 0.73 seconds
Started Jul 26 07:00:20 PM PDT 24
Finished Jul 26 07:00:21 PM PDT 24
Peak memory 201648 kb
Host smart-77b8316f-830b-4388-9d78-86cde759ed52
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063815915 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_lowpower_inval
id.3063815915
Directory /workspace/41.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/41.pwrmgr_reset.2587917323
Short name T416
Test name
Test status
Simulation time 175873426 ps
CPU time 0.83 seconds
Started Jul 26 07:00:18 PM PDT 24
Finished Jul 26 07:00:19 PM PDT 24
Peak memory 198656 kb
Host smart-606e7126-f3e2-4bfb-80ca-c658f1aacb2f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587917323 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset.2587917323
Directory /workspace/41.pwrmgr_reset/latest

Test location /workspace/coverage/default/41.pwrmgr_reset_invalid.2143124213
Short name T524
Test name
Test status
Simulation time 105091199 ps
CPU time 0.92 seconds
Started Jul 26 07:00:14 PM PDT 24
Finished Jul 26 07:00:15 PM PDT 24
Peak memory 209500 kb
Host smart-3839d87e-3c0e-4a69-9c5a-3d0ebf1c1a75
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143124213 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset_invalid.2143124213
Directory /workspace/41.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/41.pwrmgr_smoke.3831684212
Short name T92
Test name
Test status
Simulation time 152210498 ps
CPU time 0.64 seconds
Started Jul 26 07:00:09 PM PDT 24
Finished Jul 26 07:00:10 PM PDT 24
Peak memory 198536 kb
Host smart-ecb637e5-d035-404c-b9ed-1f259fd1fbe2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831684212 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_smoke.3831684212
Directory /workspace/41.pwrmgr_smoke/latest

Test location /workspace/coverage/default/42.pwrmgr_disable_rom_integrity_check.66545950
Short name T149
Test name
Test status
Simulation time 105061003 ps
CPU time 0.7 seconds
Started Jul 26 07:00:20 PM PDT 24
Finished Jul 26 07:00:21 PM PDT 24
Peak memory 198744 kb
Host smart-8779a8b0-f6f4-4502-81b6-2a18a3111b08
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66545950 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_int
egrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_disab
le_rom_integrity_check.66545950
Directory /workspace/42.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/42.pwrmgr_esc_clk_rst_malfunc.2760546122
Short name T571
Test name
Test status
Simulation time 30284377 ps
CPU time 0.62 seconds
Started Jul 26 07:00:23 PM PDT 24
Finished Jul 26 07:00:24 PM PDT 24
Peak memory 198028 kb
Host smart-1d510bf4-b318-4aff-9a0b-e7cb20067d9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760546122 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_esc_clk_rst
_malfunc.2760546122
Directory /workspace/42.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/42.pwrmgr_escalation_timeout.1467560755
Short name T51
Test name
Test status
Simulation time 164827625 ps
CPU time 0.96 seconds
Started Jul 26 07:00:22 PM PDT 24
Finished Jul 26 07:00:23 PM PDT 24
Peak memory 198160 kb
Host smart-7b2dc12e-18b2-4a31-9b27-7802ff6e95a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467560755 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_escalation_timeout.1467560755
Directory /workspace/42.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/42.pwrmgr_glitch.1542595882
Short name T319
Test name
Test status
Simulation time 51796530 ps
CPU time 0.63 seconds
Started Jul 26 07:00:21 PM PDT 24
Finished Jul 26 07:00:22 PM PDT 24
Peak memory 197436 kb
Host smart-ee8d9103-1545-49aa-9738-0eae1681e384
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542595882 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_glitch.1542595882
Directory /workspace/42.pwrmgr_glitch/latest

Test location /workspace/coverage/default/42.pwrmgr_global_esc.2008794301
Short name T436
Test name
Test status
Simulation time 84493950 ps
CPU time 0.61 seconds
Started Jul 26 07:00:24 PM PDT 24
Finished Jul 26 07:00:25 PM PDT 24
Peak memory 198436 kb
Host smart-aa245170-213b-4729-bc75-602a8478b02f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008794301 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_global_esc.2008794301
Directory /workspace/42.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/42.pwrmgr_lowpower_invalid.2569402613
Short name T29
Test name
Test status
Simulation time 67829082 ps
CPU time 0.69 seconds
Started Jul 26 07:00:22 PM PDT 24
Finished Jul 26 07:00:23 PM PDT 24
Peak memory 201432 kb
Host smart-2f79c5e6-2e31-4961-8533-0926913792ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569402613 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_lowpower_inval
id.2569402613
Directory /workspace/42.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/42.pwrmgr_reset.1083243286
Short name T203
Test name
Test status
Simulation time 102836475 ps
CPU time 0.75 seconds
Started Jul 26 07:00:30 PM PDT 24
Finished Jul 26 07:00:31 PM PDT 24
Peak memory 199164 kb
Host smart-f9bfd64b-cacc-4fd3-972d-c6f44221360a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083243286 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset.1083243286
Directory /workspace/42.pwrmgr_reset/latest

Test location /workspace/coverage/default/42.pwrmgr_reset_invalid.438490725
Short name T494
Test name
Test status
Simulation time 125513536 ps
CPU time 0.84 seconds
Started Jul 26 07:00:22 PM PDT 24
Finished Jul 26 07:00:23 PM PDT 24
Peak memory 209540 kb
Host smart-5d2fadc1-5962-40eb-88a3-f1eccea1a420
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438490725 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset_invalid.438490725
Directory /workspace/42.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/42.pwrmgr_sec_cm_rstmgr_intersig_mubi.1976184683
Short name T435
Test name
Test status
Simulation time 54490175 ps
CPU time 0.82 seconds
Started Jul 26 07:00:20 PM PDT 24
Finished Jul 26 07:00:21 PM PDT 24
Peak memory 198272 kb
Host smart-5d73c148-016a-415d-b395-c5c8e7e17a39
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976184683 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1976184683
Directory /workspace/42.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/42.pwrmgr_smoke.2571839170
Short name T290
Test name
Test status
Simulation time 27962643 ps
CPU time 0.7 seconds
Started Jul 26 07:00:22 PM PDT 24
Finished Jul 26 07:00:23 PM PDT 24
Peak memory 199412 kb
Host smart-08bc528f-84fc-4b89-a9e1-0090a1e87fa8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571839170 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_smoke.2571839170
Directory /workspace/42.pwrmgr_smoke/latest

Test location /workspace/coverage/default/43.pwrmgr_aborted_low_power.1935043189
Short name T127
Test name
Test status
Simulation time 23831089 ps
CPU time 0.62 seconds
Started Jul 26 07:00:20 PM PDT 24
Finished Jul 26 07:00:21 PM PDT 24
Peak memory 198592 kb
Host smart-bcc1d738-3de0-4e03-81bd-3852b9388510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935043189 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_aborted_low_power.1935043189
Directory /workspace/43.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/43.pwrmgr_disable_rom_integrity_check.3509774687
Short name T161
Test name
Test status
Simulation time 69798415 ps
CPU time 0.69 seconds
Started Jul 26 07:00:29 PM PDT 24
Finished Jul 26 07:00:30 PM PDT 24
Peak memory 198452 kb
Host smart-6850e09e-1181-41af-b5e1-da76f13ebf73
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509774687 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_dis
able_rom_integrity_check.3509774687
Directory /workspace/43.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/43.pwrmgr_esc_clk_rst_malfunc.4169668518
Short name T547
Test name
Test status
Simulation time 30104430 ps
CPU time 0.64 seconds
Started Jul 26 07:00:28 PM PDT 24
Finished Jul 26 07:00:29 PM PDT 24
Peak memory 198064 kb
Host smart-f11c65b3-5426-4c68-976c-e50ef64589c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169668518 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_esc_clk_rst
_malfunc.4169668518
Directory /workspace/43.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/43.pwrmgr_escalation_timeout.4064820167
Short name T384
Test name
Test status
Simulation time 636798942 ps
CPU time 0.99 seconds
Started Jul 26 07:00:28 PM PDT 24
Finished Jul 26 07:00:29 PM PDT 24
Peak memory 198204 kb
Host smart-15e766e4-b475-4c2f-a010-52819e9ff28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064820167 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_escalation_timeout.4064820167
Directory /workspace/43.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/43.pwrmgr_glitch.4085992870
Short name T512
Test name
Test status
Simulation time 57912459 ps
CPU time 0.61 seconds
Started Jul 26 07:00:32 PM PDT 24
Finished Jul 26 07:00:33 PM PDT 24
Peak memory 198120 kb
Host smart-6c786a5f-a9f8-4bbb-90fc-893a1fad0652
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085992870 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_glitch.4085992870
Directory /workspace/43.pwrmgr_glitch/latest

Test location /workspace/coverage/default/43.pwrmgr_global_esc.1973656161
Short name T385
Test name
Test status
Simulation time 24926058 ps
CPU time 0.61 seconds
Started Jul 26 07:00:29 PM PDT 24
Finished Jul 26 07:00:30 PM PDT 24
Peak memory 198184 kb
Host smart-999d9f67-9503-4cb2-b4b9-f804dfafcf63
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973656161 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_global_esc.1973656161
Directory /workspace/43.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/43.pwrmgr_lowpower_invalid.1054454913
Short name T180
Test name
Test status
Simulation time 170645123 ps
CPU time 0.66 seconds
Started Jul 26 07:00:29 PM PDT 24
Finished Jul 26 07:00:30 PM PDT 24
Peak memory 201396 kb
Host smart-8d48ae3f-f30d-4bba-a0a0-c92e7938df9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054454913 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_lowpower_inval
id.1054454913
Directory /workspace/43.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/43.pwrmgr_reset.1584047483
Short name T519
Test name
Test status
Simulation time 61560750 ps
CPU time 0.75 seconds
Started Jul 26 07:00:23 PM PDT 24
Finished Jul 26 07:00:24 PM PDT 24
Peak memory 199156 kb
Host smart-3f2eb479-ab7a-474f-90cb-2d9c078fcd69
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584047483 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset.1584047483
Directory /workspace/43.pwrmgr_reset/latest

Test location /workspace/coverage/default/43.pwrmgr_reset_invalid.3673972565
Short name T419
Test name
Test status
Simulation time 102667039 ps
CPU time 0.94 seconds
Started Jul 26 07:00:31 PM PDT 24
Finished Jul 26 07:00:32 PM PDT 24
Peak memory 209476 kb
Host smart-f0221924-c663-4179-9179-a7a52a0e084a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673972565 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset_invalid.3673972565
Directory /workspace/43.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/43.pwrmgr_sec_cm_rstmgr_intersig_mubi.3581293714
Short name T557
Test name
Test status
Simulation time 62820886 ps
CPU time 0.85 seconds
Started Jul 26 07:00:28 PM PDT 24
Finished Jul 26 07:00:29 PM PDT 24
Peak memory 198208 kb
Host smart-37677db4-565f-4d35-8a9b-3885a9fddcac
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581293714 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3581293714
Directory /workspace/43.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/43.pwrmgr_smoke.2463546034
Short name T564
Test name
Test status
Simulation time 57942594 ps
CPU time 0.64 seconds
Started Jul 26 07:00:20 PM PDT 24
Finished Jul 26 07:00:21 PM PDT 24
Peak memory 199440 kb
Host smart-27039922-1dcb-4380-81a8-071ef88eb127
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463546034 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_smoke.2463546034
Directory /workspace/43.pwrmgr_smoke/latest

Test location /workspace/coverage/default/44.pwrmgr_aborted_low_power.3797437966
Short name T409
Test name
Test status
Simulation time 75311015 ps
CPU time 0.77 seconds
Started Jul 26 07:00:31 PM PDT 24
Finished Jul 26 07:00:32 PM PDT 24
Peak memory 198884 kb
Host smart-f34afb95-7079-4a39-b23a-c6df9f39a254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797437966 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_aborted_low_power.3797437966
Directory /workspace/44.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/44.pwrmgr_disable_rom_integrity_check.2648719313
Short name T535
Test name
Test status
Simulation time 81085695 ps
CPU time 0.66 seconds
Started Jul 26 07:00:31 PM PDT 24
Finished Jul 26 07:00:32 PM PDT 24
Peak memory 198620 kb
Host smart-9e89ae71-2995-43d9-a089-2d5543904b0d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648719313 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_dis
able_rom_integrity_check.2648719313
Directory /workspace/44.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/44.pwrmgr_esc_clk_rst_malfunc.1195824033
Short name T367
Test name
Test status
Simulation time 30814240 ps
CPU time 0.61 seconds
Started Jul 26 07:00:30 PM PDT 24
Finished Jul 26 07:00:31 PM PDT 24
Peak memory 198120 kb
Host smart-a972a3c5-e0ca-44df-b0b7-594585ac0f3c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195824033 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_esc_clk_rst
_malfunc.1195824033
Directory /workspace/44.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/44.pwrmgr_escalation_timeout.2771446059
Short name T627
Test name
Test status
Simulation time 625319941 ps
CPU time 0.97 seconds
Started Jul 26 07:00:30 PM PDT 24
Finished Jul 26 07:00:32 PM PDT 24
Peak memory 198148 kb
Host smart-308d1630-d46a-4224-9ba5-ce8d4bc57921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771446059 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_escalation_timeout.2771446059
Directory /workspace/44.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/44.pwrmgr_glitch.1480332582
Short name T424
Test name
Test status
Simulation time 25118314 ps
CPU time 0.61 seconds
Started Jul 26 07:00:30 PM PDT 24
Finished Jul 26 07:00:31 PM PDT 24
Peak memory 198112 kb
Host smart-dafb3d0a-9702-45c7-aa35-caa17203686a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480332582 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_glitch.1480332582
Directory /workspace/44.pwrmgr_glitch/latest

Test location /workspace/coverage/default/44.pwrmgr_global_esc.3522372555
Short name T244
Test name
Test status
Simulation time 44371803 ps
CPU time 0.68 seconds
Started Jul 26 07:00:30 PM PDT 24
Finished Jul 26 07:00:31 PM PDT 24
Peak memory 198136 kb
Host smart-dd8e4ef7-8d19-43ac-8253-bd541aa83372
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522372555 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_global_esc.3522372555
Directory /workspace/44.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/44.pwrmgr_lowpower_invalid.2677376646
Short name T3
Test name
Test status
Simulation time 74689557 ps
CPU time 0.66 seconds
Started Jul 26 07:00:28 PM PDT 24
Finished Jul 26 07:00:28 PM PDT 24
Peak memory 201428 kb
Host smart-d4c61ec0-4129-4f30-8f99-78ba2198b4fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677376646 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_lowpower_inval
id.2677376646
Directory /workspace/44.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/44.pwrmgr_reset.1691805118
Short name T40
Test name
Test status
Simulation time 39122480 ps
CPU time 0.72 seconds
Started Jul 26 07:00:46 PM PDT 24
Finished Jul 26 07:00:47 PM PDT 24
Peak memory 198432 kb
Host smart-8d380e80-800c-468c-b219-04810980ae17
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691805118 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset.1691805118
Directory /workspace/44.pwrmgr_reset/latest

Test location /workspace/coverage/default/44.pwrmgr_reset_invalid.4137262492
Short name T464
Test name
Test status
Simulation time 112331059 ps
CPU time 0.84 seconds
Started Jul 26 07:00:28 PM PDT 24
Finished Jul 26 07:00:29 PM PDT 24
Peak memory 209428 kb
Host smart-4d2cae23-9151-43f0-9c5b-065e4790a5cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137262492 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset_invalid.4137262492
Directory /workspace/44.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/44.pwrmgr_sec_cm_rstmgr_intersig_mubi.2128003275
Short name T205
Test name
Test status
Simulation time 69059284 ps
CPU time 0.96 seconds
Started Jul 26 07:00:32 PM PDT 24
Finished Jul 26 07:00:33 PM PDT 24
Peak memory 199264 kb
Host smart-da7f4d27-ea8a-4cc7-a0da-1e476fd9dcc2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128003275 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2128003275
Directory /workspace/44.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/44.pwrmgr_smoke.2079831505
Short name T281
Test name
Test status
Simulation time 49160066 ps
CPU time 0.7 seconds
Started Jul 26 07:00:28 PM PDT 24
Finished Jul 26 07:00:29 PM PDT 24
Peak memory 199396 kb
Host smart-3260521a-8f51-4092-b7f2-814a91841394
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079831505 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_smoke.2079831505
Directory /workspace/44.pwrmgr_smoke/latest

Test location /workspace/coverage/default/45.pwrmgr_aborted_low_power.544663315
Short name T200
Test name
Test status
Simulation time 19244049 ps
CPU time 0.65 seconds
Started Jul 26 07:00:28 PM PDT 24
Finished Jul 26 07:00:29 PM PDT 24
Peak memory 199200 kb
Host smart-37c1e1fa-0c77-477a-983f-a4e18fbefe54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544663315 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_aborted_low_power.544663315
Directory /workspace/45.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/45.pwrmgr_disable_rom_integrity_check.726842270
Short name T160
Test name
Test status
Simulation time 85442675 ps
CPU time 0.68 seconds
Started Jul 26 07:00:30 PM PDT 24
Finished Jul 26 07:00:30 PM PDT 24
Peak memory 198276 kb
Host smart-62f78aa1-6905-44a8-bf6b-453f82c5dcd7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726842270 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_disa
ble_rom_integrity_check.726842270
Directory /workspace/45.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/45.pwrmgr_esc_clk_rst_malfunc.3975457630
Short name T472
Test name
Test status
Simulation time 39169663 ps
CPU time 0.59 seconds
Started Jul 26 07:00:29 PM PDT 24
Finished Jul 26 07:00:29 PM PDT 24
Peak memory 197392 kb
Host smart-ef8d0e8e-d242-4ed2-8c05-2d07da97a7d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975457630 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_esc_clk_rst
_malfunc.3975457630
Directory /workspace/45.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/45.pwrmgr_escalation_timeout.418241095
Short name T443
Test name
Test status
Simulation time 160775533 ps
CPU time 0.97 seconds
Started Jul 26 07:00:31 PM PDT 24
Finished Jul 26 07:00:33 PM PDT 24
Peak memory 198160 kb
Host smart-50461f48-7f59-41b2-8cdf-e1fc5de516e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418241095 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_escalation_timeout.418241095
Directory /workspace/45.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/45.pwrmgr_glitch.2886393594
Short name T284
Test name
Test status
Simulation time 39831492 ps
CPU time 0.62 seconds
Started Jul 26 07:00:30 PM PDT 24
Finished Jul 26 07:00:31 PM PDT 24
Peak memory 197440 kb
Host smart-3e2e46ed-73af-49d9-b02b-6a848e0b18c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886393594 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_glitch.2886393594
Directory /workspace/45.pwrmgr_glitch/latest

Test location /workspace/coverage/default/45.pwrmgr_global_esc.1364643038
Short name T421
Test name
Test status
Simulation time 53431619 ps
CPU time 0.63 seconds
Started Jul 26 07:00:31 PM PDT 24
Finished Jul 26 07:00:32 PM PDT 24
Peak memory 198504 kb
Host smart-fe5599c8-9076-4882-ab78-e59b35bf2cf4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364643038 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_global_esc.1364643038
Directory /workspace/45.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/45.pwrmgr_lowpower_invalid.2108070460
Short name T171
Test name
Test status
Simulation time 49809096 ps
CPU time 0.7 seconds
Started Jul 26 07:00:32 PM PDT 24
Finished Jul 26 07:00:32 PM PDT 24
Peak memory 201420 kb
Host smart-6563ee52-e95a-428b-9bbc-4c3d5e661ae1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108070460 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_lowpower_inval
id.2108070460
Directory /workspace/45.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/45.pwrmgr_reset.2758006274
Short name T427
Test name
Test status
Simulation time 132966283 ps
CPU time 0.66 seconds
Started Jul 26 07:00:29 PM PDT 24
Finished Jul 26 07:00:30 PM PDT 24
Peak memory 198336 kb
Host smart-28c6e5fb-f8c4-4ad1-88a1-add81d2c7fb0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758006274 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset.2758006274
Directory /workspace/45.pwrmgr_reset/latest

Test location /workspace/coverage/default/45.pwrmgr_reset_invalid.3295208516
Short name T432
Test name
Test status
Simulation time 102046058 ps
CPU time 0.91 seconds
Started Jul 26 07:00:31 PM PDT 24
Finished Jul 26 07:00:32 PM PDT 24
Peak memory 209592 kb
Host smart-c1b2b54f-f392-4f8e-a86c-5721796ab0b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295208516 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset_invalid.3295208516
Directory /workspace/45.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/45.pwrmgr_sec_cm_rstmgr_intersig_mubi.2160262509
Short name T86
Test name
Test status
Simulation time 53759292 ps
CPU time 0.8 seconds
Started Jul 26 07:00:28 PM PDT 24
Finished Jul 26 07:00:29 PM PDT 24
Peak memory 198100 kb
Host smart-4b04ae79-49dd-4ab1-a231-460d3117a717
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160262509 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2160262509
Directory /workspace/45.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/45.pwrmgr_smoke.4014193547
Short name T476
Test name
Test status
Simulation time 42051578 ps
CPU time 0.72 seconds
Started Jul 26 07:00:31 PM PDT 24
Finished Jul 26 07:00:32 PM PDT 24
Peak memory 198556 kb
Host smart-2becbb56-e564-4e62-b84f-601b833f2346
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014193547 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_smoke.4014193547
Directory /workspace/45.pwrmgr_smoke/latest

Test location /workspace/coverage/default/46.pwrmgr_aborted_low_power.2124631737
Short name T398
Test name
Test status
Simulation time 87163878 ps
CPU time 0.72 seconds
Started Jul 26 07:00:32 PM PDT 24
Finished Jul 26 07:00:33 PM PDT 24
Peak memory 198848 kb
Host smart-5f5ed469-0ff3-4fe3-98fc-7c5cd04f006b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124631737 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_aborted_low_power.2124631737
Directory /workspace/46.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/46.pwrmgr_disable_rom_integrity_check.581753619
Short name T38
Test name
Test status
Simulation time 66404759 ps
CPU time 0.7 seconds
Started Jul 26 07:00:30 PM PDT 24
Finished Jul 26 07:00:31 PM PDT 24
Peak memory 199096 kb
Host smart-2faa7cdb-f1a0-48ee-b72d-6d177cd7a9aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581753619 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_disa
ble_rom_integrity_check.581753619
Directory /workspace/46.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/46.pwrmgr_esc_clk_rst_malfunc.4224898861
Short name T296
Test name
Test status
Simulation time 38928861 ps
CPU time 0.58 seconds
Started Jul 26 07:00:29 PM PDT 24
Finished Jul 26 07:00:30 PM PDT 24
Peak memory 197980 kb
Host smart-bdbbf46d-257c-415a-ab9a-9d3323d1da91
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224898861 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_esc_clk_rst
_malfunc.4224898861
Directory /workspace/46.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/46.pwrmgr_escalation_timeout.967731625
Short name T418
Test name
Test status
Simulation time 638363774 ps
CPU time 0.94 seconds
Started Jul 26 07:00:32 PM PDT 24
Finished Jul 26 07:00:34 PM PDT 24
Peak memory 198432 kb
Host smart-97b3111b-9dcd-412c-9c6a-66619010f3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967731625 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_escalation_timeout.967731625
Directory /workspace/46.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/46.pwrmgr_glitch.3547896284
Short name T526
Test name
Test status
Simulation time 219056981 ps
CPU time 0.61 seconds
Started Jul 26 07:00:32 PM PDT 24
Finished Jul 26 07:00:33 PM PDT 24
Peak memory 197468 kb
Host smart-cb041abf-5c9c-4c22-9d7e-8fdf7f9d352c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547896284 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_glitch.3547896284
Directory /workspace/46.pwrmgr_glitch/latest

Test location /workspace/coverage/default/46.pwrmgr_global_esc.1871070531
Short name T207
Test name
Test status
Simulation time 23644802 ps
CPU time 0.61 seconds
Started Jul 26 07:00:29 PM PDT 24
Finished Jul 26 07:00:29 PM PDT 24
Peak memory 198448 kb
Host smart-a6fa0348-5e93-47b8-a579-f9b3e2a5c450
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871070531 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_global_esc.1871070531
Directory /workspace/46.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/46.pwrmgr_lowpower_invalid.3564605312
Short name T184
Test name
Test status
Simulation time 41692114 ps
CPU time 0.71 seconds
Started Jul 26 07:00:31 PM PDT 24
Finished Jul 26 07:00:32 PM PDT 24
Peak memory 201472 kb
Host smart-98f74a2a-8165-4d85-93eb-9be3d74c09f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564605312 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_lowpower_inval
id.3564605312
Directory /workspace/46.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/46.pwrmgr_reset.689443438
Short name T218
Test name
Test status
Simulation time 66793925 ps
CPU time 0.74 seconds
Started Jul 26 07:00:30 PM PDT 24
Finished Jul 26 07:00:31 PM PDT 24
Peak memory 198352 kb
Host smart-cfa2d431-76ce-4b56-bbfd-f51ac570bc8e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689443438 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset.689443438
Directory /workspace/46.pwrmgr_reset/latest

Test location /workspace/coverage/default/46.pwrmgr_sec_cm_rstmgr_intersig_mubi.3417036109
Short name T428
Test name
Test status
Simulation time 72585138 ps
CPU time 0.74 seconds
Started Jul 26 07:00:29 PM PDT 24
Finished Jul 26 07:00:30 PM PDT 24
Peak memory 198116 kb
Host smart-a131a35b-7bf4-42dc-a665-c56ddbcc4ef5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417036109 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3417036109
Directory /workspace/46.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/46.pwrmgr_smoke.2806797593
Short name T33
Test name
Test status
Simulation time 29243021 ps
CPU time 0.66 seconds
Started Jul 26 07:00:30 PM PDT 24
Finished Jul 26 07:00:31 PM PDT 24
Peak memory 198560 kb
Host smart-ebb20c4e-8dd6-438e-9fa7-92cb9a8532c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806797593 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_smoke.2806797593
Directory /workspace/46.pwrmgr_smoke/latest

Test location /workspace/coverage/default/46.pwrmgr_wakeup.2751965405
Short name T191
Test name
Test status
Simulation time 40295468 ps
CPU time 0.63 seconds
Started Jul 26 07:00:29 PM PDT 24
Finished Jul 26 07:00:29 PM PDT 24
Peak memory 198268 kb
Host smart-bdcf9fd5-af5b-4d6b-b4a1-47b065b32ff0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751965405 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_wakeup.2751965405
Directory /workspace/46.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/47.pwrmgr_aborted_low_power.1360243230
Short name T456
Test name
Test status
Simulation time 41085114 ps
CPU time 0.88 seconds
Started Jul 26 07:00:32 PM PDT 24
Finished Jul 26 07:00:33 PM PDT 24
Peak memory 200368 kb
Host smart-ecc2e3e8-c206-4cdc-82f6-de428570d981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360243230 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_aborted_low_power.1360243230
Directory /workspace/47.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/47.pwrmgr_disable_rom_integrity_check.4233719530
Short name T628
Test name
Test status
Simulation time 66631060 ps
CPU time 0.75 seconds
Started Jul 26 07:00:41 PM PDT 24
Finished Jul 26 07:00:42 PM PDT 24
Peak memory 198560 kb
Host smart-920435fb-a130-4d07-be40-733fd188cc0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233719530 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_dis
able_rom_integrity_check.4233719530
Directory /workspace/47.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/47.pwrmgr_esc_clk_rst_malfunc.854915740
Short name T360
Test name
Test status
Simulation time 82683555 ps
CPU time 0.58 seconds
Started Jul 26 07:00:30 PM PDT 24
Finished Jul 26 07:00:31 PM PDT 24
Peak memory 198112 kb
Host smart-a0700e51-6e25-4175-bcca-07e5441495a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854915740 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_esc_clk_rst_
malfunc.854915740
Directory /workspace/47.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/47.pwrmgr_escalation_timeout.1933082690
Short name T298
Test name
Test status
Simulation time 1512919647 ps
CPU time 0.97 seconds
Started Jul 26 07:00:32 PM PDT 24
Finished Jul 26 07:00:33 PM PDT 24
Peak memory 198512 kb
Host smart-bb7ee4f4-44a4-4912-a194-5ef7379205d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933082690 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_escalation_timeout.1933082690
Directory /workspace/47.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/47.pwrmgr_glitch.404415962
Short name T287
Test name
Test status
Simulation time 34057513 ps
CPU time 0.67 seconds
Started Jul 26 07:00:35 PM PDT 24
Finished Jul 26 07:00:36 PM PDT 24
Peak memory 197360 kb
Host smart-73e258b8-706d-442e-ba66-2ad08360b45d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404415962 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_glitch.404415962
Directory /workspace/47.pwrmgr_glitch/latest

Test location /workspace/coverage/default/47.pwrmgr_global_esc.2200584852
Short name T586
Test name
Test status
Simulation time 28991204 ps
CPU time 0.64 seconds
Started Jul 26 07:00:32 PM PDT 24
Finished Jul 26 07:00:33 PM PDT 24
Peak memory 198464 kb
Host smart-6871b3c1-94e7-4f6f-8799-f185cd17f85f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200584852 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_global_esc.2200584852
Directory /workspace/47.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/47.pwrmgr_lowpower_invalid.3356470382
Short name T169
Test name
Test status
Simulation time 75172237 ps
CPU time 0.68 seconds
Started Jul 26 07:00:41 PM PDT 24
Finished Jul 26 07:00:42 PM PDT 24
Peak memory 201420 kb
Host smart-6e564064-06af-472c-a56d-b57809f64d81
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356470382 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_lowpower_inval
id.3356470382
Directory /workspace/47.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/47.pwrmgr_reset.899767082
Short name T295
Test name
Test status
Simulation time 45541221 ps
CPU time 0.67 seconds
Started Jul 26 07:00:32 PM PDT 24
Finished Jul 26 07:00:33 PM PDT 24
Peak memory 198376 kb
Host smart-71017bc0-24c0-4c05-96e3-bf6d2396d3e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899767082 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset.899767082
Directory /workspace/47.pwrmgr_reset/latest

Test location /workspace/coverage/default/47.pwrmgr_reset_invalid.1432554850
Short name T274
Test name
Test status
Simulation time 98131061 ps
CPU time 1.08 seconds
Started Jul 26 07:00:37 PM PDT 24
Finished Jul 26 07:00:38 PM PDT 24
Peak memory 209576 kb
Host smart-29cd8639-9f9a-42b7-be04-16fc0f1efe5e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432554850 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset_invalid.1432554850
Directory /workspace/47.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/47.pwrmgr_sec_cm_rstmgr_intersig_mubi.1479993503
Short name T130
Test name
Test status
Simulation time 175317687 ps
CPU time 0.85 seconds
Started Jul 26 07:00:32 PM PDT 24
Finished Jul 26 07:00:33 PM PDT 24
Peak memory 199272 kb
Host smart-a1f806e9-16e4-4fcf-8bdb-59dd95987da4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479993503 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1479993503
Directory /workspace/47.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/47.pwrmgr_smoke.2613636415
Short name T247
Test name
Test status
Simulation time 59611931 ps
CPU time 0.63 seconds
Started Jul 26 07:00:31 PM PDT 24
Finished Jul 26 07:00:32 PM PDT 24
Peak memory 198496 kb
Host smart-53b42870-f8a8-420e-9df4-b8825b22496a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613636415 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_smoke.2613636415
Directory /workspace/47.pwrmgr_smoke/latest

Test location /workspace/coverage/default/47.pwrmgr_stress_all.2699878631
Short name T362
Test name
Test status
Simulation time 217892832 ps
CPU time 1.01 seconds
Started Jul 26 07:00:28 PM PDT 24
Finished Jul 26 07:00:29 PM PDT 24
Peak memory 200092 kb
Host smart-a8b8d066-5e6e-4b13-b644-0e0a1d452ba2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699878631 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_stress_all.2699878631
Directory /workspace/47.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/48.pwrmgr_aborted_low_power.3974247185
Short name T249
Test name
Test status
Simulation time 26648462 ps
CPU time 0.71 seconds
Started Jul 26 07:00:38 PM PDT 24
Finished Jul 26 07:00:39 PM PDT 24
Peak memory 198736 kb
Host smart-c20cbb75-4cb4-4dbb-bd1d-91f3a6c24c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974247185 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_aborted_low_power.3974247185
Directory /workspace/48.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/48.pwrmgr_esc_clk_rst_malfunc.3495323187
Short name T582
Test name
Test status
Simulation time 39804788 ps
CPU time 0.61 seconds
Started Jul 26 07:00:40 PM PDT 24
Finished Jul 26 07:00:41 PM PDT 24
Peak memory 198072 kb
Host smart-777e6952-65b1-4992-84dd-dd65f0670027
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495323187 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_esc_clk_rst
_malfunc.3495323187
Directory /workspace/48.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/48.pwrmgr_escalation_timeout.203111903
Short name T135
Test name
Test status
Simulation time 337257242 ps
CPU time 0.99 seconds
Started Jul 26 07:00:34 PM PDT 24
Finished Jul 26 07:00:35 PM PDT 24
Peak memory 198456 kb
Host smart-aa05b0bc-e9ff-4a80-a51e-1ef05a535634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203111903 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_escalation_timeout.203111903
Directory /workspace/48.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/48.pwrmgr_glitch.863414756
Short name T591
Test name
Test status
Simulation time 34053940 ps
CPU time 0.61 seconds
Started Jul 26 07:00:47 PM PDT 24
Finished Jul 26 07:00:52 PM PDT 24
Peak memory 197332 kb
Host smart-fe163a0e-4cff-4e3f-8841-89e6917c0dbb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863414756 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_glitch.863414756
Directory /workspace/48.pwrmgr_glitch/latest

Test location /workspace/coverage/default/48.pwrmgr_global_esc.3728248903
Short name T534
Test name
Test status
Simulation time 44468290 ps
CPU time 0.66 seconds
Started Jul 26 07:00:44 PM PDT 24
Finished Jul 26 07:00:44 PM PDT 24
Peak memory 198100 kb
Host smart-591d031a-7806-415a-8094-51f16e40f256
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728248903 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_global_esc.3728248903
Directory /workspace/48.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/48.pwrmgr_reset.510018347
Short name T255
Test name
Test status
Simulation time 69772257 ps
CPU time 0.91 seconds
Started Jul 26 07:00:36 PM PDT 24
Finished Jul 26 07:00:37 PM PDT 24
Peak memory 199160 kb
Host smart-19a22d08-a69c-41d9-ae69-761bc9583160
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510018347 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset.510018347
Directory /workspace/48.pwrmgr_reset/latest

Test location /workspace/coverage/default/48.pwrmgr_reset_invalid.1001111437
Short name T299
Test name
Test status
Simulation time 110327567 ps
CPU time 0.96 seconds
Started Jul 26 07:00:34 PM PDT 24
Finished Jul 26 07:00:35 PM PDT 24
Peak memory 209444 kb
Host smart-b21d481d-5a2d-475f-8610-d5a3f2975548
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001111437 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset_invalid.1001111437
Directory /workspace/48.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/48.pwrmgr_sec_cm_rstmgr_intersig_mubi.262350034
Short name T573
Test name
Test status
Simulation time 63949680 ps
CPU time 0.82 seconds
Started Jul 26 07:00:43 PM PDT 24
Finished Jul 26 07:00:44 PM PDT 24
Peak memory 198140 kb
Host smart-a3677de1-d1fc-42c8-b16d-5e4fba218169
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262350034 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_rstmgr_intersig_
mubi.262350034
Directory /workspace/48.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/48.pwrmgr_smoke.1769409129
Short name T258
Test name
Test status
Simulation time 114418274 ps
CPU time 0.64 seconds
Started Jul 26 07:00:42 PM PDT 24
Finished Jul 26 07:00:42 PM PDT 24
Peak memory 198552 kb
Host smart-deb54ca8-7334-4fc3-8303-d4ebd34e0a51
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769409129 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_smoke.1769409129
Directory /workspace/48.pwrmgr_smoke/latest

Test location /workspace/coverage/default/49.pwrmgr_aborted_low_power.2070591585
Short name T624
Test name
Test status
Simulation time 57734517 ps
CPU time 0.69 seconds
Started Jul 26 07:00:54 PM PDT 24
Finished Jul 26 07:00:55 PM PDT 24
Peak memory 198908 kb
Host smart-f2847d23-a47a-4cc5-b851-58f18a23a281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070591585 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_aborted_low_power.2070591585
Directory /workspace/49.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/49.pwrmgr_disable_rom_integrity_check.4254041321
Short name T151
Test name
Test status
Simulation time 73622928 ps
CPU time 0.68 seconds
Started Jul 26 07:00:40 PM PDT 24
Finished Jul 26 07:00:41 PM PDT 24
Peak memory 198472 kb
Host smart-2c6828b5-b2e7-4e9f-ae6f-880992cb850f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254041321 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_dis
able_rom_integrity_check.4254041321
Directory /workspace/49.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/49.pwrmgr_esc_clk_rst_malfunc.1396426065
Short name T522
Test name
Test status
Simulation time 29950595 ps
CPU time 0.62 seconds
Started Jul 26 07:00:42 PM PDT 24
Finished Jul 26 07:00:43 PM PDT 24
Peak memory 198140 kb
Host smart-21050f41-a8df-442a-9bd0-d795c44bf5d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396426065 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_esc_clk_rst
_malfunc.1396426065
Directory /workspace/49.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/49.pwrmgr_escalation_timeout.3139419872
Short name T555
Test name
Test status
Simulation time 165391271 ps
CPU time 1.01 seconds
Started Jul 26 07:00:40 PM PDT 24
Finished Jul 26 07:00:41 PM PDT 24
Peak memory 198460 kb
Host smart-be0a6197-0e46-4c41-ac4b-b504194aa74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139419872 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_escalation_timeout.3139419872
Directory /workspace/49.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/49.pwrmgr_glitch.2416546477
Short name T309
Test name
Test status
Simulation time 45927583 ps
CPU time 0.66 seconds
Started Jul 26 07:00:41 PM PDT 24
Finished Jul 26 07:00:42 PM PDT 24
Peak memory 197420 kb
Host smart-3a6cb4ab-4591-498f-8ef4-8b6af9e6fe4a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416546477 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_glitch.2416546477
Directory /workspace/49.pwrmgr_glitch/latest

Test location /workspace/coverage/default/49.pwrmgr_global_esc.4071179559
Short name T267
Test name
Test status
Simulation time 71983751 ps
CPU time 0.59 seconds
Started Jul 26 07:00:49 PM PDT 24
Finished Jul 26 07:00:49 PM PDT 24
Peak memory 198044 kb
Host smart-14c5aa91-92ea-4e46-9b16-477af469a10a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071179559 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_global_esc.4071179559
Directory /workspace/49.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/49.pwrmgr_lowpower_invalid.1379002975
Short name T375
Test name
Test status
Simulation time 51889753 ps
CPU time 0.66 seconds
Started Jul 26 07:00:52 PM PDT 24
Finished Jul 26 07:00:53 PM PDT 24
Peak memory 201416 kb
Host smart-70f78beb-041f-4678-8baa-234bf897e9e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379002975 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_lowpower_inval
id.1379002975
Directory /workspace/49.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/49.pwrmgr_reset.1985278838
Short name T245
Test name
Test status
Simulation time 110925195 ps
CPU time 0.77 seconds
Started Jul 26 07:00:37 PM PDT 24
Finished Jul 26 07:00:37 PM PDT 24
Peak memory 199160 kb
Host smart-dbaa372a-11ea-435d-81c8-e1384639f46f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985278838 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset.1985278838
Directory /workspace/49.pwrmgr_reset/latest

Test location /workspace/coverage/default/49.pwrmgr_reset_invalid.1725722641
Short name T538
Test name
Test status
Simulation time 147582792 ps
CPU time 0.81 seconds
Started Jul 26 07:00:43 PM PDT 24
Finished Jul 26 07:00:49 PM PDT 24
Peak memory 209492 kb
Host smart-79fa5c6e-04fb-451e-a612-190c63f04a61
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725722641 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset_invalid.1725722641
Directory /workspace/49.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/49.pwrmgr_sec_cm_rstmgr_intersig_mubi.1842454325
Short name T575
Test name
Test status
Simulation time 50708974 ps
CPU time 0.79 seconds
Started Jul 26 07:00:40 PM PDT 24
Finished Jul 26 07:00:41 PM PDT 24
Peak memory 198240 kb
Host smart-fe51e0e2-c152-4b88-a64e-a4cfcabf9871
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842454325 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1842454325
Directory /workspace/49.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/49.pwrmgr_smoke.208566651
Short name T129
Test name
Test status
Simulation time 29793607 ps
CPU time 0.67 seconds
Started Jul 26 07:00:44 PM PDT 24
Finished Jul 26 07:00:45 PM PDT 24
Peak memory 199380 kb
Host smart-c831d94d-d95a-427d-8ce4-78fe83f859f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208566651 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_smoke.208566651
Directory /workspace/49.pwrmgr_smoke/latest

Test location /workspace/coverage/default/5.pwrmgr_disable_rom_integrity_check.1357078604
Short name T140
Test name
Test status
Simulation time 73277165 ps
CPU time 0.73 seconds
Started Jul 26 06:58:03 PM PDT 24
Finished Jul 26 06:58:04 PM PDT 24
Peak memory 199192 kb
Host smart-b7b78507-27f9-428a-ba18-9eb90c31f997
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357078604 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_disa
ble_rom_integrity_check.1357078604
Directory /workspace/5.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/5.pwrmgr_esc_clk_rst_malfunc.3050546411
Short name T278
Test name
Test status
Simulation time 39086295 ps
CPU time 0.58 seconds
Started Jul 26 06:58:04 PM PDT 24
Finished Jul 26 06:58:05 PM PDT 24
Peak memory 198108 kb
Host smart-7226c945-0141-465b-96ea-24dad2071cd8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050546411 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_esc_clk_rst_
malfunc.3050546411
Directory /workspace/5.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/5.pwrmgr_escalation_timeout.2162371863
Short name T609
Test name
Test status
Simulation time 304215724 ps
CPU time 1 seconds
Started Jul 26 06:58:04 PM PDT 24
Finished Jul 26 06:58:05 PM PDT 24
Peak memory 198152 kb
Host smart-ef19b919-0ef6-4f33-b110-7c3622d73bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162371863 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_escalation_timeout.2162371863
Directory /workspace/5.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/5.pwrmgr_glitch.4132278455
Short name T9
Test name
Test status
Simulation time 76225526 ps
CPU time 0.64 seconds
Started Jul 26 06:58:02 PM PDT 24
Finished Jul 26 06:58:03 PM PDT 24
Peak memory 197336 kb
Host smart-131e0e25-aace-4105-9553-27c16cfd57dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132278455 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_glitch.4132278455
Directory /workspace/5.pwrmgr_glitch/latest

Test location /workspace/coverage/default/5.pwrmgr_global_esc.574875027
Short name T52
Test name
Test status
Simulation time 44896120 ps
CPU time 0.63 seconds
Started Jul 26 06:58:03 PM PDT 24
Finished Jul 26 06:58:04 PM PDT 24
Peak memory 198092 kb
Host smart-b64ff09a-d6dd-4db7-b589-1e6fc97a84d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574875027 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_global_esc.574875027
Directory /workspace/5.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/5.pwrmgr_lowpower_invalid.1822305232
Short name T174
Test name
Test status
Simulation time 42369544 ps
CPU time 0.72 seconds
Started Jul 26 06:58:04 PM PDT 24
Finished Jul 26 06:58:05 PM PDT 24
Peak memory 201544 kb
Host smart-76c7f72d-4367-4f72-a12e-be324675a96c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822305232 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_lowpower_invali
d.1822305232
Directory /workspace/5.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/5.pwrmgr_reset.3154602322
Short name T45
Test name
Test status
Simulation time 51013206 ps
CPU time 0.61 seconds
Started Jul 26 06:57:56 PM PDT 24
Finished Jul 26 06:57:57 PM PDT 24
Peak memory 198348 kb
Host smart-3cf3aa53-26ca-463f-acf3-fb73fd5afad6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154602322 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset.3154602322
Directory /workspace/5.pwrmgr_reset/latest

Test location /workspace/coverage/default/5.pwrmgr_reset_invalid.4213315249
Short name T437
Test name
Test status
Simulation time 433756101 ps
CPU time 0.78 seconds
Started Jul 26 06:58:04 PM PDT 24
Finished Jul 26 06:58:05 PM PDT 24
Peak memory 209528 kb
Host smart-d3462c2f-147d-4cd1-8d29-bf4334435379
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213315249 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset_invalid.4213315249
Directory /workspace/5.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/5.pwrmgr_sec_cm_rstmgr_intersig_mubi.104465163
Short name T541
Test name
Test status
Simulation time 81455213 ps
CPU time 0.67 seconds
Started Jul 26 06:57:53 PM PDT 24
Finished Jul 26 06:57:54 PM PDT 24
Peak memory 198140 kb
Host smart-eaf45997-04c9-4631-8870-d9724a7585e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104465163 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.104465163
Directory /workspace/5.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/5.pwrmgr_smoke.3139431451
Short name T434
Test name
Test status
Simulation time 62488347 ps
CPU time 0.64 seconds
Started Jul 26 06:57:54 PM PDT 24
Finished Jul 26 06:57:54 PM PDT 24
Peak memory 198580 kb
Host smart-ee328f47-8393-4885-a514-12a8d02846c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139431451 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_smoke.3139431451
Directory /workspace/5.pwrmgr_smoke/latest

Test location /workspace/coverage/default/5.pwrmgr_wakeup.3938614903
Short name T54
Test name
Test status
Simulation time 64773014 ps
CPU time 0.7 seconds
Started Jul 26 06:57:55 PM PDT 24
Finished Jul 26 06:57:56 PM PDT 24
Peak memory 198292 kb
Host smart-2f7c607f-bb11-4edf-bba6-81f359a29987
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938614903 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_wakeup.3938614903
Directory /workspace/5.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/6.pwrmgr_aborted_low_power.2566102928
Short name T104
Test name
Test status
Simulation time 96385128 ps
CPU time 0.73 seconds
Started Jul 26 06:58:06 PM PDT 24
Finished Jul 26 06:58:07 PM PDT 24
Peak memory 198936 kb
Host smart-0539ee4a-c826-4b7a-9618-dbe6c4f19f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566102928 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_aborted_low_power.2566102928
Directory /workspace/6.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/6.pwrmgr_disable_rom_integrity_check.4256218387
Short name T142
Test name
Test status
Simulation time 60378143 ps
CPU time 0.8 seconds
Started Jul 26 06:58:02 PM PDT 24
Finished Jul 26 06:58:03 PM PDT 24
Peak memory 198772 kb
Host smart-64c27496-903c-4adb-96b2-cb167110fcbd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256218387 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_disa
ble_rom_integrity_check.4256218387
Directory /workspace/6.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/6.pwrmgr_esc_clk_rst_malfunc.1085084343
Short name T377
Test name
Test status
Simulation time 37175012 ps
CPU time 0.58 seconds
Started Jul 26 06:58:04 PM PDT 24
Finished Jul 26 06:58:05 PM PDT 24
Peak memory 197452 kb
Host smart-65556366-ed77-41a6-9732-b04e3c2b8d7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085084343 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_esc_clk_rst_
malfunc.1085084343
Directory /workspace/6.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/6.pwrmgr_escalation_timeout.1605002908
Short name T138
Test name
Test status
Simulation time 282345032 ps
CPU time 0.98 seconds
Started Jul 26 06:58:05 PM PDT 24
Finished Jul 26 06:58:06 PM PDT 24
Peak memory 198152 kb
Host smart-ea2e08d6-2064-44fe-9092-d86a3d6d2a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605002908 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_escalation_timeout.1605002908
Directory /workspace/6.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/6.pwrmgr_glitch.4126978574
Short name T467
Test name
Test status
Simulation time 35182978 ps
CPU time 0.64 seconds
Started Jul 26 06:58:06 PM PDT 24
Finished Jul 26 06:58:06 PM PDT 24
Peak memory 197292 kb
Host smart-2a875eb1-b4eb-4951-9450-8ba31fbef795
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126978574 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_glitch.4126978574
Directory /workspace/6.pwrmgr_glitch/latest

Test location /workspace/coverage/default/6.pwrmgr_global_esc.574684617
Short name T259
Test name
Test status
Simulation time 41812536 ps
CPU time 0.67 seconds
Started Jul 26 06:58:04 PM PDT 24
Finished Jul 26 06:58:05 PM PDT 24
Peak memory 198008 kb
Host smart-23c586a7-2f48-40ef-9b40-316cea887156
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574684617 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_global_esc.574684617
Directory /workspace/6.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/6.pwrmgr_lowpower_invalid.2301023520
Short name T599
Test name
Test status
Simulation time 51194616 ps
CPU time 0.72 seconds
Started Jul 26 06:58:05 PM PDT 24
Finished Jul 26 06:58:06 PM PDT 24
Peak memory 201420 kb
Host smart-d37d4e38-23bb-46ed-ba0f-1c4eaab6f086
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301023520 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_lowpower_invali
d.2301023520
Directory /workspace/6.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/6.pwrmgr_reset.3107250442
Short name T399
Test name
Test status
Simulation time 60937182 ps
CPU time 0.63 seconds
Started Jul 26 06:58:03 PM PDT 24
Finished Jul 26 06:58:04 PM PDT 24
Peak memory 199128 kb
Host smart-8a2cd559-1707-46be-ba43-cdf530483428
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107250442 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset.3107250442
Directory /workspace/6.pwrmgr_reset/latest

Test location /workspace/coverage/default/6.pwrmgr_reset_invalid.3784093251
Short name T595
Test name
Test status
Simulation time 154074895 ps
CPU time 0.8 seconds
Started Jul 26 06:58:06 PM PDT 24
Finished Jul 26 06:58:06 PM PDT 24
Peak memory 209424 kb
Host smart-0a4cf998-5965-456e-a6eb-98935e373e8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784093251 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset_invalid.3784093251
Directory /workspace/6.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/6.pwrmgr_sec_cm_rstmgr_intersig_mubi.2584659678
Short name T265
Test name
Test status
Simulation time 51332126 ps
CPU time 0.88 seconds
Started Jul 26 06:58:03 PM PDT 24
Finished Jul 26 06:58:04 PM PDT 24
Peak memory 199320 kb
Host smart-2533652a-729f-4d1b-9608-d9a1ebc08d3d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584659678 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2584659678
Directory /workspace/6.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/6.pwrmgr_smoke.3413155076
Short name T222
Test name
Test status
Simulation time 28843399 ps
CPU time 0.73 seconds
Started Jul 26 06:58:04 PM PDT 24
Finished Jul 26 06:58:04 PM PDT 24
Peak memory 199436 kb
Host smart-e5f80be8-bf43-47c3-81dd-df6249ac9248
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413155076 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_smoke.3413155076
Directory /workspace/6.pwrmgr_smoke/latest

Test location /workspace/coverage/default/7.pwrmgr_aborted_low_power.656194111
Short name T102
Test name
Test status
Simulation time 31771051 ps
CPU time 0.81 seconds
Started Jul 26 06:58:02 PM PDT 24
Finished Jul 26 06:58:03 PM PDT 24
Peak memory 198996 kb
Host smart-cb433acf-9038-4e5b-b4ab-5c42bde3d780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656194111 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_aborted_low_power.656194111
Directory /workspace/7.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/7.pwrmgr_disable_rom_integrity_check.1940084927
Short name T349
Test name
Test status
Simulation time 73563612 ps
CPU time 0.66 seconds
Started Jul 26 06:58:11 PM PDT 24
Finished Jul 26 06:58:12 PM PDT 24
Peak memory 199104 kb
Host smart-b9ebe217-43d9-4f05-8f40-8ba4c9532981
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940084927 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_disa
ble_rom_integrity_check.1940084927
Directory /workspace/7.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.2808122173
Short name T402
Test name
Test status
Simulation time 29099949 ps
CPU time 0.62 seconds
Started Jul 26 06:58:13 PM PDT 24
Finished Jul 26 06:58:14 PM PDT 24
Peak memory 198072 kb
Host smart-a96b426c-e6c7-487c-b9ea-ef368ad2edd5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808122173 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_esc_clk_rst_
malfunc.2808122173
Directory /workspace/7.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/7.pwrmgr_escalation_timeout.2981750120
Short name T516
Test name
Test status
Simulation time 1378769588 ps
CPU time 0.97 seconds
Started Jul 26 06:58:14 PM PDT 24
Finished Jul 26 06:58:15 PM PDT 24
Peak memory 198168 kb
Host smart-aae2dfc8-a3c8-41aa-9bdb-a988f3391505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981750120 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_escalation_timeout.2981750120
Directory /workspace/7.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/7.pwrmgr_glitch.1916781015
Short name T615
Test name
Test status
Simulation time 51415738 ps
CPU time 0.67 seconds
Started Jul 26 06:58:13 PM PDT 24
Finished Jul 26 06:58:14 PM PDT 24
Peak memory 197444 kb
Host smart-100899cb-1a20-41cf-bcc7-9cfc820f13fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916781015 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_glitch.1916781015
Directory /workspace/7.pwrmgr_glitch/latest

Test location /workspace/coverage/default/7.pwrmgr_global_esc.1307025615
Short name T213
Test name
Test status
Simulation time 23451911 ps
CPU time 0.65 seconds
Started Jul 26 06:58:09 PM PDT 24
Finished Jul 26 06:58:10 PM PDT 24
Peak memory 198092 kb
Host smart-e7a2a84d-8bd0-43e4-8973-7b7b351ce2eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307025615 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_global_esc.1307025615
Directory /workspace/7.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/7.pwrmgr_lowpower_invalid.243868563
Short name T445
Test name
Test status
Simulation time 48001295 ps
CPU time 0.74 seconds
Started Jul 26 06:58:11 PM PDT 24
Finished Jul 26 06:58:11 PM PDT 24
Peak memory 201392 kb
Host smart-46941b20-698b-479e-92d5-1ffa849a058b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243868563 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_lowpower_invalid
.243868563
Directory /workspace/7.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/7.pwrmgr_reset.2142080700
Short name T488
Test name
Test status
Simulation time 83856213 ps
CPU time 0.91 seconds
Started Jul 26 06:58:04 PM PDT 24
Finished Jul 26 06:58:05 PM PDT 24
Peak memory 199152 kb
Host smart-b0686ecf-22ab-4a60-9788-659d799b54ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142080700 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset.2142080700
Directory /workspace/7.pwrmgr_reset/latest

Test location /workspace/coverage/default/7.pwrmgr_reset_invalid.2405155524
Short name T601
Test name
Test status
Simulation time 99813659 ps
CPU time 1.02 seconds
Started Jul 26 06:58:11 PM PDT 24
Finished Jul 26 06:58:12 PM PDT 24
Peak memory 209560 kb
Host smart-cb867805-2299-4c1f-b2e6-1763193b35bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405155524 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset_invalid.2405155524
Directory /workspace/7.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.3866409317
Short name T536
Test name
Test status
Simulation time 188768931 ps
CPU time 0.82 seconds
Started Jul 26 06:58:11 PM PDT 24
Finished Jul 26 06:58:12 PM PDT 24
Peak memory 199216 kb
Host smart-a94c18da-da55-46ef-b498-8bdef4e08c48
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866409317 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_rstmgr_intersig_
mubi.3866409317
Directory /workspace/7.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/7.pwrmgr_smoke.3784182460
Short name T339
Test name
Test status
Simulation time 32778189 ps
CPU time 0.69 seconds
Started Jul 26 06:58:01 PM PDT 24
Finished Jul 26 06:58:02 PM PDT 24
Peak memory 199432 kb
Host smart-5d7aeff2-3cbe-43cb-8613-0bc9cd770c88
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784182460 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_smoke.3784182460
Directory /workspace/7.pwrmgr_smoke/latest

Test location /workspace/coverage/default/8.pwrmgr_aborted_low_power.3640064301
Short name T26
Test name
Test status
Simulation time 64163558 ps
CPU time 0.66 seconds
Started Jul 26 06:58:10 PM PDT 24
Finished Jul 26 06:58:11 PM PDT 24
Peak memory 198636 kb
Host smart-7649811a-2efe-4283-b9bc-e9ed047f199c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640064301 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_aborted_low_power.3640064301
Directory /workspace/8.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/8.pwrmgr_disable_rom_integrity_check.514037188
Short name T619
Test name
Test status
Simulation time 191387889 ps
CPU time 0.64 seconds
Started Jul 26 06:58:17 PM PDT 24
Finished Jul 26 06:58:18 PM PDT 24
Peak memory 198596 kb
Host smart-70a188a9-c3ed-4c41-b725-e7f4ae3baf1a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514037188 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_disab
le_rom_integrity_check.514037188
Directory /workspace/8.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.2423651493
Short name T616
Test name
Test status
Simulation time 37205523 ps
CPU time 0.62 seconds
Started Jul 26 06:58:10 PM PDT 24
Finished Jul 26 06:58:11 PM PDT 24
Peak memory 197380 kb
Host smart-81ea4a9d-205c-4ebb-8f7f-07007a91cb84
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423651493 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_esc_clk_rst_
malfunc.2423651493
Directory /workspace/8.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/8.pwrmgr_escalation_timeout.2854142344
Short name T570
Test name
Test status
Simulation time 488501142 ps
CPU time 0.99 seconds
Started Jul 26 06:58:11 PM PDT 24
Finished Jul 26 06:58:12 PM PDT 24
Peak memory 198164 kb
Host smart-dda902bc-d653-4e9d-bf50-d249616891f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854142344 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_escalation_timeout.2854142344
Directory /workspace/8.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/8.pwrmgr_glitch.2336660222
Short name T208
Test name
Test status
Simulation time 32785783 ps
CPU time 0.64 seconds
Started Jul 26 06:58:20 PM PDT 24
Finished Jul 26 06:58:20 PM PDT 24
Peak memory 198028 kb
Host smart-946f22c1-1300-4a67-8565-58cb9c717a76
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336660222 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_glitch.2336660222
Directory /workspace/8.pwrmgr_glitch/latest

Test location /workspace/coverage/default/8.pwrmgr_global_esc.1746055443
Short name T387
Test name
Test status
Simulation time 42092705 ps
CPU time 0.66 seconds
Started Jul 26 06:58:11 PM PDT 24
Finished Jul 26 06:58:12 PM PDT 24
Peak memory 198160 kb
Host smart-71c7c5f9-49a2-4696-a7da-222ed38bb46e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746055443 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_global_esc.1746055443
Directory /workspace/8.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/8.pwrmgr_lowpower_invalid.2645201979
Short name T579
Test name
Test status
Simulation time 186147699 ps
CPU time 0.67 seconds
Started Jul 26 06:58:22 PM PDT 24
Finished Jul 26 06:58:23 PM PDT 24
Peak memory 201416 kb
Host smart-2f04c029-35c1-45d5-bfb4-905efb28efb5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645201979 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_lowpower_invali
d.2645201979
Directory /workspace/8.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/8.pwrmgr_reset.2982461679
Short name T227
Test name
Test status
Simulation time 77889818 ps
CPU time 0.78 seconds
Started Jul 26 06:58:13 PM PDT 24
Finished Jul 26 06:58:14 PM PDT 24
Peak memory 199148 kb
Host smart-73c1799f-21fa-49e2-99eb-51dfe619900e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982461679 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset.2982461679
Directory /workspace/8.pwrmgr_reset/latest

Test location /workspace/coverage/default/8.pwrmgr_reset_invalid.2062428598
Short name T625
Test name
Test status
Simulation time 164236186 ps
CPU time 0.8 seconds
Started Jul 26 06:58:18 PM PDT 24
Finished Jul 26 06:58:19 PM PDT 24
Peak memory 209712 kb
Host smart-021e8cc0-06bb-411c-94e6-2d49558330e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062428598 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset_invalid.2062428598
Directory /workspace/8.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.1769178652
Short name T492
Test name
Test status
Simulation time 52579182 ps
CPU time 0.82 seconds
Started Jul 26 06:58:13 PM PDT 24
Finished Jul 26 06:58:14 PM PDT 24
Peak memory 198200 kb
Host smart-58ebaf12-bb76-4abe-ad8f-4b6ee3851aa1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769178652 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_rstmgr_intersig_
mubi.1769178652
Directory /workspace/8.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/8.pwrmgr_smoke.1713693876
Short name T62
Test name
Test status
Simulation time 62005927 ps
CPU time 0.64 seconds
Started Jul 26 06:58:13 PM PDT 24
Finished Jul 26 06:58:14 PM PDT 24
Peak memory 199416 kb
Host smart-0733b757-41ad-4a89-bda4-5e66fdff6104
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713693876 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_smoke.1713693876
Directory /workspace/8.pwrmgr_smoke/latest

Test location /workspace/coverage/default/9.pwrmgr_aborted_low_power.3686705213
Short name T613
Test name
Test status
Simulation time 96165343 ps
CPU time 0.76 seconds
Started Jul 26 06:58:20 PM PDT 24
Finished Jul 26 06:58:21 PM PDT 24
Peak memory 200124 kb
Host smart-7544194e-cb7a-4cd6-b1cd-8864d0d65fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686705213 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_aborted_low_power.3686705213
Directory /workspace/9.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/9.pwrmgr_disable_rom_integrity_check.4004236979
Short name T442
Test name
Test status
Simulation time 64233420 ps
CPU time 0.81 seconds
Started Jul 26 06:58:19 PM PDT 24
Finished Jul 26 06:58:20 PM PDT 24
Peak memory 198712 kb
Host smart-c4d6597b-8464-460c-8087-eb20c5088d64
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004236979 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_disa
ble_rom_integrity_check.4004236979
Directory /workspace/9.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.2497753747
Short name T332
Test name
Test status
Simulation time 40374882 ps
CPU time 0.6 seconds
Started Jul 26 06:58:20 PM PDT 24
Finished Jul 26 06:58:21 PM PDT 24
Peak memory 198036 kb
Host smart-82540cef-48bd-41e7-8080-8a5d5bb91e8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497753747 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_esc_clk_rst_
malfunc.2497753747
Directory /workspace/9.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/9.pwrmgr_escalation_timeout.3404936589
Short name T550
Test name
Test status
Simulation time 160037992 ps
CPU time 0.99 seconds
Started Jul 26 06:58:17 PM PDT 24
Finished Jul 26 06:58:18 PM PDT 24
Peak memory 198436 kb
Host smart-8836cf30-d80d-4cea-bae3-5c29b4a5d33e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404936589 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_escalation_timeout.3404936589
Directory /workspace/9.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/9.pwrmgr_glitch.2335239543
Short name T229
Test name
Test status
Simulation time 47999961 ps
CPU time 0.57 seconds
Started Jul 26 06:58:17 PM PDT 24
Finished Jul 26 06:58:17 PM PDT 24
Peak memory 198128 kb
Host smart-800888c5-cfe7-4095-95d4-137c9c50006a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335239543 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_glitch.2335239543
Directory /workspace/9.pwrmgr_glitch/latest

Test location /workspace/coverage/default/9.pwrmgr_global_esc.2560665132
Short name T242
Test name
Test status
Simulation time 36507429 ps
CPU time 0.66 seconds
Started Jul 26 06:58:19 PM PDT 24
Finished Jul 26 06:58:20 PM PDT 24
Peak memory 198436 kb
Host smart-749e2395-d21b-4264-a74b-a4fc7647e114
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560665132 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_global_esc.2560665132
Directory /workspace/9.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/9.pwrmgr_lowpower_invalid.3206482832
Short name T185
Test name
Test status
Simulation time 79513378 ps
CPU time 0.65 seconds
Started Jul 26 06:58:18 PM PDT 24
Finished Jul 26 06:58:19 PM PDT 24
Peak memory 201408 kb
Host smart-c1eac8d9-d42e-47a1-809d-1104f4551341
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206482832 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_lowpower_invali
d.3206482832
Directory /workspace/9.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/9.pwrmgr_reset.3005427346
Short name T438
Test name
Test status
Simulation time 140253799 ps
CPU time 0.74 seconds
Started Jul 26 06:58:17 PM PDT 24
Finished Jul 26 06:58:17 PM PDT 24
Peak memory 198448 kb
Host smart-0c9705b0-583b-440a-ba60-d2d2df24a20b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005427346 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset.3005427346
Directory /workspace/9.pwrmgr_reset/latest

Test location /workspace/coverage/default/9.pwrmgr_reset_invalid.3126480446
Short name T484
Test name
Test status
Simulation time 105504339 ps
CPU time 0.95 seconds
Started Jul 26 06:58:18 PM PDT 24
Finished Jul 26 06:58:20 PM PDT 24
Peak memory 209468 kb
Host smart-90820460-1ebf-4538-9807-1445d6c03515
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126480446 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset_invalid.3126480446
Directory /workspace/9.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.4197400472
Short name T532
Test name
Test status
Simulation time 104365951 ps
CPU time 0.71 seconds
Started Jul 26 06:58:17 PM PDT 24
Finished Jul 26 06:58:18 PM PDT 24
Peak memory 198184 kb
Host smart-15880479-e9e7-440f-a6cf-a029c6a4e480
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197400472 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_rstmgr_intersig_
mubi.4197400472
Directory /workspace/9.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/9.pwrmgr_smoke.2556244111
Short name T515
Test name
Test status
Simulation time 29312869 ps
CPU time 0.67 seconds
Started Jul 26 06:58:17 PM PDT 24
Finished Jul 26 06:58:18 PM PDT 24
Peak memory 198556 kb
Host smart-07c13fa6-6580-4c24-9fe2-4b1a094ee6d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556244111 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_smoke.2556244111
Directory /workspace/9.pwrmgr_smoke/latest
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