---

Detail Report for Assertions

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AlertNumCheck_A	0	0	574	574	0	0
tb.dut.AlertsKnownO_A	0	0	2295225	2143626	0	0
tb.dut.AstKnownO_A	0	0	2295225	2143626	0	0
tb.dut.ClkKnownO_A	0	0	2295225	2143626	0	0
tb.dut.ClkRatio_A	0	0	2295225	2143626	0	0
tb.dut.FpvSecCmFsmCheck_A	0	0	2295225	60	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	2295225	60	0	0
tb.dut.FpvSecCmSlowFsmCheck_A	0	0	304923	60	0	0
tb.dut.GlitchStatusPersist_A	0	0	2295225	497	0	0
tb.dut.IntrKnownO_A	0	0	2295225	2143626	0	0
tb.dut.LcKnownO_A	0	0	2295225	2143626	0	0
tb.dut.OtpKnownO_A	0	0	2295225	2143626	0	0
tb.dut.PwrmgrSecCmEscToLCReset_A	0	0	2295225	533	0	0
tb.dut.PwrmgrSecCmEscToSlowResetReq_A	0	0	304923	2791	0	0
tb.dut.PwrmgrSecCmFsmEscToResetReq_A	0	0	2295225	24947	0	0
tb.dut.RstKnownO_A	0	0	2295225	2143626	0	0
tb.dut.TlAReadyKnownO_A	0	0	2295225	2143626	0	0
tb.dut.TlDValidKnownO_A	0	0	2295225	2143626	0	0
tb.dut.clkmgr_pwrmgr_io_sva_if.StatusFall_A	0	0	2295225	3324	0	0
tb.dut.clkmgr_pwrmgr_io_sva_if.StatusRise_A	0	0	2295225	4475	0	0
tb.dut.clkmgr_pwrmgr_main_sva_if.StatusFall_A	0	0	2295225	3324	0	0
tb.dut.clkmgr_pwrmgr_main_sva_if.StatusRise_A	0	0	2295225	4475	0	0
tb.dut.clkmgr_pwrmgr_usb_sva_if.StatusFall_A	0	0	2295225	3201	0	0
tb.dut.clkmgr_pwrmgr_usb_sva_if.StatusRise_A	0	0	2295225	4322	0	0
tb.dut.intr_wakeup.IntrTKind_A	0	0	574	574	0	0
tb.dut.pwrmgr_clock_enables_sva_if.CoreClkPwrDown_A	0	0	304923	83	0	0
tb.dut.pwrmgr_clock_enables_sva_if.CoreClkPwrUp_A	0	0	304923	2466	0	0
tb.dut.pwrmgr_clock_enables_sva_if.IoClkPwrDown_A	0	0	304923	83	0	0
tb.dut.pwrmgr_clock_enables_sva_if.IoClkPwrUp_A	0	0	304923	2466	0	0
tb.dut.pwrmgr_clock_enables_sva_if.UsbClkActive_A	0	0	304923	128	0	0
tb.dut.pwrmgr_clock_enables_sva_if.UsbClkPwrDown_A	0	0	304923	83	0	0
tb.dut.pwrmgr_clock_enables_sva_if.UsbClkPwrUp_A	0	0	304923	2466	0	0
tb.dut.pwrmgr_csr_assert.TlulOOBAddrErr_A	0	0	2892134	13765	0	0
tb.dut.pwrmgr_csr_assert.intr_enable_rd_A	0	0	2892134	3100	0	0
tb.dut.pwrmgr_csr_assert.reset_en_rd_A	0	0	2892134	1478	0	0
tb.dut.pwrmgr_csr_assert.reset_en_regwen_rd_A	0	0	2892134	1357	0	0
tb.dut.pwrmgr_csr_assert.wake_info_capture_dis_rd_A	0	0	2892134	1330	0	0
tb.dut.pwrmgr_csr_assert.wakeup_en_rd_A	0	0	2892134	1684	0	0
tb.dut.pwrmgr_csr_assert.wakeup_en_regwen_rd_A	0	0	2892134	1284	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].LcHandshakeOff_A	0	0	2295225	158	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].LcHandshakeOn_A	0	0	2295225	15713	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].SysHandshakeOff_A	0	0	2295225	149835	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].SysHandshakeOn_A	0	0	2295225	15713	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].LcHandshakeOff_A	0	0	2295225	158	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].LcHandshakeOn_A	0	0	2295225	15713	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].SysHandshakeOff_A	0	0	2295225	149835	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].SysHandshakeOn_A	0	0	2295225	15713	0	0
tb.dut.pwrmgr_sec_cm_checker_assert.EscClkStopEscTimeout_A	0	0	2295595	5658	0	0
tb.dut.pwrmgr_sec_cm_checker_assert.EscTimeoutStoppedByClReset_A	0	0	2295225	79532	0	0
tb.dut.pwrmgr_sec_cm_checker_assert.EscTimeoutTriggersReset_A	0	0	304923	328	0	0
tb.dut.pwrmgr_sec_cm_checker_assert.RomAllowActiveState_A	0	0	2295225	4115	0	0
tb.dut.pwrmgr_sec_cm_checker_assert.RomAllowCheckGoodState_A	0	0	2295225	4165	0	0
tb.dut.pwrmgr_sec_cm_checker_assert.RomBlockActiveState_A	0	0	2295225	26050	0	0
tb.dut.pwrmgr_sec_cm_checker_assert.RomBlockCheckGoodState_A	0	0	2295225	18624	0	0
tb.dut.pwrmgr_sec_cm_checker_assert.RomIntgChkDisFalse_A	0	0	2295225	2124514	0	0
tb.dut.pwrmgr_sec_cm_checker_assert.RomIntgChkDisTrue_A	0	0	2295225	19112	0	0
tb.dut.pwrmgr_sec_cm_checker_assert.RstreqChkEsctimeout_A	0	0	2295225	1053	0	0
tb.dut.pwrmgr_sec_cm_checker_assert.RstreqChkFsmterm_A	0	0	2295225	120	0	0
tb.dut.pwrmgr_sec_cm_checker_assert.RstreqChkGlbesc_A	0	0	2295225	1053	0	0
tb.dut.pwrmgr_sec_cm_checker_assert.RstreqChkMainpd_A	0	0	2295225	53028	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	2892134	119487	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	2892134	2701363	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	2892134	2701363	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	2892134	158610	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	2892134	2701363	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	2892134	2701363	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[120].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[143].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[145].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[146].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[149].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[14].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[150].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[151].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[152].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[153].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[154].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[155].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[156].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[157].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[158].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[159].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[15].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[160].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[161].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[162].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[163].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[164].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[165].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[166].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[167].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[168].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[169].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[16].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[170].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[171].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[172].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[173].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[174].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[175].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[176].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[177].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[178].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[179].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[17].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[180].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[181].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[182].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[183].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[184].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[185].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[186].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[187].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[188].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[189].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[18].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[190].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[191].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[192].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[193].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[194].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[195].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[196].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[197].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[198].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[199].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[19].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[1].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[200].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[201].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[202].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[203].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[204].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
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tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A	0	0	739	739	0	0
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tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A	0	0	2892134	5722	0	0
tb.dut.tlul_assert_device.gen_device.contigMask_M	0	0	2892614	44889	0	0
tb.dut.tlul_assert_device.gen_device.dDataKnown_A	0	0	2892614	50356	0	0
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tb.dut.tlul_assert_device.gen_device.legalAParam_M	0	0	2892614	119487	0	0
tb.dut.tlul_assert_device.gen_device.legalDParam_A	0	0	2892614	158613	0	0
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M	0	0	2892614	119487	0	0
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A	0	0	2892614	158613	0	0
tb.dut.tlul_assert_device.gen_device.respOpcode_A	0	0	2892614	158613	0	0
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A	0	0	2892614	158613	0	0
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A	0	0	2892134	3286	0	0
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A	0	0	2892134	2442	0	0
tb.dut.tlul_assert_device.p_dbw.TlDbw_A	0	0	739	739	0	0
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tb.dut.u_reg.en2addrHit	0	0	2892134	64137	0	0
tb.dut.u_reg.reAfterRv	0	0	2892134	64136	0	0
tb.dut.u_reg.rePulse	0	0	2892134	35020	0	0
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tb.dut.u_reg.u_reg_if.MatchedWidthAssert	0	0	739	739	0	0
tb.dut.u_reg.u_reg_if.u_err.dataWidthOnly32_A	0	0	739	739	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	739	739	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	739	739	0	0
tb.dut.u_reg.u_rsp_intg_gen.DataWidthCheck_A	0	0	739	739	0	0
tb.dut.u_reg.u_rsp_intg_gen.PayLoadWidthCheck	0	0	739	739	0	0
tb.dut.u_reg.wePulse	0	0	2892134	29116	0	0
tb.dut.u_slow_fsm.IntRstReq_A	0	0	192428	186158	0	0
tb.dut.u_slow_fsm.u_state_regs.AssertConnected_A	0	0	574	574	0	0
tb.dut.u_slow_fsm.u_state_regs_A	0	0	304923	294818	0	0

Assertions Incomplete:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_cdc.u_sync_rom_ctrl.gen_flops.gen_stable_chks.OutputDelay_A	0	0	2295225	2137563	0	1722
tb.dut.u_prim_lc_sync_dft_en.gen_flops.OutputDelay_A	0	0	2295225	2137563	0	1722
tb.dut.u_prim_lc_sync_hw_debug_en.gen_flops.OutputDelay_A	0	0	2295225	2137563	0	1722

Assertions Excluded:

ASSERTIONS	CATEGORY	SEVERITY	EXCLUSION	EXCLUDE ANNOTATION	SRC
tb.dut.u_esc_timeout.u_ref_timeout.SyncReqAckHoldReq	0	0	Excluded	[UNR] Input req_chk_i is tied to constant 0 and src_req_i to constant 1

---

Detail Report for Cover Sequences

Cover Sequences All Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	2892614	409	409	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	2892614	29	29	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	2892614	31	31	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	2892614	23	23	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	2892614	11	11	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	2892614	21	21	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	2892614	8	8	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	2892614	2597	2597	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	2892614	4857	4857	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	2892614	22488	22488	719

Cover Sequences First Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	2892614	409	409	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	2892614	29	29	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	2892614	31	31	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	2892614	23	23	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	2892614	11	11	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	2892614	21	21	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	2892614	8	8	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	2892614	2597	2597	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	2892614	4857	4857	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	2892614	22488	22488	719