Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	44032	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

32727

1

T1

22

T2

11

T3

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	39877	1			T1	61		T2	11		T3	6
values[0x0]	18306	1			T1	35		T2	9		T3	3
values[0x1]	18576	1			T1	28		T2	7		T3	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35240	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

41519

1

T1

42

T2

13

T3

8

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	267	1			T72	1		T93	1		T204	1
valid_sources[0x01]	222	1			T3	4		T6	1		T10	2
valid_sources[0x02]	202	1			T4	5		T47	1		T14	1
valid_sources[0x03]	224	1			T14	1		T59	2		T205	3
valid_sources[0x04]	255	1			T2	1		T7	6		T15	2
valid_sources[0x05]	418	1			T14	7		T59	3		T41	4
valid_sources[0x06]	188	1			T4	2		T46	1		T206	1
valid_sources[0x07]	262	1			T7	1		T10	1		T47	1
valid_sources[0x08]	354	1			T206	1		T207	3		T123	1
valid_sources[0x09]	246	1			T4	1		T10	3		T143	2
valid_sources[0x0a]	257	1			T1	2		T50	20		T14	1
valid_sources[0x0b]	329	1			T143	1		T59	1		T38	3
valid_sources[0x0c]	265	1			T7	3		T47	1		T48	2
valid_sources[0x0d]	256	1			T1	1		T47	1		T14	1
valid_sources[0x0e]	220	1			T143	3		T206	1		T205	1
valid_sources[0x0f]	368	1			T47	1		T14	2		T143	1
valid_sources[0x10]	225	1			T7	2		T14	1		T143	2
valid_sources[0x11]	372	1			T1	2		T7	2		T9	7
valid_sources[0x12]	221	1			T1	1		T10	4		T47	1
valid_sources[0x13]	226	1			T7	2		T8	1		T14	1
valid_sources[0x14]	312	1			T7	5		T14	2		T42	1
valid_sources[0x15]	211	1			T10	1		T47	1		T46	7
valid_sources[0x16]	373	1			T48	1		T14	6		T59	1
valid_sources[0x17]	340	1			T7	7		T14	3		T143	1
valid_sources[0x18]	301	1			T4	15		T10	1		T47	1
valid_sources[0x19]	342	1			T14	2		T121	1		T93	1
valid_sources[0x1a]	278	1			T7	2		T10	2		T143	1
valid_sources[0x1b]	233	1			T7	5		T205	2		T92	1
valid_sources[0x1c]	353	1			T1	1		T143	2		T46	3
valid_sources[0x1d]	243	1			T1	3		T9	6		T47	1
valid_sources[0x1e]	181	1			T7	1		T143	1		T38	8
valid_sources[0x1f]	403	1			T7	7		T143	1		T30	17
valid_sources[0x20]	239	1			T47	1		T30	3		T46	1
valid_sources[0x21]	368	1			T7	2		T14	3		T88	2
valid_sources[0x22]	263	1			T1	1		T7	1		T14	1
valid_sources[0x23]	270	1			T7	1		T47	1		T15	2
valid_sources[0x24]	334	1			T1	1		T47	1		T15	1
valid_sources[0x25]	225	1			T1	1		T7	2		T14	2
valid_sources[0x26]	276	1			T10	1		T14	2		T42	1
valid_sources[0x27]	226	1			T1	1		T4	3		T59	1
valid_sources[0x28]	339	1			T1	1		T4	4		T7	2
valid_sources[0x29]	273	1			T15	2		T14	1		T46	1
valid_sources[0x2a]	223	1			T1	2		T47	2		T48	1
valid_sources[0x2b]	262	1			T1	4		T14	2		T30	5
valid_sources[0x2c]	326	1			T17	32		T45	1		T32	1
valid_sources[0x2d]	243	1			T9	4		T143	1		T59	4
valid_sources[0x2e]	402	1			T7	2		T10	3		T143	2
valid_sources[0x2f]	253	1			T7	1		T14	3		T38	15
valid_sources[0x30]	210	1			T7	5		T10	1		T47	2
valid_sources[0x31]	346	1			T1	2		T14	3		T42	2
valid_sources[0x32]	353	1			T14	1		T42	1		T41	4
valid_sources[0x33]	396	1			T14	2		T36	1		T206	1
valid_sources[0x34]	264	1			T14	2		T42	1		T59	1
valid_sources[0x35]	283	1			T1	2		T7	13		T48	1
valid_sources[0x36]	539	1			T1	1		T6	1		T143	3
valid_sources[0x37]	259	1			T1	1		T14	1		T42	1
valid_sources[0x38]	218	1			T2	2		T47	1		T14	2
valid_sources[0x39]	252	1			T14	4		T59	1		T46	1
valid_sources[0x3a]	286	1			T1	1		T7	8		T14	2
valid_sources[0x3b]	183	1			T14	3		T205	1		T121	1
valid_sources[0x3c]	206	1			T4	4		T7	3		T14	1
valid_sources[0x3d]	201	1			T143	1		T59	1		T41	1
valid_sources[0x3e]	207	1			T1	1		T6	1		T46	3
valid_sources[0x3f]	340	1			T10	2		T143	3		T59	1
valid_sources[0x40]	298	1			T14	2		T88	1		T143	1
valid_sources[0x41]	361	1			T7	3		T15	1		T14	5
valid_sources[0x42]	249	1			T6	1		T10	1		T14	3
valid_sources[0x43]	204	1			T7	3		T47	1		T14	2
valid_sources[0x44]	371	1			T9	24		T14	1		T38	3
valid_sources[0x45]	445	1			T1	1		T4	2		T48	1
valid_sources[0x46]	516	1			T2	2		T4	1		T8	2
valid_sources[0x47]	259	1			T1	1		T14	1		T143	1
valid_sources[0x48]	238	1			T1	1		T10	2		T14	2
valid_sources[0x49]	300	1			T1	1		T3	1		T7	3
valid_sources[0x4a]	246	1			T1	1		T7	1		T47	2
valid_sources[0x4b]	250	1			T4	1		T8	1		T48	1
valid_sources[0x4c]	248	1			T48	1		T14	3		T24	30
valid_sources[0x4d]	353	1			T47	1		T14	1		T143	1
valid_sources[0x4e]	246	1			T7	1		T10	2		T47	1
valid_sources[0x4f]	476	1			T1	1		T15	1		T14	1
valid_sources[0x50]	298	1			T6	2		T47	1		T14	5
valid_sources[0x51]	306	1			T1	1		T14	1		T143	1
valid_sources[0x52]	200	1			T15	1		T14	1		T59	1
valid_sources[0x53]	299	1			T1	2		T7	1		T14	1
valid_sources[0x54]	239	1			T8	2		T14	2		T59	1
valid_sources[0x55]	501	1			T7	7		T47	1		T14	2
valid_sources[0x56]	443	1			T7	2		T47	1		T14	1
valid_sources[0x57]	258	1			T1	1		T4	4		T10	3
valid_sources[0x58]	511	1			T10	2		T59	1		T206	1
valid_sources[0x59]	401	1			T1	1		T47	1		T37	33
valid_sources[0x5a]	191	1			T14	1		T88	1		T59	2
valid_sources[0x5b]	345	1			T47	1		T48	1		T15	1
valid_sources[0x5c]	220	1			T1	1		T47	3		T48	4
valid_sources[0x5d]	345	1			T15	2		T14	1		T143	2
valid_sources[0x5e]	235	1			T6	1		T14	4		T143	1
valid_sources[0x5f]	341	1			T1	1		T48	1		T14	4
valid_sources[0x60]	279	1			T1	1		T2	4		T8	1
valid_sources[0x61]	238	1			T1	1		T47	1		T14	1
valid_sources[0x62]	208	1			T10	3		T48	1		T14	1
valid_sources[0x63]	277	1			T1	2		T2	2		T10	3
valid_sources[0x64]	302	1			T7	4		T48	1		T14	1
valid_sources[0x65]	230	1			T59	1		T121	1		T93	1
valid_sources[0x66]	384	1			T9	22		T47	1		T14	1
valid_sources[0x67]	268	1			T4	2		T14	2		T206	1
valid_sources[0x68]	506	1			T1	1		T14	1		T17	18
valid_sources[0x69]	242	1			T1	2		T2	2		T7	3
valid_sources[0x6a]	421	1			T1	1		T14	1		T38	7
valid_sources[0x6b]	231	1			T1	1		T59	2		T206	1
valid_sources[0x6c]	244	1			T47	1		T14	2		T143	1
valid_sources[0x6d]	352	1			T7	6		T14	6		T88	2
valid_sources[0x6e]	293	1			T47	1		T30	17		T59	1
valid_sources[0x6f]	472	1			T1	1		T5	3		T7	3
valid_sources[0x70]	289	1			T2	1		T7	2		T8	6
valid_sources[0x71]	275	1			T47	1		T205	2		T54	1
valid_sources[0x72]	256	1			T206	1		T205	1		T121	2
valid_sources[0x73]	219	1			T1	2		T10	5		T14	1
valid_sources[0x74]	404	1			T7	1		T10	1		T14	2
valid_sources[0x75]	308	1			T1	1		T10	1		T48	1
valid_sources[0x76]	218	1			T1	2		T7	2		T8	3
valid_sources[0x77]	340	1			T1	1		T10	1		T59	1
valid_sources[0x78]	369	1			T32	2		T205	1		T121	2
valid_sources[0x79]	374	1			T1	1		T48	1		T15	1
valid_sources[0x7a]	289	1			T1	1		T7	3		T14	1
valid_sources[0x7b]	440	1			T47	1		T14	2		T206	1
valid_sources[0x7c]	239	1			T37	12		T41	4		T121	1
valid_sources[0x7d]	380	1			T47	1		T14	1		T51	1
valid_sources[0x7e]	239	1			T1	1		T42	1		T59	2
valid_sources[0x7f]	344	1			T7	8		T14	2		T143	2
valid_sources[0x80]	236	1			T4	6		T10	2		T14	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

16743

1

T1

5

T2

6

T3

4

values[0x0]

all_enables

biggest_size

9225

1

T1

13

T2

3

T3

1

values[0x1]

all_enables

biggest_size

6759

1

T1

4

T2

2

T3

1