Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2835682	13219	0	0
intr_enable_rd_A	2835682	2035	0	0
reset_en_rd_A	2835682	895	0	0
reset_en_regwen_rd_A	2835682	746	0	0
wake_info_capture_dis_rd_A	2835682	780	0	0
wakeup_en_rd_A	2835682	1487	0	0
wakeup_en_regwen_rd_A	2835682	770	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2835682	13219	0	0
T25	9450	11	0	0
T26	2222	337	0	0
T27	2123	21	0	0
T60	2213	234	0	0
T61	15126	4	0	0
T63	2664	346	0	0
T74	2651	117	0	0
T80	1386	44	0	0
T81	4825	76	0	0
T82	4500	48	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2835682	2035	0	0
T9	4354	35	0	0
T10	2543	0	0	0
T14	2531	0	0	0
T15	1037	0	0	0
T16	5795	0	0	0
T18	4661	0	0	0
T41	0	119	0	0
T47	5015	0	0	0
T48	1502	0	0	0
T50	2164	0	0	0
T54	0	1	0	0
T59	0	63	0	0
T69	0	3	0	0
T91	0	84	0	0
T94	2891	0	0	0
T121	0	51	0	0
T122	0	3	0	0
T123	0	31	0	0
T124	0	95	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2835682	895	0	0
T27	2123	19	0	0
T62	15470	71	0	0
T81	4825	24	0	0
T82	4500	20	0	0
T114	2254	23	0	0
T117	3906	41	0	0
T125	2454	25	0	0
T126	14540	47	0	0
T127	2714	37	0	0
T128	1919	24	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2835682	746	0	0
T27	2123	22	0	0
T62	15470	40	0	0
T81	4825	10	0	0
T82	4500	8	0	0
T114	2254	12	0	0
T117	3906	28	0	0
T125	2454	17	0	0
T126	14540	57	0	0
T127	2714	21	0	0
T128	1919	9	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2835682	780	0	0
T27	2123	24	0	0
T62	15470	30	0	0
T81	4825	3	0	0
T82	4500	24	0	0
T114	2254	23	0	0
T117	3906	10	0	0
T125	2454	36	0	0
T126	14540	18	0	0
T127	2714	33	0	0
T128	1919	11	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2835682	1487	0	0
T27	2123	49	0	0
T62	15470	162	0	0
T81	4825	8	0	0
T82	4500	23	0	0
T114	2254	14	0	0
T117	3906	23	0	0
T125	2454	24	0	0
T126	14540	24	0	0
T127	2714	58	0	0
T128	1919	21	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2835682	770	0	0
T27	2123	9	0	0
T62	15470	45	0	0
T81	4825	10	0	0
T82	4500	16	0	0
T114	2254	28	0	0
T117	3906	31	0	0
T125	2454	43	0	0
T126	14540	13	0	0
T127	2714	10	0	0
T128	1919	16	0	0