Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	6745257	9526	0	0
StatusRise_A	6745257	13082	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6745257	9526	0	0
T1	7173	3	0	0
T2	3177	6	0	0
T3	3351	6	0	0
T4	25554	54	0	0
T5	9183	12	0	0
T6	4875	12	0	0
T7	14469	0	0	0
T8	3705	6	0	0
T9	13062	9	0	0
T10	7629	8	0	0
T47	0	6	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6745257	13082	0	0
T1	7173	6	0	0
T2	3177	8	0	0
T3	3351	9	0	0
T4	25554	60	0	0
T5	9183	15	0	0
T6	4875	15	0	0
T7	14469	3	0	0
T8	3705	9	0	0
T9	13062	12	0	0
T10	7629	11	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	2248419	3218	0	0
StatusRise_A	2248419	4415	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2248419	3218	0	0
T1	2391	1	0	0
T2	1059	2	0	0
T3	1117	2	0	0
T4	8518	18	0	0
T5	3061	4	0	0
T6	1625	4	0	0
T7	4823	0	0	0
T8	1235	2	0	0
T9	4354	3	0	0
T10	2543	3	0	0
T47	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2248419	4415	0	0
T1	2391	2	0	0
T2	1059	3	0	0
T3	1117	3	0	0
T4	8518	20	0	0
T5	3061	5	0	0
T6	1625	5	0	0
T7	4823	1	0	0
T8	1235	3	0	0
T9	4354	4	0	0
T10	2543	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	2248419	3218	0	0
StatusRise_A	2248419	4415	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2248419	3218	0	0
T1	2391	1	0	0
T2	1059	2	0	0
T3	1117	2	0	0
T4	8518	18	0	0
T5	3061	4	0	0
T6	1625	4	0	0
T7	4823	0	0	0
T8	1235	2	0	0
T9	4354	3	0	0
T10	2543	3	0	0
T47	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2248419	4415	0	0
T1	2391	2	0	0
T2	1059	3	0	0
T3	1117	3	0	0
T4	8518	20	0	0
T5	3061	5	0	0
T6	1625	5	0	0
T7	4823	1	0	0
T8	1235	3	0	0
T9	4354	4	0	0
T10	2543	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	2248419	3090	0	0
StatusRise_A	2248419	4252	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2248419	3090	0	0
T1	2391	1	0	0
T2	1059	2	0	0
T3	1117	2	0	0
T4	8518	18	0	0
T5	3061	4	0	0
T6	1625	4	0	0
T7	4823	0	0	0
T8	1235	2	0	0
T9	4354	3	0	0
T10	2543	2	0	0
T47	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2248419	4252	0	0
T1	2391	2	0	0
T2	1059	2	0	0
T3	1117	3	0	0
T4	8518	20	0	0
T5	3061	5	0	0
T6	1625	5	0	0
T7	4823	1	0	0
T8	1235	3	0	0
T9	4354	4	0	0
T10	2543	3	0	0