Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	2248754	6464	0	0
EscTimeoutStoppedByClReset_A	2248419	80767	0	0
EscTimeoutTriggersReset_A	309997	372	0	0
RomAllowActiveState_A	2248419	4030	0	0
RomAllowCheckGoodState_A	2248419	4081	0	0
RomBlockActiveState_A	2248419	24477	0	0
RomBlockCheckGoodState_A	2248419	16143	0	0
RomIntgChkDisFalse_A	2248419	2062245	0	0
RomIntgChkDisTrue_A	2248419	28150	0	0
RstreqChkEsctimeout_A	2248419	999	0	0
RstreqChkFsmterm_A	2248419	160	0	0
RstreqChkGlbesc_A	2248419	999	0	0
RstreqChkMainpd_A	2248419	48171	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2248754	6464	0	0
T11	15161	14	0	0
T12	2386	26	0	0
T19	1692	0	0	0
T21	22516	0	0	0
T29	2742	0	0	0
T30	1430	0	0	0
T36	0	50	0	0
T49	0	15	0	0
T52	3261	0	0	0
T53	2722	0	0	0
T59	2836	0	0	0
T67	1121	0	0	0
T129	0	217	0	0
T130	0	278	0	0
T131	0	57	0	0
T132	0	8	0	0
T133	0	146	0	0
T134	0	6	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2248419	80767	0	0
T1	2391	10	0	0
T2	1059	0	0	0
T3	1117	37	0	0
T4	8518	377	0	0
T5	3061	44	0	0
T6	1625	37	0	0
T7	4823	15	0	0
T8	1235	12	0	0
T9	4354	42	0	0
T10	2543	0	0	0
T47	0	27	0	0
T48	0	56	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309997	372	0	0
T11	2013	3	0	0
T12	198	2	0	0
T13	0	5	0	0
T19	578	0	0	0
T21	2286	0	0	0
T29	274	0	0	0
T30	437	0	0	0
T36	0	3	0	0
T49	0	4	0	0
T52	333	0	0	0
T53	264	0	0	0
T59	1547	0	0	0
T67	355	0	0	0
T129	0	3	0	0
T130	0	3	0	0
T131	0	3	0	0
T135	0	9	0	0
T136	0	10	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2248419	4030	0	0
T1	2391	2	0	0
T2	1059	3	0	0
T3	1117	3	0	0
T4	8518	13	0	0
T5	3061	5	0	0
T6	1625	5	0	0
T7	4823	1	0	0
T8	1235	3	0	0
T9	4354	4	0	0
T10	2543	4	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2248419	4081	0	0
T1	2391	2	0	0
T2	1059	3	0	0
T3	1117	3	0	0
T4	8518	14	0	0
T5	3061	5	0	0
T6	1625	5	0	0
T7	4823	1	0	0
T8	1235	3	0	0
T9	4354	4	0	0
T10	2543	4	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2248419	24477	0	0
T11	15160	0	0	0
T17	1149	0	0	0
T24	1346	0	0	0
T28	968	0	0	0
T31	1305	93	0	0
T32	0	566	0	0
T33	0	178	0	0
T42	3592	0	0	0
T51	2084	0	0	0
T53	2722	0	0	0
T72	0	687	0	0
T88	2063	0	0	0
T137	0	930	0	0
T138	0	58	0	0
T139	0	329	0	0
T140	0	237	0	0
T141	0	1141	0	0
T142	0	537	0	0
T143	3726	0	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2248419	16143	0	0
T11	15160	0	0	0
T17	1149	0	0	0
T24	1346	0	0	0
T28	968	0	0	0
T31	1305	94	0	0
T32	0	286	0	0
T33	0	52	0	0
T42	3592	0	0	0
T51	2084	0	0	0
T53	2722	0	0	0
T72	0	252	0	0
T88	2063	0	0	0
T137	0	1021	0	0
T138	0	1	0	0
T139	0	101	0	0
T140	0	127	0	0
T141	0	836	0	0
T142	0	341	0	0
T143	3726	0	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2248419	2062245	0	0
T1	2391	2295	0	0
T2	1059	993	0	0
T3	1117	1038	0	0
T4	8518	7546	0	0
T5	3061	2643	0	0
T6	1625	1198	0	0
T7	4823	4759	0	0
T8	1235	1171	0	0
T9	4354	4275	0	0
T10	2543	2449	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2248419	28150	0	0
T11	15160	0	0	0
T17	1149	0	0	0
T24	1346	0	0	0
T28	968	0	0	0
T31	1305	51	0	0
T32	0	1208	0	0
T33	0	21	0	0
T42	3592	0	0	0
T51	2084	0	0	0
T53	2722	0	0	0
T72	0	967	0	0
T88	2063	0	0	0
T137	0	802	0	0
T138	0	36	0	0
T139	0	83	0	0
T140	0	732	0	0
T141	0	281	0	0
T142	0	612	0	0
T143	3726	0	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2248419	999	0	0
T3	1117	1	0	0
T4	8518	8	0	0
T5	3061	0	0	0
T6	1625	0	0	0
T7	4823	0	0	0
T8	1235	0	0	0
T9	4354	0	0	0
T10	2543	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T16	0	7	0	0
T31	0	3	0	0
T42	0	1	0	0
T47	5015	0	0	0
T48	1502	0	0	0
T51	0	2	0	0
T52	0	5	0	0
T53	0	3	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2248419	160	0	0
T13	782	0	0	0
T19	1691	0	0	0
T20	2725	0	0	0
T21	22515	20	0	0
T22	0	40	0	0
T23	0	20	0	0
T34	0	40	0	0
T35	0	40	0	0
T36	15181	0	0	0
T37	2160	0	0	0
T38	7537	0	0	0
T39	1938	0	0	0
T40	2920	0	0	0
T41	6910	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2248419	999	0	0
T3	1117	1	0	0
T4	8518	8	0	0
T5	3061	0	0	0
T6	1625	0	0	0
T7	4823	0	0	0
T8	1235	0	0	0
T9	4354	0	0	0
T10	2543	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T16	0	7	0	0
T31	0	3	0	0
T42	0	1	0	0
T47	5015	0	0	0
T48	1502	0	0	0
T51	0	2	0	0
T52	0	5	0	0
T53	0	3	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2248419	48171	0	0
T3	1117	26	0	0
T4	8518	135	0	0
T5	3061	0	0	0
T6	1625	0	0	0
T7	4823	0	0	0
T8	1235	0	0	0
T9	4354	0	0	0
T10	2543	0	0	0
T16	0	215	0	0
T18	0	27	0	0
T19	0	22	0	0
T20	0	18	0	0
T28	0	11	0	0
T31	0	21	0	0
T38	0	215	0	0
T42	0	222	0	0
T47	5015	0	0	0
T48	1502	0	0	0