Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	40782	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

32153

1

T1

1

T2

1

T3

24

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36746	1			T1	1		T2	1		T3	10
values[0x0]	17891	1			T3	30		T5	14		T6	74
values[0x1]	18298	1			T3	28		T5	10		T6	62

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	32850	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

40085

1

T1

1

T2

1

T3

29

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	179	1			T65	4		T86	1		T212	1
valid_sources[0x01]	327	1			T65	1		T69	1		T213	1
valid_sources[0x02]	245	1			T6	1		T28	1		T65	2
valid_sources[0x03]	213	1			T65	1		T45	1		T69	1
valid_sources[0x04]	504	1			T6	2		T65	2		T152	2
valid_sources[0x05]	348	1			T214	1		T152	1		T88	3
valid_sources[0x06]	214	1			T6	2		T14	3		T65	1
valid_sources[0x07]	420	1			T6	1		T65	3		T214	2
valid_sources[0x08]	337	1			T6	1		T8	1		T42	3
valid_sources[0x09]	160	1			T6	2		T152	2		T215	2
valid_sources[0x0a]	289	1			T8	1		T14	1		T65	4
valid_sources[0x0b]	386	1			T5	4		T6	4		T28	1
valid_sources[0x0c]	198	1			T6	3		T65	1		T152	1
valid_sources[0x0d]	215	1			T6	1		T8	1		T152	1
valid_sources[0x0e]	255	1			T8	1		T28	1		T65	3
valid_sources[0x0f]	259	1			T6	6		T14	1		T65	1
valid_sources[0x10]	234	1			T8	4		T65	4		T25	1
valid_sources[0x11]	228	1			T14	4		T214	2		T47	1
valid_sources[0x12]	417	1			T6	2		T65	4		T42	1
valid_sources[0x13]	238	1			T6	1		T152	2		T69	1
valid_sources[0x14]	355	1			T6	1		T14	1		T65	2
valid_sources[0x15]	265	1			T5	5		T86	2		T67	6
valid_sources[0x16]	432	1			T6	1		T65	1		T214	1
valid_sources[0x17]	228	1			T6	1		T212	1		T127	1
valid_sources[0x18]	211	1			T6	2		T8	2		T65	1
valid_sources[0x19]	422	1			T14	2		T65	1		T45	2
valid_sources[0x1a]	550	1			T6	1		T214	1		T86	1
valid_sources[0x1b]	328	1			T6	2		T8	1		T29	1
valid_sources[0x1c]	349	1			T6	4		T8	1		T14	1
valid_sources[0x1d]	277	1			T6	1		T14	1		T65	1
valid_sources[0x1e]	281	1			T6	1		T8	5		T42	1
valid_sources[0x1f]	263	1			T14	1		T65	2		T53	2
valid_sources[0x20]	174	1			T6	1		T65	1		T152	3
valid_sources[0x21]	187	1			T6	1		T65	1		T86	1
valid_sources[0x22]	234	1			T6	1		T65	1		T214	1
valid_sources[0x23]	193	1			T6	1		T214	1		T128	2
valid_sources[0x24]	331	1			T65	1		T214	2		T152	2
valid_sources[0x25]	216	1			T6	4		T65	1		T86	2
valid_sources[0x26]	246	1			T6	2		T8	1		T65	1
valid_sources[0x27]	305	1			T6	2		T65	1		T67	3
valid_sources[0x28]	230	1			T6	2		T7	1		T8	5
valid_sources[0x29]	213	1			T6	3		T14	2		T45	2
valid_sources[0x2a]	359	1			T6	2		T66	1		T88	1
valid_sources[0x2b]	209	1			T65	1		T45	1		T67	2
valid_sources[0x2c]	269	1			T214	3		T152	2		T55	4
valid_sources[0x2d]	256	1			T65	2		T69	1		T212	1
valid_sources[0x2e]	285	1			T6	2		T14	4		T65	2
valid_sources[0x2f]	187	1			T6	2		T14	1		T47	3
valid_sources[0x30]	281	1			T14	2		T44	1		T69	1
valid_sources[0x31]	233	1			T2	1		T6	1		T14	1
valid_sources[0x32]	257	1			T6	3		T8	2		T152	1
valid_sources[0x33]	200	1			T6	2		T14	1		T65	1
valid_sources[0x34]	237	1			T6	4		T7	2		T8	2
valid_sources[0x35]	235	1			T6	1		T8	2		T65	2
valid_sources[0x36]	427	1			T6	1		T65	1		T214	2
valid_sources[0x37]	340	1			T6	1		T47	8		T152	1
valid_sources[0x38]	291	1			T6	2		T47	1		T152	1
valid_sources[0x39]	238	1			T6	1		T8	4		T25	1
valid_sources[0x3a]	172	1			T6	1		T8	1		T65	4
valid_sources[0x3b]	299	1			T6	2		T65	1		T55	2
valid_sources[0x3c]	305	1			T6	1		T65	1		T88	1
valid_sources[0x3d]	382	1			T6	1		T28	1		T14	1
valid_sources[0x3e]	212	1			T6	2		T7	1		T14	1
valid_sources[0x3f]	367	1			T6	2		T65	1		T53	16
valid_sources[0x40]	221	1			T6	2		T14	1		T42	1
valid_sources[0x41]	250	1			T6	4		T14	3		T65	1
valid_sources[0x42]	272	1			T6	1		T14	4		T212	2
valid_sources[0x43]	391	1			T8	2		T30	1		T42	1
valid_sources[0x44]	259	1			T97	2		T91	1		T27	5
valid_sources[0x45]	266	1			T6	1		T8	1		T14	2
valid_sources[0x46]	359	1			T65	1		T214	1		T55	3
valid_sources[0x47]	188	1			T6	2		T29	3		T212	1
valid_sources[0x48]	265	1			T14	3		T65	1		T152	1
valid_sources[0x49]	545	1			T6	1		T14	2		T65	4
valid_sources[0x4a]	321	1			T6	1		T42	1		T44	2
valid_sources[0x4b]	645	1			T28	1		T65	2		T86	2
valid_sources[0x4c]	477	1			T6	3		T14	3		T65	3
valid_sources[0x4d]	377	1			T6	1		T8	1		T65	1
valid_sources[0x4e]	344	1			T6	1		T14	2		T65	1
valid_sources[0x4f]	333	1			T6	2		T8	1		T29	3
valid_sources[0x50]	468	1			T65	3		T42	1		T44	1
valid_sources[0x51]	331	1			T6	3		T7	2		T8	2
valid_sources[0x52]	434	1			T8	2		T65	2		T42	2
valid_sources[0x53]	226	1			T6	1		T14	1		T65	1
valid_sources[0x54]	181	1			T6	1		T8	2		T65	2
valid_sources[0x55]	174	1			T65	1		T30	1		T86	1
valid_sources[0x56]	252	1			T6	2		T14	3		T42	1
valid_sources[0x57]	287	1			T5	4		T6	4		T14	2
valid_sources[0x58]	261	1			T6	2		T7	1		T86	1
valid_sources[0x59]	229	1			T6	2		T29	1		T45	4
valid_sources[0x5a]	183	1			T5	1		T6	2		T14	1
valid_sources[0x5b]	510	1			T6	1		T28	1		T42	2
valid_sources[0x5c]	297	1			T6	1		T8	4		T66	1
valid_sources[0x5d]	242	1			T6	3		T14	1		T44	1
valid_sources[0x5e]	387	1			T6	2		T65	1		T66	1
valid_sources[0x5f]	247	1			T6	1		T14	3		T86	1
valid_sources[0x60]	192	1			T6	2		T65	1		T45	2
valid_sources[0x61]	278	1			T6	3		T8	3		T65	1
valid_sources[0x62]	236	1			T14	3		T65	3		T42	1
valid_sources[0x63]	243	1			T6	4		T7	1		T214	4
valid_sources[0x64]	337	1			T8	1		T14	1		T65	1
valid_sources[0x65]	171	1			T6	4		T65	3		T86	1
valid_sources[0x66]	382	1			T6	1		T28	1		T86	1
valid_sources[0x67]	195	1			T6	3		T65	1		T44	2
valid_sources[0x68]	233	1			T6	1		T14	1		T65	1
valid_sources[0x69]	227	1			T7	1		T65	3		T152	1
valid_sources[0x6a]	340	1			T6	1		T28	2		T65	1
valid_sources[0x6b]	209	1			T6	5		T65	2		T66	1
valid_sources[0x6c]	391	1			T6	1		T7	2		T14	1
valid_sources[0x6d]	249	1			T8	1		T14	1		T65	2
valid_sources[0x6e]	395	1			T8	1		T29	1		T65	1
valid_sources[0x6f]	216	1			T6	1		T29	1		T86	3
valid_sources[0x70]	257	1			T65	2		T212	2		T97	2
valid_sources[0x71]	297	1			T6	2		T214	1		T55	3
valid_sources[0x72]	202	1			T6	1		T8	1		T65	1
valid_sources[0x73]	184	1			T6	1		T8	1		T14	2
valid_sources[0x74]	335	1			T53	5		T55	1		T97	1
valid_sources[0x75]	332	1			T6	3		T65	6		T214	1
valid_sources[0x76]	350	1			T6	3		T14	2		T44	1
valid_sources[0x77]	258	1			T6	1		T8	2		T65	2
valid_sources[0x78]	253	1			T6	1		T8	3		T65	1
valid_sources[0x79]	344	1			T6	2		T65	1		T42	1
valid_sources[0x7a]	206	1			T6	2		T14	1		T42	1
valid_sources[0x7b]	301	1			T6	2		T131	1		T55	8
valid_sources[0x7c]	232	1			T6	2		T44	1		T45	1
valid_sources[0x7d]	235	1			T8	1		T28	1		T30	1
valid_sources[0x7e]	301	1			T6	2		T29	1		T65	4
valid_sources[0x7f]	266	1			T14	1		T65	2		T30	2
valid_sources[0x80]	271	1			T6	1		T8	3		T152	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

15960

1

T1

1

T2

1

T3

7

values[0x0]

all_enables

biggest_size

9241

1

T3

11

T5

4

T6

34

values[0x1]

all_enables

biggest_size

6952

1

T3

6

T5

4

T6

6