Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T48

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	2250764	157	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	2250764	15023	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	2250764	143534	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	2250764	15023	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	2250764	157	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	2250764	15023	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	2250764	143534	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	2250764	15023	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2250764	157	0	0
T7	1619	1	0	0
T8	2870	0	0	0
T9	5417	0	0	0
T10	3283	0	0	0
T11	819	0	0	0
T14	3108	0	0	0
T20	1234	0	0	0
T28	2447	0	0	0
T29	1817	2	0	0
T30	0	3	0	0
T46	1929	0	0	0
T48	0	2	0	0
T53	0	1	0	0
T54	0	1	0	0
T67	0	1	0	0
T88	0	3	0	0
T89	0	3	0	0
T90	0	2	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2250764	15023	0	0
T7	1619	13	0	0
T8	2870	0	0	0
T9	5417	0	0	0
T10	3283	0	0	0
T11	819	0	0	0
T14	3108	0	0	0
T20	1234	0	0	0
T28	2447	0	0	0
T29	1817	202	0	0
T30	0	835	0	0
T46	1929	0	0	0
T48	0	142	0	0
T53	0	13	0	0
T54	0	12	0	0
T67	0	12	0	0
T88	0	369	0	0
T89	0	262	0	0
T90	0	180	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2250764	143534	0	0
T5	1014	665	0	0
T6	2247	579	0	0
T7	1619	1081	0	0
T8	2870	0	0	0
T9	5417	0	0	0
T10	3283	0	0	0
T14	3108	1720	0	0
T20	1234	0	0	0
T28	2447	0	0	0
T29	0	225	0	0
T30	0	1243	0	0
T46	1929	0	0	0
T48	0	145	0	0
T53	0	878	0	0
T54	0	1106	0	0
T67	0	1034	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2250764	15023	0	0
T7	1619	13	0	0
T8	2870	0	0	0
T9	5417	0	0	0
T10	3283	0	0	0
T11	819	0	0	0
T14	3108	0	0	0
T20	1234	0	0	0
T28	2447	0	0	0
T29	1817	202	0	0
T30	0	835	0	0
T46	1929	0	0	0
T48	0	142	0	0
T53	0	13	0	0
T54	0	12	0	0
T67	0	12	0	0
T88	0	369	0	0
T89	0	262	0	0
T90	0	180	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2250764	157	0	0
T7	1619	1	0	0
T8	2870	0	0	0
T9	5417	0	0	0
T10	3283	0	0	0
T11	819	0	0	0
T14	3108	0	0	0
T20	1234	0	0	0
T28	2447	0	0	0
T29	1817	2	0	0
T30	0	3	0	0
T46	1929	0	0	0
T48	0	2	0	0
T53	0	1	0	0
T54	0	1	0	0
T67	0	1	0	0
T88	0	3	0	0
T89	0	3	0	0
T90	0	2	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2250764	15023	0	0
T7	1619	13	0	0
T8	2870	0	0	0
T9	5417	0	0	0
T10	3283	0	0	0
T11	819	0	0	0
T14	3108	0	0	0
T20	1234	0	0	0
T28	2447	0	0	0
T29	1817	202	0	0
T30	0	835	0	0
T46	1929	0	0	0
T48	0	142	0	0
T53	0	13	0	0
T54	0	12	0	0
T67	0	12	0	0
T88	0	369	0	0
T89	0	262	0	0
T90	0	180	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2250764	143534	0	0
T5	1014	665	0	0
T6	2247	579	0	0
T7	1619	1081	0	0
T8	2870	0	0	0
T9	5417	0	0	0
T10	3283	0	0	0
T14	3108	1720	0	0
T20	1234	0	0	0
T28	2447	0	0	0
T29	0	225	0	0
T30	0	1243	0	0
T46	1929	0	0	0
T48	0	145	0	0
T53	0	878	0	0
T54	0	1106	0	0
T67	0	1034	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2250764	15023	0	0
T7	1619	13	0	0
T8	2870	0	0	0
T9	5417	0	0	0
T10	3283	0	0	0
T11	819	0	0	0
T14	3108	0	0	0
T20	1234	0	0	0
T28	2447	0	0	0
T29	1817	202	0	0
T30	0	835	0	0
T46	1929	0	0	0
T48	0	142	0	0
T53	0	13	0	0
T54	0	12	0	0
T67	0	12	0	0
T88	0	369	0	0
T89	0	262	0	0
T90	0	180	0	0