Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2859950	14372	0	0
intr_enable_rd_A	2859950	3285	0	0
reset_en_rd_A	2859950	1873	0	0
reset_en_regwen_rd_A	2859950	1635	0	0
wake_info_capture_dis_rd_A	2859950	1846	0	0
wakeup_en_rd_A	2859950	2539	0	0
wakeup_en_regwen_rd_A	2859950	1768	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2859950	14372	0	0
T21	5732	5	0	0
T22	7606	5	0	0
T23	1838	164	0	0
T57	4295	41	0	0
T58	1861	162	0	0
T59	9950	9	0	0
T61	6888	6	0	0
T62	10934	565	0	0
T70	14590	9	0	0
T71	1986	38	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2859950	3285	0	0
T5	1014	7	0	0
T6	2247	0	0	0
T7	1619	3	0	0
T8	2870	0	0	0
T9	5417	0	0	0
T10	3283	0	0	0
T14	3108	40	0	0
T20	1234	0	0	0
T28	2447	0	0	0
T46	1929	0	0	0
T47	0	64	0	0
T54	0	9	0	0
T65	0	67	0	0
T67	0	1	0	0
T91	0	5	0	0
T98	0	34	0	0
T128	0	33	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2859950	1873	0	0
T21	5732	36	0	0
T57	4295	14	0	0
T61	6888	9	0	0
T62	10934	16	0	0
T81	9443	24	0	0
T83	15435	49	0	0
T99	11031	117	0	0
T108	1333	8	0	0
T109	2460	48	0	0
T123	2738	9	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2859950	1635	0	0
T21	5732	18	0	0
T57	4295	11	0	0
T61	6888	17	0	0
T62	10934	28	0	0
T83	15435	54	0	0
T99	11031	62	0	0
T108	1333	9	0	0
T109	2460	45	0	0
T123	2738	21	0	0
T130	2279	1	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2859950	1846	0	0
T21	5732	16	0	0
T57	4295	10	0	0
T61	6888	24	0	0
T62	10934	24	0	0
T83	15435	51	0	0
T99	11031	77	0	0
T108	1333	14	0	0
T109	2460	57	0	0
T123	2738	25	0	0
T130	2279	5	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2859950	2539	0	0
T21	5732	32	0	0
T57	4295	27	0	0
T61	6888	96	0	0
T62	10934	43	0	0
T83	15435	150	0	0
T99	11031	182	0	0
T108	1333	1	0	0
T109	2460	48	0	0
T123	2738	12	0	0
T130	2279	2	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2859950	1768	0	0
T21	5732	30	0	0
T57	4295	12	0	0
T61	6888	17	0	0
T62	10934	33	0	0
T83	15435	44	0	0
T99	11031	95	0	0
T108	1333	10	0	0
T109	2460	61	0	0
T123	2738	7	0	0
T130	2279	1	0	0