Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	6752292	9506	0	0
StatusRise_A	6752292	13004	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6752292	9506	0	0
T3	17316	54	0	0
T4	4317	0	0	0
T5	3042	9	0	0
T6	6741	49	0	0
T7	4857	6	0	0
T8	8610	54	0	0
T9	16251	18	0	0
T10	9849	18	0	0
T14	0	31	0	0
T20	0	15	0	0
T28	7341	15	0	0
T46	5787	0	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6752292	13004	0	0
T1	10518	15	0	0
T2	5475	15	0	0
T3	17316	60	0	0
T4	4317	6	0	0
T5	3042	12	0	0
T6	6741	52	0	0
T7	4857	9	0	0
T8	8610	60	0	0
T9	16251	24	0	0
T10	9849	24	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	2250764	3208	0	0
StatusRise_A	2250764	4388	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2250764	3208	0	0
T3	5772	18	0	0
T4	1439	0	0	0
T5	1014	3	0	0
T6	2247	17	0	0
T7	1619	2	0	0
T8	2870	18	0	0
T9	5417	6	0	0
T10	3283	6	0	0
T14	0	10	0	0
T20	0	5	0	0
T28	2447	5	0	0
T46	1929	0	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2250764	4388	0	0
T1	3506	5	0	0
T2	1825	5	0	0
T3	5772	20	0	0
T4	1439	2	0	0
T5	1014	4	0	0
T6	2247	18	0	0
T7	1619	3	0	0
T8	2870	20	0	0
T9	5417	8	0	0
T10	3283	8	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	2250764	3208	0	0
StatusRise_A	2250764	4388	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2250764	3208	0	0
T3	5772	18	0	0
T4	1439	0	0	0
T5	1014	3	0	0
T6	2247	17	0	0
T7	1619	2	0	0
T8	2870	18	0	0
T9	5417	6	0	0
T10	3283	6	0	0
T14	0	10	0	0
T20	0	5	0	0
T28	2447	5	0	0
T46	1929	0	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2250764	4388	0	0
T1	3506	5	0	0
T2	1825	5	0	0
T3	5772	20	0	0
T4	1439	2	0	0
T5	1014	4	0	0
T6	2247	18	0	0
T7	1619	3	0	0
T8	2870	20	0	0
T9	5417	8	0	0
T10	3283	8	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	2250764	3090	0	0
StatusRise_A	2250764	4228	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2250764	3090	0	0
T3	5772	18	0	0
T4	1439	0	0	0
T5	1014	3	0	0
T6	2247	15	0	0
T7	1619	2	0	0
T8	2870	18	0	0
T9	5417	6	0	0
T10	3283	6	0	0
T14	0	11	0	0
T20	0	5	0	0
T28	2447	5	0	0
T46	1929	0	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2250764	4228	0	0
T1	3506	5	0	0
T2	1825	5	0	0
T3	5772	20	0	0
T4	1439	2	0	0
T5	1014	4	0	0
T6	2247	16	0	0
T7	1619	3	0	0
T8	2870	20	0	0
T9	5417	8	0	0
T10	3283	8	0	0