Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	2251131	5864	0	0
EscTimeoutStoppedByClReset_A	2250764	79989	0	0
EscTimeoutTriggersReset_A	309551	319	0	0
RomAllowActiveState_A	2250764	4018	0	0
RomAllowCheckGoodState_A	2250764	4068	0	0
RomBlockActiveState_A	2250764	36619	0	0
RomBlockCheckGoodState_A	2250764	26417	0	0
RomIntgChkDisFalse_A	2250764	2065304	0	0
RomIntgChkDisTrue_A	2250764	31379	0	0
RstreqChkEsctimeout_A	2250764	960	0	0
RstreqChkFsmterm_A	2250764	140	0	0
RstreqChkGlbesc_A	2250764	960	0	0
RstreqChkMainpd_A	2250764	59455	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2251131	5864	0	0
T11	820	4	0	0
T12	15033	83	0	0
T13	14932	56	0	0
T24	1678	0	0	0
T29	1817	0	0	0
T30	3506	0	0	0
T42	2002	0	0	0
T43	3176	0	0	0
T44	4381	0	0	0
T65	6626	0	0	0
T131	0	4	0	0
T132	0	36	0	0
T133	0	130	0	0
T134	0	157	0	0
T135	0	46	0	0
T136	0	21	0	0
T137	0	230	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2250764	79989	0	0
T1	3506	41	0	0
T2	1825	35	0	0
T3	5772	503	0	0
T4	1439	2	0	0
T5	1014	0	0	0
T6	2247	0	0	0
T7	1619	13	0	0
T8	2870	369	0	0
T9	5417	139	0	0
T10	3283	219	0	0
T28	0	99	0	0
T46	0	42	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309551	319	0	0
T11	272	3	0	0
T12	588	3	0	0
T13	530	2	0	0
T24	303	0	0	0
T29	351	0	0	0
T30	327	0	0	0
T42	652	0	0	0
T43	1063	0	0	0
T44	480	0	0	0
T65	492	0	0	0
T131	0	9	0	0
T132	0	3	0	0
T133	0	2	0	0
T134	0	2	0	0
T135	0	3	0	0
T138	0	3	0	0
T139	0	4	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2250764	4018	0	0
T1	3506	5	0	0
T2	1825	5	0	0
T3	5772	20	0	0
T4	1439	2	0	0
T5	1014	4	0	0
T6	2247	18	0	0
T7	1619	3	0	0
T8	2870	13	0	0
T9	5417	8	0	0
T10	3283	8	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2250764	4068	0	0
T1	3506	5	0	0
T2	1825	5	0	0
T3	5772	20	0	0
T4	1439	2	0	0
T5	1014	4	0	0
T6	2247	18	0	0
T7	1619	3	0	0
T8	2870	14	0	0
T9	5417	8	0	0
T10	3283	8	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2250764	36619	0	0
T9	5417	1177	0	0
T10	3283	0	0	0
T11	819	0	0	0
T14	3108	0	0	0
T20	1234	93	0	0
T28	2447	181	0	0
T29	1817	0	0	0
T30	3505	0	0	0
T46	1929	0	0	0
T56	0	612	0	0
T65	6626	0	0	0
T140	0	1461	0	0
T141	0	299	0	0
T142	0	1450	0	0
T143	0	563	0	0
T144	0	1503	0	0
T145	0	591	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2250764	26417	0	0
T9	5417	836	0	0
T10	3283	0	0	0
T11	819	0	0	0
T14	3108	0	0	0
T20	1234	0	0	0
T28	2447	190	0	0
T29	1817	0	0	0
T30	3505	0	0	0
T46	1929	0	0	0
T56	0	316	0	0
T65	6626	0	0	0
T140	0	1055	0	0
T141	0	96	0	0
T142	0	722	0	0
T143	0	525	0	0
T144	0	1072	0	0
T145	0	1050	0	0
T146	0	837	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2250764	2065304	0	0
T1	3506	3140	0	0
T2	1825	1436	0	0
T3	5772	5619	0	0
T4	1439	1286	0	0
T5	1014	945	0	0
T6	2247	2163	0	0
T7	1619	1530	0	0
T8	2870	1926	0	0
T9	5417	4777	0	0
T10	3283	3146	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2250764	31379	0	0
T9	5417	454	0	0
T10	3283	0	0	0
T11	819	0	0	0
T14	3108	0	0	0
T20	1234	734	0	0
T28	2447	61	0	0
T29	1817	0	0	0
T30	3505	0	0	0
T46	1929	0	0	0
T56	0	138	0	0
T65	6626	0	0	0
T140	0	455	0	0
T141	0	990	0	0
T142	0	326	0	0
T143	0	359	0	0
T144	0	87	0	0
T145	0	563	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2250764	960	0	0
T2	1825	4	0	0
T3	5772	8	0	0
T4	1439	0	0	0
T5	1014	0	0	0
T6	2247	0	0	0
T7	1619	0	0	0
T8	2870	7	0	0
T9	5417	2	0	0
T10	3283	1	0	0
T11	0	1	0	0
T12	0	1	0	0
T20	0	2	0	0
T28	0	4	0	0
T46	1929	3	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2250764	140	0	0
T17	14710	20	0	0
T18	0	20	0	0
T19	0	20	0	0
T31	0	40	0	0
T32	0	40	0	0
T33	3293	0	0	0
T34	1058	0	0	0
T35	575	0	0	0
T36	15899	0	0	0
T37	582	0	0	0
T38	3910	0	0	0
T39	5055	0	0	0
T40	800	0	0	0
T41	15206	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2250764	960	0	0
T2	1825	4	0	0
T3	5772	8	0	0
T4	1439	0	0	0
T5	1014	0	0	0
T6	2247	0	0	0
T7	1619	0	0	0
T8	2870	7	0	0
T9	5417	2	0	0
T10	3283	1	0	0
T11	0	1	0	0
T12	0	1	0	0
T20	0	2	0	0
T28	0	4	0	0
T46	1929	3	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2250764	59455	0	0
T1	3506	22	0	0
T2	1825	0	0	0
T3	5772	494	0	0
T4	1439	5	0	0
T5	1014	0	0	0
T6	2247	0	0	0
T7	1619	0	0	0
T8	2870	147	0	0
T9	5417	109	0	0
T10	3283	222	0	0
T20	0	31	0	0
T28	0	44	0	0
T42	0	135	0	0
T43	0	139	0	0