Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	38457	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

30892

1

T1

1

T2

14

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	34070	1			T1	1		T2	3		T3	1
values[0x0]	17318	1			T2	40		T4	1		T5	50
values[0x1]	17961	1			T2	31		T5	54		T7	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	30893	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

38456

1

T1

1

T2

20

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	329	1			T31	1		T220	2		T125	1
valid_sources[0x01]	211	1			T2	1		T23	1		T38	1
valid_sources[0x02]	258	1			T5	1		T41	3		T42	6
valid_sources[0x03]	247	1			T40	1		T41	1		T28	1
valid_sources[0x04]	340	1			T5	2		T23	1		T40	2
valid_sources[0x05]	197	1			T5	2		T40	1		T38	2
valid_sources[0x06]	175	1			T35	8		T95	1		T220	1
valid_sources[0x07]	291	1			T2	1		T41	1		T43	2
valid_sources[0x08]	380	1			T42	1		T130	1		T221	1
valid_sources[0x09]	238	1			T2	1		T5	1		T95	7
valid_sources[0x0a]	226	1			T95	3		T28	1		T130	3
valid_sources[0x0b]	256	1			T5	1		T40	1		T27	1
valid_sources[0x0c]	264	1			T5	1		T93	1		T222	1
valid_sources[0x0d]	355	1			T40	2		T38	1		T42	2
valid_sources[0x0e]	228	1			T41	1		T17	1		T220	1
valid_sources[0x0f]	306	1			T223	4		T220	1		T224	1
valid_sources[0x10]	212	1			T5	2		T23	1		T81	1
valid_sources[0x11]	218	1			T5	2		T29	1		T223	2
valid_sources[0x12]	454	1			T25	1		T225	2		T226	83
valid_sources[0x13]	335	1			T2	2		T9	1		T40	2
valid_sources[0x14]	214	1			T23	1		T38	5		T27	1
valid_sources[0x15]	214	1			T2	1		T38	1		T223	2
valid_sources[0x16]	216	1			T5	1		T35	21		T30	1
valid_sources[0x17]	603	1			T38	5		T181	1		T224	4
valid_sources[0x18]	190	1			T5	1		T181	1		T227	1
valid_sources[0x19]	217	1			T130	1		T31	4		T223	2
valid_sources[0x1a]	164	1			T2	1		T54	4		T224	5
valid_sources[0x1b]	219	1			T5	2		T41	1		T28	2
valid_sources[0x1c]	584	1			T2	1		T38	5		T30	1
valid_sources[0x1d]	252	1			T40	1		T31	1		T220	1
valid_sources[0x1e]	213	1			T5	1		T95	1		T28	1
valid_sources[0x1f]	354	1			T5	1		T29	2		T95	1
valid_sources[0x20]	256	1			T2	1		T5	1		T133	2
valid_sources[0x21]	209	1			T38	1		T27	2		T220	1
valid_sources[0x22]	192	1			T40	2		T30	1		T140	1
valid_sources[0x23]	213	1			T2	1		T5	1		T40	1
valid_sources[0x24]	191	1			T5	1		T133	1		T83	2
valid_sources[0x25]	232	1			T95	2		T224	2		T228	3
valid_sources[0x26]	196	1			T12	1		T220	1		T224	2
valid_sources[0x27]	257	1			T133	1		T27	1		T220	1
valid_sources[0x28]	210	1			T2	1		T5	2		T41	1
valid_sources[0x29]	398	1			T5	1		T14	1		T133	1
valid_sources[0x2a]	193	1			T41	1		T29	2		T133	1
valid_sources[0x2b]	224	1			T43	12		T27	6		T224	1
valid_sources[0x2c]	253	1			T2	2		T5	1		T38	1
valid_sources[0x2d]	244	1			T40	2		T95	6		T124	1
valid_sources[0x2e]	198	1			T3	1		T5	2		T130	1
valid_sources[0x2f]	292	1			T2	2		T5	1		T30	1
valid_sources[0x30]	223	1			T141	1		T133	1		T223	2
valid_sources[0x31]	255	1			T5	1		T52	5		T83	2
valid_sources[0x32]	177	1			T38	1		T42	4		T27	1
valid_sources[0x33]	324	1			T2	1		T5	1		T40	1
valid_sources[0x34]	156	1			T2	1		T5	2		T41	2
valid_sources[0x35]	249	1			T5	3		T41	1		T38	1
valid_sources[0x36]	193	1			T5	2		T223	6		T220	2
valid_sources[0x37]	352	1			T5	2		T40	2		T52	2
valid_sources[0x38]	204	1			T2	1		T5	1		T40	1
valid_sources[0x39]	302	1			T40	1		T42	6		T27	2
valid_sources[0x3a]	407	1			T5	1		T41	1		T95	2
valid_sources[0x3b]	205	1			T23	2		T11	2		T95	4
valid_sources[0x3c]	438	1			T2	1		T40	1		T38	4
valid_sources[0x3d]	375	1			T5	2		T38	1		T130	1
valid_sources[0x3e]	255	1			T5	1		T130	1		T133	1
valid_sources[0x3f]	295	1			T2	1		T5	1		T52	2
valid_sources[0x40]	421	1			T27	3		T222	1		T126	4
valid_sources[0x41]	251	1			T53	32		T27	2		T220	2
valid_sources[0x42]	199	1			T5	2		T29	2		T124	2
valid_sources[0x43]	354	1			T5	1		T26	72		T27	5
valid_sources[0x44]	373	1			T5	2		T29	4		T38	1
valid_sources[0x45]	219	1			T2	1		T5	1		T54	12
valid_sources[0x46]	144	1			T2	1		T5	1		T23	1
valid_sources[0x47]	300	1			T5	1		T12	2		T54	6
valid_sources[0x48]	729	1			T40	1		T11	1		T27	3
valid_sources[0x49]	349	1			T41	2		T38	2		T220	1
valid_sources[0x4a]	314	1			T5	2		T220	2		T224	1
valid_sources[0x4b]	242	1			T2	1		T5	1		T41	1
valid_sources[0x4c]	182	1			T11	13		T38	1		T95	3
valid_sources[0x4d]	223	1			T5	1		T42	2		T124	1
valid_sources[0x4e]	312	1			T2	2		T5	1		T38	2
valid_sources[0x4f]	334	1			T5	1		T42	7		T13	4
valid_sources[0x50]	276	1			T40	3		T38	7		T95	7
valid_sources[0x51]	396	1			T42	5		T223	7		T224	2
valid_sources[0x52]	247	1			T2	2		T5	3		T42	4
valid_sources[0x53]	303	1			T5	1		T40	1		T95	1
valid_sources[0x54]	159	1			T2	1		T40	1		T11	1
valid_sources[0x55]	187	1			T40	1		T42	4		T43	3
valid_sources[0x56]	366	1			T2	2		T5	1		T95	1
valid_sources[0x57]	289	1			T5	1		T42	2		T220	1
valid_sources[0x58]	242	1			T2	1		T41	2		T38	2
valid_sources[0x59]	269	1			T5	1		T133	3		T223	2
valid_sources[0x5a]	247	1			T5	1		T52	1		T27	1
valid_sources[0x5b]	243	1			T2	1		T10	1		T38	5
valid_sources[0x5c]	548	1			T5	1		T130	12		T133	1
valid_sources[0x5d]	197	1			T40	1		T95	2		T27	2
valid_sources[0x5e]	402	1			T23	1		T40	3		T42	2
valid_sources[0x5f]	211	1			T5	2		T150	1		T12	10
valid_sources[0x60]	202	1			T5	3		T7	10		T95	4
valid_sources[0x61]	212	1			T5	1		T14	13		T40	1
valid_sources[0x62]	275	1			T2	1		T41	3		T17	1
valid_sources[0x63]	252	1			T5	1		T23	1		T40	2
valid_sources[0x64]	173	1			T2	1		T5	1		T42	2
valid_sources[0x65]	207	1			T5	3		T40	4		T30	1
valid_sources[0x66]	283	1			T5	2		T23	2		T40	1
valid_sources[0x67]	196	1			T2	1		T29	2		T30	1
valid_sources[0x68]	357	1			T41	2		T30	1		T130	3
valid_sources[0x69]	264	1			T17	2		T29	1		T38	1
valid_sources[0x6a]	317	1			T43	12		T13	1		T27	1
valid_sources[0x6b]	417	1			T40	1		T38	1		T31	2
valid_sources[0x6c]	453	1			T2	1		T229	44		T224	1
valid_sources[0x6d]	221	1			T5	1		T27	3		T83	2
valid_sources[0x6e]	292	1			T5	2		T133	1		T13	2
valid_sources[0x6f]	181	1			T220	1		T229	1		T224	2
valid_sources[0x70]	207	1			T5	1		T30	1		T95	2
valid_sources[0x71]	281	1			T5	1		T130	1		T223	2
valid_sources[0x72]	411	1			T2	1		T40	2		T32	15
valid_sources[0x73]	193	1			T27	2		T220	1		T224	1
valid_sources[0x74]	313	1			T2	1		T5	2		T95	1
valid_sources[0x75]	235	1			T28	1		T13	4		T223	4
valid_sources[0x76]	264	1			T5	3		T7	6		T12	2
valid_sources[0x77]	213	1			T2	1		T5	1		T133	2
valid_sources[0x78]	156	1			T5	1		T95	2		T133	3
valid_sources[0x79]	192	1			T5	2		T23	1		T42	1
valid_sources[0x7a]	271	1			T5	2		T23	1		T42	4
valid_sources[0x7b]	308	1			T5	1		T11	1		T29	1
valid_sources[0x7c]	215	1			T45	1		T223	1		T126	1
valid_sources[0x7d]	241	1			T5	1		T95	1		T28	3
valid_sources[0x7e]	419	1			T5	1		T38	2		T95	2
valid_sources[0x7f]	281	1			T5	1		T40	1		T32	1
valid_sources[0x80]	275	1			T2	2		T5	3		T40	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

14809

1

T1

1

T2

1

T3

1

values[0x0]

all_enables

biggest_size

9069

1

T2

9

T4

1

T5

16

values[0x1]

all_enables

biggest_size

7014

1

T2

4

T5

12

T23

2