SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 4 | 1 | T166 | 1 | T167 | 1 | T178 | 1 | ||||
others[1] | 6 | 1 | T149 | 1 | T145 | 1 | T159 | 1 | ||||
others[2] | 14 | 1 | T143 | 1 | T144 | 1 | T146 | 2 | ||||
others[3] | 19 | 1 | T7 | 1 | T23 | 1 | T28 | 1 | ||||
false | 120 | 1 | T7 | 2 | T23 | 2 | T28 | 2 | ||||
true | 2637 | 1 | T1 | 3 | T2 | 1 | T3 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 13 | 1 | T23 | 1 | T166 | 1 | T167 | 1 | ||||
others[1] | 13 | 1 | T142 | 1 | T149 | 1 | T145 | 1 | ||||
others[2] | 10 | 1 | T158 | 1 | T179 | 1 | T180 | 1 | ||||
others[3] | 16 | 1 | T7 | 1 | T143 | 2 | T144 | 1 | ||||
false | 143 | 1 | T7 | 3 | T23 | 3 | T28 | 3 | ||||
true | 2722 | 1 | T1 | 3 | T2 | 1 | T3 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 348 | 1 | T2 | 3 | T23 | 1 | T68 | 8 | ||||
others[1] | 327 | 1 | T2 | 1 | T7 | 1 | T68 | 4 | ||||
others[2] | 330 | 1 | T2 | 2 | T7 | 1 | T68 | 3 | ||||
others[3] | 570 | 1 | T2 | 3 | T68 | 12 | T26 | 1 | ||||
false | 3662 | 1 | T1 | 3 | T2 | 14 | T3 | 2 | ||||
true | 729 | 1 | T2 | 4 | T7 | 3 | T23 | 2 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |