Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T11,T29
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T32,T30

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	2222327	159	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	2222327	14700	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	2222327	156654	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	2222327	14700	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	2222327	159	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	2222327	14700	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	2222327	156654	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	2222327	14700	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2222327	159	0	0
T11	1020	1	0	0
T12	1602	0	0	0
T29	2268	3	0	0
T30	1686	2	0	0
T31	0	3	0	0
T32	1662	2	0	0
T36	1918	0	0	0
T37	15041	0	0	0
T38	4770	0	0	0
T39	15302	0	0	0
T52	0	1	0	0
T53	0	1	0	0
T82	0	1	0	0
T83	0	3	0	0
T84	0	1	0	0
T85	14895	0	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2222327	14700	0	0
T11	1020	13	0	0
T12	1602	0	0	0
T29	2268	330	0	0
T30	1686	173	0	0
T31	0	366	0	0
T32	1662	161	0	0
T36	1918	0	0	0
T37	15041	0	0	0
T38	4770	0	0	0
T39	15302	0	0	0
T52	0	12	0	0
T53	0	14	0	0
T82	0	10	0	0
T83	0	390	0	0
T84	0	88	0	0
T85	14895	0	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2222327	156654	0	0
T5	3567	1807	0	0
T6	14929	0	0	0
T7	4803	0	0	0
T8	2329	0	0	0
T9	1498	0	0	0
T10	1774	0	0	0
T11	0	887	0	0
T12	0	144	0	0
T13	0	921	0	0
T15	3518	0	0	0
T16	1185	0	0	0
T23	1408	0	0	0
T29	0	1144	0	0
T30	0	814	0	0
T32	0	119	0	0
T52	0	1030	0	0
T53	0	761	0	0
T82	0	832	0	0
T86	3734	0	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2222327	14700	0	0
T11	1020	13	0	0
T12	1602	0	0	0
T29	2268	330	0	0
T30	1686	173	0	0
T31	0	366	0	0
T32	1662	161	0	0
T36	1918	0	0	0
T37	15041	0	0	0
T38	4770	0	0	0
T39	15302	0	0	0
T52	0	12	0	0
T53	0	14	0	0
T82	0	10	0	0
T83	0	390	0	0
T84	0	88	0	0
T85	14895	0	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2222327	159	0	0
T11	1020	1	0	0
T12	1602	0	0	0
T29	2268	3	0	0
T30	1686	2	0	0
T31	0	3	0	0
T32	1662	2	0	0
T36	1918	0	0	0
T37	15041	0	0	0
T38	4770	0	0	0
T39	15302	0	0	0
T52	0	1	0	0
T53	0	1	0	0
T82	0	1	0	0
T83	0	3	0	0
T84	0	1	0	0
T85	14895	0	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2222327	14700	0	0
T11	1020	13	0	0
T12	1602	0	0	0
T29	2268	330	0	0
T30	1686	173	0	0
T31	0	366	0	0
T32	1662	161	0	0
T36	1918	0	0	0
T37	15041	0	0	0
T38	4770	0	0	0
T39	15302	0	0	0
T52	0	12	0	0
T53	0	14	0	0
T82	0	10	0	0
T83	0	390	0	0
T84	0	88	0	0
T85	14895	0	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2222327	156654	0	0
T5	3567	1807	0	0
T6	14929	0	0	0
T7	4803	0	0	0
T8	2329	0	0	0
T9	1498	0	0	0
T10	1774	0	0	0
T11	0	887	0	0
T12	0	144	0	0
T13	0	921	0	0
T15	3518	0	0	0
T16	1185	0	0	0
T23	1408	0	0	0
T29	0	1144	0	0
T30	0	814	0	0
T32	0	119	0	0
T52	0	1030	0	0
T53	0	761	0	0
T82	0	832	0	0
T86	3734	0	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2222327	14700	0	0
T11	1020	13	0	0
T12	1602	0	0	0
T29	2268	330	0	0
T30	1686	173	0	0
T31	0	366	0	0
T32	1662	161	0	0
T36	1918	0	0	0
T37	15041	0	0	0
T38	4770	0	0	0
T39	15302	0	0	0
T52	0	12	0	0
T53	0	14	0	0
T82	0	10	0	0
T83	0	390	0	0
T84	0	88	0	0
T85	14895	0	0	0