Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2869400	15569	0	0
intr_enable_rd_A	2869400	2708	0	0
reset_en_rd_A	2869400	1666	0	0
reset_en_regwen_rd_A	2869400	1502	0	0
wake_info_capture_dis_rd_A	2869400	1399	0	0
wakeup_en_rd_A	2869400	1932	0	0
wakeup_en_regwen_rd_A	2869400	1450	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2869400	15569	0	0
T20	9635	9	0	0
T21	1733	58	0	0
T22	4157	277	0	0
T58	3066	79	0	0
T59	10152	9	0	0
T60	15501	1094	0	0
T63	3779	240	0	0
T69	2813	64	0	0
T70	11762	1187	0	0
T92	1619	33	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2869400	2708	0	0
T13	1112	0	0	0
T27	0	23	0	0
T28	4460	0	0	0
T31	1993	0	0	0
T54	0	91	0	0
T82	1113	9	0	0
T95	3780	60	0	0
T124	0	57	0	0
T125	0	18	0	0
T126	0	43	0	0
T127	0	11	0	0
T128	0	3	0	0
T129	0	4	0	0
T130	7175	0	0	0
T131	1732	0	0	0
T132	1036	0	0	0
T133	4470	0	0	0
T134	1135	0	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2869400	1666	0	0
T60	15501	11	0	0
T71	7560	5	0	0
T78	12128	20	0	0
T79	14933	102	0	0
T104	1581	12	0	0
T105	15332	181	0	0
T116	3305	30	0	0
T135	15552	258	0	0
T136	9759	8	0	0
T137	15319	150	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2869400	1502	0	0
T60	15501	30	0	0
T71	7560	6	0	0
T78	12128	39	0	0
T79	14933	42	0	0
T104	1581	3	0	0
T105	15332	239	0	0
T116	3305	46	0	0
T135	15552	269	0	0
T136	9759	12	0	0
T137	15319	91	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2869400	1399	0	0
T60	15501	7	0	0
T71	7560	14	0	0
T78	12128	13	0	0
T79	14933	18	0	0
T105	15332	230	0	0
T116	3305	50	0	0
T135	15552	210	0	0
T136	9759	41	0	0
T137	15319	78	0	0
T138	6417	7	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2869400	1932	0	0
T60	15501	26	0	0
T78	12128	21	0	0
T79	14933	130	0	0
T104	1581	18	0	0
T105	15332	222	0	0
T116	3305	45	0	0
T135	15552	202	0	0
T136	9759	34	0	0
T137	15319	224	0	0
T138	6417	21	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2869400	1450	0	0
T60	15501	26	0	0
T71	7560	11	0	0
T78	12128	8	0	0
T79	14933	54	0	0
T105	15332	234	0	0
T116	3305	32	0	0
T135	15552	235	0	0
T136	9759	9	0	0
T137	15319	80	0	0
T138	6417	30	0	0