Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	6666981	9067	0	0
StatusRise_A	6666981	12433	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6666981	9067	0	0
T2	8736	51	0	0
T3	1584	3	0	0
T4	47550	15	0	0
T5	10701	38	0	0
T6	44787	3	0	0
T7	14409	30	0	0
T8	6987	0	0	0
T9	4494	0	0	0
T10	5322	3	0	0
T14	0	12	0	0
T15	10554	0	0	0
T23	0	15	0	0
T45	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6666981	12433	0	0
T1	3861	9	0	0
T2	8736	54	0	0
T3	1584	9	0	0
T4	47550	18	0	0
T5	10701	40	0	0
T6	44787	6	0	0
T7	14409	33	0	0
T8	6987	15	0	0
T9	4494	21	0	0
T10	5322	9	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	2222327	3050	0	0
StatusRise_A	2222327	4183	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2222327	3050	0	0
T2	2912	17	0	0
T3	528	1	0	0
T4	15850	5	0	0
T5	3567	13	0	0
T6	14929	1	0	0
T7	4803	10	0	0
T8	2329	0	0	0
T9	1498	0	0	0
T10	1774	1	0	0
T14	0	4	0	0
T15	3518	0	0	0
T23	0	5	0	0
T45	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2222327	4183	0	0
T1	1287	3	0	0
T2	2912	18	0	0
T3	528	3	0	0
T4	15850	6	0	0
T5	3567	14	0	0
T6	14929	2	0	0
T7	4803	11	0	0
T8	2329	5	0	0
T9	1498	7	0	0
T10	1774	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	2222327	3050	0	0
StatusRise_A	2222327	4183	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2222327	3050	0	0
T2	2912	17	0	0
T3	528	1	0	0
T4	15850	5	0	0
T5	3567	13	0	0
T6	14929	1	0	0
T7	4803	10	0	0
T8	2329	0	0	0
T9	1498	0	0	0
T10	1774	1	0	0
T14	0	4	0	0
T15	3518	0	0	0
T23	0	5	0	0
T45	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2222327	4183	0	0
T1	1287	3	0	0
T2	2912	18	0	0
T3	528	3	0	0
T4	15850	6	0	0
T5	3567	14	0	0
T6	14929	2	0	0
T7	4803	11	0	0
T8	2329	5	0	0
T9	1498	7	0	0
T10	1774	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	2222327	2967	0	0
StatusRise_A	2222327	4067	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2222327	2967	0	0
T2	2912	17	0	0
T3	528	1	0	0
T4	15850	5	0	0
T5	3567	12	0	0
T6	14929	1	0	0
T7	4803	10	0	0
T8	2329	0	0	0
T9	1498	0	0	0
T10	1774	1	0	0
T14	0	4	0	0
T15	3518	0	0	0
T23	0	5	0	0
T45	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2222327	4067	0	0
T1	1287	3	0	0
T2	2912	18	0	0
T3	528	3	0	0
T4	15850	6	0	0
T5	3567	12	0	0
T6	14929	2	0	0
T7	4803	11	0	0
T8	2329	5	0	0
T9	1498	7	0	0
T10	1774	3	0	0