Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	2222679	6140	0	0
EscTimeoutStoppedByClReset_A	2222327	81387	0	0
EscTimeoutTriggersReset_A	305060	328	0	0
RomAllowActiveState_A	2222327	3833	0	0
RomAllowCheckGoodState_A	2222327	3883	0	0
RomBlockActiveState_A	2222327	27814	0	0
RomBlockCheckGoodState_A	2222327	18405	0	0
RomIntgChkDisFalse_A	2222327	2045852	0	0
RomIntgChkDisTrue_A	2222327	23942	0	0
RstreqChkEsctimeout_A	2222327	964	0	0
RstreqChkFsmterm_A	2222327	140	0	0
RstreqChkGlbesc_A	2222327	964	0	0
RstreqChkMainpd_A	2222327	42563	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2222679	6140	0	0
T4	15851	130	0	0
T5	3568	0	0	0
T6	14930	53	0	0
T7	4804	0	0	0
T8	2329	0	0	0
T9	1499	0	0	0
T10	1775	17	0	0
T15	3519	0	0	0
T16	1186	0	0	0
T23	1409	0	0	0
T37	0	30	0	0
T39	0	94	0	0
T46	0	6	0	0
T81	0	65	0	0
T85	0	52	0	0
T139	0	40	0	0
T140	0	27	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2222327	81387	0	0
T1	1287	9	0	0
T2	2912	367	0	0
T3	528	39	0	0
T4	15850	82	0	0
T5	3567	18	0	0
T6	14929	11	0	0
T7	4803	484	0	0
T8	2329	57	0	0
T9	1498	39	0	0
T10	1774	49	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305060	328	0	0
T3	492	10	0	0
T4	201	2	0	0
T5	271	0	0	0
T6	622	3	0	0
T7	350	0	0	0
T8	410	0	0	0
T9	530	0	0	0
T10	210	3	0	0
T15	335	0	0	0
T16	363	0	0	0
T37	0	2	0	0
T39	0	3	0	0
T45	0	4	0	0
T46	0	3	0	0
T81	0	3	0	0
T141	0	3	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2222327	3833	0	0
T1	1287	3	0	0
T2	2912	18	0	0
T3	528	3	0	0
T4	15850	6	0	0
T5	3567	14	0	0
T6	14929	2	0	0
T7	4803	11	0	0
T8	2329	5	0	0
T9	1498	7	0	0
T10	1774	3	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2222327	3883	0	0
T1	1287	3	0	0
T2	2912	18	0	0
T3	528	3	0	0
T4	15850	6	0	0
T5	3567	14	0	0
T6	14929	2	0	0
T7	4803	11	0	0
T8	2329	5	0	0
T9	1498	7	0	0
T10	1774	3	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2222327	27814	0	0
T7	4803	930	0	0
T8	2329	0	0	0
T9	1498	0	0	0
T10	1774	0	0	0
T14	3124	0	0	0
T15	3518	0	0	0
T16	1185	0	0	0
T23	1408	21	0	0
T28	0	1011	0	0
T45	1304	0	0	0
T86	3734	0	0	0
T142	0	73	0	0
T143	0	594	0	0
T144	0	628	0	0
T145	0	421	0	0
T146	0	1055	0	0
T147	0	406	0	0
T148	0	494	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2222327	18405	0	0
T7	4803	879	0	0
T8	2329	0	0	0
T9	1498	0	0	0
T10	1774	0	0	0
T14	3124	0	0	0
T15	3518	0	0	0
T16	1185	0	0	0
T23	1408	0	0	0
T25	0	23	0	0
T28	0	558	0	0
T45	1304	0	0	0
T50	0	23	0	0
T86	3734	0	0	0
T142	0	90	0	0
T143	0	313	0	0
T144	0	317	0	0
T145	0	289	0	0
T146	0	593	0	0
T147	0	285	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2222327	2045852	0	0
T1	1287	1069	0	0
T2	2912	2850	0	0
T3	528	381	0	0
T4	15850	15786	0	0
T5	3567	3515	0	0
T6	14929	14852	0	0
T7	4803	4535	0	0
T8	2329	1926	0	0
T9	1498	970	0	0
T10	1774	1622	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2222327	23942	0	0
T7	4803	190	0	0
T8	2329	0	0	0
T9	1498	0	0	0
T10	1774	0	0	0
T14	3124	0	0	0
T15	3518	0	0	0
T16	1185	0	0	0
T23	1408	82	0	0
T28	0	378	0	0
T45	1304	0	0	0
T86	3734	0	0	0
T142	0	145	0	0
T143	0	279	0	0
T144	0	46	0	0
T145	0	1050	0	0
T146	0	308	0	0
T147	0	1518	0	0
T149	0	117	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2222327	964	0	0
T1	1287	2	0	0
T2	2912	7	0	0
T3	528	1	0	0
T4	15850	1	0	0
T5	3567	0	0	0
T6	14929	1	0	0
T7	4803	3	0	0
T8	2329	4	0	0
T9	1498	0	0	0
T10	1774	1	0	0
T23	0	3	0	0
T45	0	1	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2222327	140	0	0
T11	1020	0	0	0
T17	22491	20	0	0
T18	0	20	0	0
T19	0	20	0	0
T29	2268	0	0	0
T30	1686	0	0	0
T32	1662	0	0	0
T33	0	40	0	0
T34	0	40	0	0
T35	1878	0	0	0
T36	1918	0	0	0
T37	15041	0	0	0
T38	4770	0	0	0
T39	15302	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2222327	964	0	0
T1	1287	2	0	0
T2	2912	7	0	0
T3	528	1	0	0
T4	15850	1	0	0
T5	3567	0	0	0
T6	14929	1	0	0
T7	4803	3	0	0
T8	2329	4	0	0
T9	1498	0	0	0
T10	1774	1	0	0
T23	0	3	0	0
T45	0	1	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2222327	42563	0	0
T2	2912	204	0	0
T3	528	0	0	0
T4	15850	0	0	0
T5	3567	0	0	0
T6	14929	0	0	0
T7	4803	2387	0	0
T8	2329	0	0	0
T9	1498	29	0	0
T10	1774	0	0	0
T15	3518	17	0	0
T16	0	5	0	0
T26	0	99	0	0
T40	0	84	0	0
T41	0	168	0	0
T86	0	27	0	0
T150	0	16	0	0