Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.32 98.23 96.15 99.44 96.00 96.18 100.00 95.25


Total test records in report: 735
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html
T564 /workspace/coverage/default/30.pwrmgr_smoke.2805760895 Jul 30 06:41:41 PM PDT 24 Jul 30 06:41:42 PM PDT 24 39191825 ps
T565 /workspace/coverage/default/6.pwrmgr_escalation_timeout.404888295 Jul 30 06:40:39 PM PDT 24 Jul 30 06:40:40 PM PDT 24 157896073 ps
T566 /workspace/coverage/default/9.pwrmgr_escalation_timeout.3176369133 Jul 30 06:40:53 PM PDT 24 Jul 30 06:40:54 PM PDT 24 164740851 ps
T166 /workspace/coverage/default/33.pwrmgr_wakeup.3629777263 Jul 30 06:41:46 PM PDT 24 Jul 30 06:41:47 PM PDT 24 39603805 ps
T567 /workspace/coverage/default/44.pwrmgr_global_esc.3488092998 Jul 30 06:42:31 PM PDT 24 Jul 30 06:42:32 PM PDT 24 35220188 ps
T568 /workspace/coverage/default/29.pwrmgr_disable_rom_integrity_check.3579195430 Jul 30 06:41:36 PM PDT 24 Jul 30 06:41:37 PM PDT 24 136193490 ps
T569 /workspace/coverage/default/17.pwrmgr_disable_rom_integrity_check.1512142655 Jul 30 06:41:06 PM PDT 24 Jul 30 06:41:09 PM PDT 24 58208388 ps
T570 /workspace/coverage/default/44.pwrmgr_lowpower_invalid.2121518585 Jul 30 06:42:02 PM PDT 24 Jul 30 06:42:03 PM PDT 24 51604614 ps
T571 /workspace/coverage/default/19.pwrmgr_glitch.2411898938 Jul 30 06:41:05 PM PDT 24 Jul 30 06:41:05 PM PDT 24 23006705 ps
T572 /workspace/coverage/default/36.pwrmgr_reset_invalid.4085971940 Jul 30 06:41:47 PM PDT 24 Jul 30 06:41:48 PM PDT 24 118795174 ps
T573 /workspace/coverage/default/18.pwrmgr_glitch.2176894093 Jul 30 06:42:15 PM PDT 24 Jul 30 06:42:16 PM PDT 24 39349838 ps
T574 /workspace/coverage/default/26.pwrmgr_reset.4089787879 Jul 30 06:41:38 PM PDT 24 Jul 30 06:41:39 PM PDT 24 34491478 ps
T575 /workspace/coverage/default/9.pwrmgr_lowpower_invalid.873481154 Jul 30 06:40:51 PM PDT 24 Jul 30 06:40:52 PM PDT 24 42220927 ps
T576 /workspace/coverage/default/19.pwrmgr_sec_cm_rstmgr_intersig_mubi.2388122673 Jul 30 06:41:10 PM PDT 24 Jul 30 06:41:11 PM PDT 24 76601351 ps
T577 /workspace/coverage/default/25.pwrmgr_glitch.2775650322 Jul 30 06:41:33 PM PDT 24 Jul 30 06:41:33 PM PDT 24 76069582 ps
T186 /workspace/coverage/default/8.pwrmgr_lowpower_invalid.273224837 Jul 30 06:40:44 PM PDT 24 Jul 30 06:40:45 PM PDT 24 43610136 ps
T578 /workspace/coverage/default/44.pwrmgr_disable_rom_integrity_check.2540035481 Jul 30 06:42:16 PM PDT 24 Jul 30 06:42:17 PM PDT 24 66413996 ps
T579 /workspace/coverage/default/31.pwrmgr_escalation_timeout.4082828631 Jul 30 06:41:37 PM PDT 24 Jul 30 06:41:38 PM PDT 24 661309959 ps
T580 /workspace/coverage/default/33.pwrmgr_escalation_timeout.3303547619 Jul 30 06:41:37 PM PDT 24 Jul 30 06:41:38 PM PDT 24 326413287 ps
T581 /workspace/coverage/default/39.pwrmgr_reset_invalid.2282320096 Jul 30 06:42:22 PM PDT 24 Jul 30 06:42:23 PM PDT 24 145273989 ps
T582 /workspace/coverage/default/6.pwrmgr_glitch.2451191902 Jul 30 06:40:39 PM PDT 24 Jul 30 06:40:40 PM PDT 24 38820484 ps
T583 /workspace/coverage/default/0.pwrmgr_escalation_timeout.3888520155 Jul 30 06:40:13 PM PDT 24 Jul 30 06:40:14 PM PDT 24 632569522 ps
T584 /workspace/coverage/default/35.pwrmgr_escalation_timeout.3414050673 Jul 30 06:41:54 PM PDT 24 Jul 30 06:41:55 PM PDT 24 631929961 ps
T585 /workspace/coverage/default/48.pwrmgr_aborted_low_power.3268475731 Jul 30 06:42:29 PM PDT 24 Jul 30 06:42:30 PM PDT 24 26816070 ps
T586 /workspace/coverage/default/28.pwrmgr_smoke.691705587 Jul 30 06:41:43 PM PDT 24 Jul 30 06:41:44 PM PDT 24 29720576 ps
T587 /workspace/coverage/default/28.pwrmgr_global_esc.2267256835 Jul 30 06:41:37 PM PDT 24 Jul 30 06:41:38 PM PDT 24 48978759 ps
T588 /workspace/coverage/default/47.pwrmgr_stress_all.3293052547 Jul 30 06:42:28 PM PDT 24 Jul 30 06:42:30 PM PDT 24 240420165 ps
T589 /workspace/coverage/default/10.pwrmgr_sec_cm_rstmgr_intersig_mubi.2894278810 Jul 30 06:40:53 PM PDT 24 Jul 30 06:40:54 PM PDT 24 228388558 ps
T590 /workspace/coverage/default/44.pwrmgr_esc_clk_rst_malfunc.2081074632 Jul 30 06:42:07 PM PDT 24 Jul 30 06:42:08 PM PDT 24 38680552 ps
T591 /workspace/coverage/default/1.pwrmgr_esc_clk_rst_malfunc.587514971 Jul 30 06:40:23 PM PDT 24 Jul 30 06:40:24 PM PDT 24 29744361 ps
T592 /workspace/coverage/default/34.pwrmgr_reset_invalid.3769130262 Jul 30 06:41:45 PM PDT 24 Jul 30 06:41:48 PM PDT 24 91313257 ps
T593 /workspace/coverage/default/6.pwrmgr_aborted_low_power.3822401505 Jul 30 06:40:32 PM PDT 24 Jul 30 06:40:33 PM PDT 24 41694800 ps
T594 /workspace/coverage/default/2.pwrmgr_aborted_low_power.1554133133 Jul 30 06:40:29 PM PDT 24 Jul 30 06:40:30 PM PDT 24 21314801 ps
T595 /workspace/coverage/default/19.pwrmgr_aborted_low_power.403025102 Jul 30 06:41:07 PM PDT 24 Jul 30 06:41:12 PM PDT 24 68842959 ps
T596 /workspace/coverage/default/8.pwrmgr_smoke.4040738297 Jul 30 06:40:47 PM PDT 24 Jul 30 06:40:48 PM PDT 24 46321708 ps
T597 /workspace/coverage/default/33.pwrmgr_reset_invalid.2200847860 Jul 30 06:41:42 PM PDT 24 Jul 30 06:41:43 PM PDT 24 123843035 ps
T598 /workspace/coverage/default/34.pwrmgr_sec_cm_rstmgr_intersig_mubi.1098544984 Jul 30 06:41:54 PM PDT 24 Jul 30 06:41:55 PM PDT 24 110209142 ps
T599 /workspace/coverage/default/29.pwrmgr_escalation_timeout.1004174627 Jul 30 06:41:43 PM PDT 24 Jul 30 06:41:46 PM PDT 24 318149569 ps
T600 /workspace/coverage/default/24.pwrmgr_esc_clk_rst_malfunc.3418732490 Jul 30 06:41:32 PM PDT 24 Jul 30 06:41:33 PM PDT 24 41937164 ps
T601 /workspace/coverage/default/35.pwrmgr_sec_cm_rstmgr_intersig_mubi.268582185 Jul 30 06:41:45 PM PDT 24 Jul 30 06:41:48 PM PDT 24 63750104 ps
T602 /workspace/coverage/default/22.pwrmgr_glitch.2884906925 Jul 30 06:41:19 PM PDT 24 Jul 30 06:41:20 PM PDT 24 43324200 ps
T603 /workspace/coverage/default/46.pwrmgr_disable_rom_integrity_check.4245186986 Jul 30 06:42:28 PM PDT 24 Jul 30 06:42:29 PM PDT 24 55151376 ps
T604 /workspace/coverage/default/39.pwrmgr_smoke.1357026255 Jul 30 06:41:52 PM PDT 24 Jul 30 06:41:53 PM PDT 24 30544872 ps
T605 /workspace/coverage/default/38.pwrmgr_global_esc.1951792980 Jul 30 06:41:46 PM PDT 24 Jul 30 06:41:47 PM PDT 24 57319939 ps
T606 /workspace/coverage/default/39.pwrmgr_escalation_timeout.3571521115 Jul 30 06:42:03 PM PDT 24 Jul 30 06:42:04 PM PDT 24 194600776 ps
T607 /workspace/coverage/default/6.pwrmgr_smoke.1778225078 Jul 30 06:40:38 PM PDT 24 Jul 30 06:40:39 PM PDT 24 139609789 ps
T140 /workspace/coverage/default/9.pwrmgr_wakeup.2988915042 Jul 30 06:40:46 PM PDT 24 Jul 30 06:40:47 PM PDT 24 70679337 ps
T608 /workspace/coverage/default/35.pwrmgr_lowpower_invalid.4153120981 Jul 30 06:42:19 PM PDT 24 Jul 30 06:42:20 PM PDT 24 44979261 ps
T609 /workspace/coverage/default/47.pwrmgr_glitch.1211276688 Jul 30 06:42:28 PM PDT 24 Jul 30 06:42:28 PM PDT 24 50893193 ps
T610 /workspace/coverage/default/35.pwrmgr_esc_clk_rst_malfunc.623417230 Jul 30 06:41:49 PM PDT 24 Jul 30 06:41:50 PM PDT 24 29813896 ps
T611 /workspace/coverage/default/28.pwrmgr_lowpower_invalid.2500502484 Jul 30 06:41:41 PM PDT 24 Jul 30 06:41:42 PM PDT 24 40142056 ps
T612 /workspace/coverage/default/44.pwrmgr_smoke.2522837450 Jul 30 06:42:17 PM PDT 24 Jul 30 06:42:18 PM PDT 24 38118356 ps
T613 /workspace/coverage/default/42.pwrmgr_reset_invalid.1076790994 Jul 30 06:41:57 PM PDT 24 Jul 30 06:41:58 PM PDT 24 178375839 ps
T614 /workspace/coverage/default/24.pwrmgr_disable_rom_integrity_check.2753550154 Jul 30 06:41:33 PM PDT 24 Jul 30 06:41:33 PM PDT 24 106759918 ps
T615 /workspace/coverage/default/34.pwrmgr_disable_rom_integrity_check.2082311695 Jul 30 06:41:54 PM PDT 24 Jul 30 06:41:55 PM PDT 24 53609946 ps
T616 /workspace/coverage/default/14.pwrmgr_reset_invalid.548777554 Jul 30 06:41:02 PM PDT 24 Jul 30 06:41:03 PM PDT 24 163717337 ps
T617 /workspace/coverage/default/25.pwrmgr_sec_cm_rstmgr_intersig_mubi.3226929101 Jul 30 06:41:35 PM PDT 24 Jul 30 06:41:36 PM PDT 24 62471155 ps
T618 /workspace/coverage/default/2.pwrmgr_glitch.4233314367 Jul 30 06:40:25 PM PDT 24 Jul 30 06:40:26 PM PDT 24 35529579 ps
T619 /workspace/coverage/default/38.pwrmgr_glitch.1333056608 Jul 30 06:41:59 PM PDT 24 Jul 30 06:41:59 PM PDT 24 63329406 ps
T620 /workspace/coverage/default/34.pwrmgr_smoke.2519054256 Jul 30 06:41:59 PM PDT 24 Jul 30 06:42:00 PM PDT 24 29138297 ps
T621 /workspace/coverage/default/36.pwrmgr_global_esc.2375354878 Jul 30 06:41:52 PM PDT 24 Jul 30 06:41:53 PM PDT 24 33595758 ps
T622 /workspace/coverage/default/20.pwrmgr_global_esc.1436755927 Jul 30 06:41:07 PM PDT 24 Jul 30 06:41:08 PM PDT 24 83340097 ps
T623 /workspace/coverage/default/21.pwrmgr_global_esc.3439403833 Jul 30 06:41:20 PM PDT 24 Jul 30 06:41:21 PM PDT 24 43981004 ps
T200 /workspace/coverage/default/13.pwrmgr_lowpower_invalid.1960001911 Jul 30 06:41:02 PM PDT 24 Jul 30 06:41:03 PM PDT 24 84317705 ps
T624 /workspace/coverage/default/14.pwrmgr_glitch.1065616034 Jul 30 06:41:02 PM PDT 24 Jul 30 06:41:03 PM PDT 24 40504209 ps
T625 /workspace/coverage/default/48.pwrmgr_global_esc.4210822665 Jul 30 06:42:28 PM PDT 24 Jul 30 06:42:29 PM PDT 24 42454330 ps
T152 /workspace/coverage/default/38.pwrmgr_disable_rom_integrity_check.2039723679 Jul 30 06:42:19 PM PDT 24 Jul 30 06:42:20 PM PDT 24 59784462 ps
T626 /workspace/coverage/default/27.pwrmgr_disable_rom_integrity_check.2719914636 Jul 30 06:41:37 PM PDT 24 Jul 30 06:41:38 PM PDT 24 55553442 ps
T627 /workspace/coverage/default/44.pwrmgr_escalation_timeout.1715586822 Jul 30 06:42:03 PM PDT 24 Jul 30 06:42:04 PM PDT 24 633940996 ps
T628 /workspace/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.2328710422 Jul 30 06:40:47 PM PDT 24 Jul 30 06:40:48 PM PDT 24 33139458 ps
T64 /workspace/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.2155177057 Jul 30 06:38:02 PM PDT 24 Jul 30 06:38:03 PM PDT 24 27885848 ps
T22 /workspace/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.1189752939 Jul 30 06:38:01 PM PDT 24 Jul 30 06:38:03 PM PDT 24 237087394 ps
T63 /workspace/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.443443522 Jul 30 06:38:08 PM PDT 24 Jul 30 06:38:09 PM PDT 24 52146107 ps
T71 /workspace/coverage/cover_reg_top/46.pwrmgr_intr_test.3541959123 Jul 30 06:38:33 PM PDT 24 Jul 30 06:38:34 PM PDT 24 47283034 ps
T23 /workspace/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.2937587319 Jul 30 06:38:14 PM PDT 24 Jul 30 06:38:15 PM PDT 24 182665635 ps
T115 /workspace/coverage/cover_reg_top/6.pwrmgr_csr_rw.1171520854 Jul 30 06:37:59 PM PDT 24 Jul 30 06:38:00 PM PDT 24 20420140 ps
T24 /workspace/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.1530253031 Jul 30 06:37:59 PM PDT 24 Jul 30 06:38:00 PM PDT 24 55563997 ps
T116 /workspace/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.1060846229 Jul 30 06:38:12 PM PDT 24 Jul 30 06:38:13 PM PDT 24 170639356 ps
T117 /workspace/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.3321921929 Jul 30 06:38:30 PM PDT 24 Jul 30 06:38:31 PM PDT 24 53474473 ps
T118 /workspace/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.392397362 Jul 30 06:38:06 PM PDT 24 Jul 30 06:38:07 PM PDT 24 39671247 ps
T72 /workspace/coverage/cover_reg_top/0.pwrmgr_intr_test.3496135780 Jul 30 06:38:14 PM PDT 24 Jul 30 06:38:19 PM PDT 24 44843763 ps
T73 /workspace/coverage/cover_reg_top/14.pwrmgr_intr_test.4169678185 Jul 30 06:38:09 PM PDT 24 Jul 30 06:38:10 PM PDT 24 18673499 ps
T56 /workspace/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.1116131986 Jul 30 06:38:09 PM PDT 24 Jul 30 06:38:10 PM PDT 24 165619985 ps
T119 /workspace/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.478352895 Jul 30 06:38:11 PM PDT 24 Jul 30 06:38:11 PM PDT 24 29880833 ps
T157 /workspace/coverage/cover_reg_top/23.pwrmgr_intr_test.3383930772 Jul 30 06:38:48 PM PDT 24 Jul 30 06:38:49 PM PDT 24 37874339 ps
T629 /workspace/coverage/cover_reg_top/31.pwrmgr_intr_test.178212086 Jul 30 06:38:25 PM PDT 24 Jul 30 06:38:25 PM PDT 24 18717690 ps
T57 /workspace/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.1662204867 Jul 30 06:38:12 PM PDT 24 Jul 30 06:38:14 PM PDT 24 189092403 ps
T158 /workspace/coverage/cover_reg_top/32.pwrmgr_intr_test.3705329071 Jul 30 06:38:46 PM PDT 24 Jul 30 06:38:47 PM PDT 24 25963291 ps
T58 /workspace/coverage/cover_reg_top/10.pwrmgr_tl_errors.2440776152 Jul 30 06:38:09 PM PDT 24 Jul 30 06:38:10 PM PDT 24 128912257 ps
T159 /workspace/coverage/cover_reg_top/48.pwrmgr_intr_test.1745155937 Jul 30 06:38:24 PM PDT 24 Jul 30 06:38:24 PM PDT 24 47717388 ps
T59 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.2226745409 Jul 30 06:37:58 PM PDT 24 Jul 30 06:37:59 PM PDT 24 70493769 ps
T77 /workspace/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.955030694 Jul 30 06:38:15 PM PDT 24 Jul 30 06:38:16 PM PDT 24 59886102 ps
T93 /workspace/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.2800529902 Jul 30 06:38:02 PM PDT 24 Jul 30 06:38:03 PM PDT 24 180219247 ps
T99 /workspace/coverage/cover_reg_top/16.pwrmgr_csr_rw.3521976828 Jul 30 06:38:11 PM PDT 24 Jul 30 06:38:12 PM PDT 24 20521178 ps
T100 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.1883924287 Jul 30 06:37:57 PM PDT 24 Jul 30 06:37:57 PM PDT 24 27935180 ps
T120 /workspace/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.1838112767 Jul 30 06:38:14 PM PDT 24 Jul 30 06:38:15 PM PDT 24 37143653 ps
T630 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.980009517 Jul 30 06:38:04 PM PDT 24 Jul 30 06:38:05 PM PDT 24 96144675 ps
T60 /workspace/coverage/cover_reg_top/11.pwrmgr_tl_errors.744829026 Jul 30 06:38:05 PM PDT 24 Jul 30 06:38:07 PM PDT 24 358946288 ps
T61 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.3514176335 Jul 30 06:37:58 PM PDT 24 Jul 30 06:37:59 PM PDT 24 52825342 ps
T121 /workspace/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.1496442563 Jul 30 06:38:11 PM PDT 24 Jul 30 06:38:12 PM PDT 24 29988018 ps
T78 /workspace/coverage/cover_reg_top/1.pwrmgr_tl_errors.2676124473 Jul 30 06:38:16 PM PDT 24 Jul 30 06:38:17 PM PDT 24 72056279 ps
T631 /workspace/coverage/cover_reg_top/21.pwrmgr_intr_test.275121702 Jul 30 06:38:14 PM PDT 24 Jul 30 06:38:15 PM PDT 24 19952667 ps
T68 /workspace/coverage/cover_reg_top/19.pwrmgr_tl_errors.3357731300 Jul 30 06:38:14 PM PDT 24 Jul 30 06:38:16 PM PDT 24 275376673 ps
T69 /workspace/coverage/cover_reg_top/14.pwrmgr_tl_errors.3153488234 Jul 30 06:38:11 PM PDT 24 Jul 30 06:38:12 PM PDT 24 31015517 ps
T632 /workspace/coverage/cover_reg_top/8.pwrmgr_csr_rw.2668302703 Jul 30 06:38:12 PM PDT 24 Jul 30 06:38:13 PM PDT 24 33382917 ps
T633 /workspace/coverage/cover_reg_top/11.pwrmgr_csr_rw.2986704749 Jul 30 06:38:10 PM PDT 24 Jul 30 06:38:11 PM PDT 24 52229667 ps
T634 /workspace/coverage/cover_reg_top/28.pwrmgr_intr_test.3383866564 Jul 30 06:38:17 PM PDT 24 Jul 30 06:38:18 PM PDT 24 45328105 ps
T122 /workspace/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.2104948845 Jul 30 06:37:59 PM PDT 24 Jul 30 06:38:00 PM PDT 24 28352360 ps
T143 /workspace/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.3915772232 Jul 30 06:37:58 PM PDT 24 Jul 30 06:37:59 PM PDT 24 96249678 ps
T635 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.3933405653 Jul 30 06:38:21 PM PDT 24 Jul 30 06:38:21 PM PDT 24 103160747 ps
T127 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.2338628759 Jul 30 06:38:06 PM PDT 24 Jul 30 06:38:07 PM PDT 24 40228389 ps
T636 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.3143398511 Jul 30 06:38:00 PM PDT 24 Jul 30 06:38:01 PM PDT 24 46036971 ps
T70 /workspace/coverage/cover_reg_top/5.pwrmgr_tl_errors.1970908657 Jul 30 06:38:00 PM PDT 24 Jul 30 06:38:03 PM PDT 24 289619804 ps
T637 /workspace/coverage/cover_reg_top/27.pwrmgr_intr_test.2073235837 Jul 30 06:38:45 PM PDT 24 Jul 30 06:38:46 PM PDT 24 52054266 ps
T638 /workspace/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.2188734992 Jul 30 06:38:14 PM PDT 24 Jul 30 06:38:15 PM PDT 24 157082925 ps
T160 /workspace/coverage/cover_reg_top/5.pwrmgr_intr_test.655367512 Jul 30 06:38:14 PM PDT 24 Jul 30 06:38:15 PM PDT 24 49332065 ps
T144 /workspace/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.1568855645 Jul 30 06:38:09 PM PDT 24 Jul 30 06:38:10 PM PDT 24 252419887 ps
T639 /workspace/coverage/cover_reg_top/12.pwrmgr_tl_errors.1347903589 Jul 30 06:38:10 PM PDT 24 Jul 30 06:38:12 PM PDT 24 64579426 ps
T109 /workspace/coverage/cover_reg_top/13.pwrmgr_csr_rw.238333637 Jul 30 06:38:13 PM PDT 24 Jul 30 06:38:14 PM PDT 24 46592625 ps
T640 /workspace/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.4266656289 Jul 30 06:38:11 PM PDT 24 Jul 30 06:38:12 PM PDT 24 300288041 ps
T101 /workspace/coverage/cover_reg_top/10.pwrmgr_csr_rw.2436929800 Jul 30 06:38:09 PM PDT 24 Jul 30 06:38:10 PM PDT 24 23953508 ps
T641 /workspace/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.2333067832 Jul 30 06:38:12 PM PDT 24 Jul 30 06:38:12 PM PDT 24 60407821 ps
T642 /workspace/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.3037616258 Jul 30 06:38:07 PM PDT 24 Jul 30 06:38:08 PM PDT 24 127008199 ps
T643 /workspace/coverage/cover_reg_top/14.pwrmgr_csr_rw.962805347 Jul 30 06:38:08 PM PDT 24 Jul 30 06:38:09 PM PDT 24 26060573 ps
T644 /workspace/coverage/cover_reg_top/20.pwrmgr_intr_test.2654160135 Jul 30 06:38:14 PM PDT 24 Jul 30 06:38:15 PM PDT 24 19312249 ps
T645 /workspace/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.3872940128 Jul 30 06:38:36 PM PDT 24 Jul 30 06:38:37 PM PDT 24 34857959 ps
T102 /workspace/coverage/cover_reg_top/7.pwrmgr_csr_rw.2080185303 Jul 30 06:38:14 PM PDT 24 Jul 30 06:38:14 PM PDT 24 85298710 ps
T103 /workspace/coverage/cover_reg_top/17.pwrmgr_csr_rw.386266856 Jul 30 06:38:17 PM PDT 24 Jul 30 06:38:18 PM PDT 24 39172796 ps
T646 /workspace/coverage/cover_reg_top/18.pwrmgr_intr_test.415468871 Jul 30 06:38:36 PM PDT 24 Jul 30 06:38:37 PM PDT 24 18819272 ps
T647 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.3897546889 Jul 30 06:37:58 PM PDT 24 Jul 30 06:37:59 PM PDT 24 35615005 ps
T648 /workspace/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.886739639 Jul 30 06:38:12 PM PDT 24 Jul 30 06:38:14 PM PDT 24 57420329 ps
T649 /workspace/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.2710844434 Jul 30 06:38:24 PM PDT 24 Jul 30 06:38:25 PM PDT 24 64478823 ps
T650 /workspace/coverage/cover_reg_top/13.pwrmgr_intr_test.436914295 Jul 30 06:38:14 PM PDT 24 Jul 30 06:38:14 PM PDT 24 112285503 ps
T651 /workspace/coverage/cover_reg_top/26.pwrmgr_intr_test.3346022899 Jul 30 06:38:17 PM PDT 24 Jul 30 06:38:18 PM PDT 24 19175191 ps
T104 /workspace/coverage/cover_reg_top/18.pwrmgr_csr_rw.2388594545 Jul 30 06:38:13 PM PDT 24 Jul 30 06:38:14 PM PDT 24 19864536 ps
T652 /workspace/coverage/cover_reg_top/12.pwrmgr_csr_rw.1137019836 Jul 30 06:38:09 PM PDT 24 Jul 30 06:38:10 PM PDT 24 26938797 ps
T653 /workspace/coverage/cover_reg_top/1.pwrmgr_intr_test.610305613 Jul 30 06:38:02 PM PDT 24 Jul 30 06:38:03 PM PDT 24 47200827 ps
T654 /workspace/coverage/cover_reg_top/15.pwrmgr_intr_test.706495612 Jul 30 06:38:18 PM PDT 24 Jul 30 06:38:18 PM PDT 24 33049926 ps
T655 /workspace/coverage/cover_reg_top/12.pwrmgr_intr_test.3053003184 Jul 30 06:38:12 PM PDT 24 Jul 30 06:38:13 PM PDT 24 33756772 ps
T656 /workspace/coverage/cover_reg_top/4.pwrmgr_intr_test.3527359128 Jul 30 06:37:57 PM PDT 24 Jul 30 06:37:58 PM PDT 24 22139751 ps
T74 /workspace/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.2144998640 Jul 30 06:38:08 PM PDT 24 Jul 30 06:38:09 PM PDT 24 371083323 ps
T657 /workspace/coverage/cover_reg_top/10.pwrmgr_intr_test.3330240848 Jul 30 06:38:07 PM PDT 24 Jul 30 06:38:08 PM PDT 24 56584262 ps
T658 /workspace/coverage/cover_reg_top/16.pwrmgr_intr_test.3445047265 Jul 30 06:38:36 PM PDT 24 Jul 30 06:38:37 PM PDT 24 18659387 ps
T105 /workspace/coverage/cover_reg_top/19.pwrmgr_csr_rw.1672054586 Jul 30 06:38:46 PM PDT 24 Jul 30 06:38:46 PM PDT 24 17486943 ps
T659 /workspace/coverage/cover_reg_top/8.pwrmgr_tl_errors.3525144721 Jul 30 06:38:11 PM PDT 24 Jul 30 06:38:13 PM PDT 24 757204884 ps
T660 /workspace/coverage/cover_reg_top/2.pwrmgr_tl_errors.2525179905 Jul 30 06:38:05 PM PDT 24 Jul 30 06:38:07 PM PDT 24 114895264 ps
T661 /workspace/coverage/cover_reg_top/11.pwrmgr_intr_test.1217947064 Jul 30 06:38:07 PM PDT 24 Jul 30 06:38:08 PM PDT 24 29857884 ps
T106 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_rw.3173129305 Jul 30 06:38:04 PM PDT 24 Jul 30 06:38:05 PM PDT 24 20171724 ps
T662 /workspace/coverage/cover_reg_top/9.pwrmgr_intr_test.3063741679 Jul 30 06:38:06 PM PDT 24 Jul 30 06:38:07 PM PDT 24 39981566 ps
T663 /workspace/coverage/cover_reg_top/3.pwrmgr_tl_errors.3651260294 Jul 30 06:37:56 PM PDT 24 Jul 30 06:37:57 PM PDT 24 38460475 ps
T664 /workspace/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.3469716767 Jul 30 06:38:10 PM PDT 24 Jul 30 06:38:11 PM PDT 24 46538566 ps
T665 /workspace/coverage/cover_reg_top/13.pwrmgr_tl_errors.2049522933 Jul 30 06:38:11 PM PDT 24 Jul 30 06:38:12 PM PDT 24 132258402 ps
T666 /workspace/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.4288984495 Jul 30 06:38:27 PM PDT 24 Jul 30 06:38:28 PM PDT 24 111715100 ps
T667 /workspace/coverage/cover_reg_top/22.pwrmgr_intr_test.1117789338 Jul 30 06:38:18 PM PDT 24 Jul 30 06:38:18 PM PDT 24 108739672 ps
T668 /workspace/coverage/cover_reg_top/45.pwrmgr_intr_test.2537602250 Jul 30 06:38:23 PM PDT 24 Jul 30 06:38:24 PM PDT 24 44696483 ps
T669 /workspace/coverage/cover_reg_top/30.pwrmgr_intr_test.1685776712 Jul 30 06:38:18 PM PDT 24 Jul 30 06:38:19 PM PDT 24 67692905 ps
T670 /workspace/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.2981018531 Jul 30 06:38:00 PM PDT 24 Jul 30 06:38:01 PM PDT 24 53033120 ps
T671 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.96060020 Jul 30 06:38:08 PM PDT 24 Jul 30 06:38:09 PM PDT 24 50570253 ps
T672 /workspace/coverage/cover_reg_top/24.pwrmgr_intr_test.443627902 Jul 30 06:38:41 PM PDT 24 Jul 30 06:38:42 PM PDT 24 51857506 ps
T107 /workspace/coverage/cover_reg_top/9.pwrmgr_csr_rw.1900063896 Jul 30 06:38:08 PM PDT 24 Jul 30 06:38:09 PM PDT 24 17815558 ps
T673 /workspace/coverage/cover_reg_top/18.pwrmgr_tl_errors.1984857955 Jul 30 06:38:10 PM PDT 24 Jul 30 06:38:12 PM PDT 24 64089674 ps
T674 /workspace/coverage/cover_reg_top/0.pwrmgr_tl_errors.1389325966 Jul 30 06:38:12 PM PDT 24 Jul 30 06:38:14 PM PDT 24 101740760 ps
T675 /workspace/coverage/cover_reg_top/16.pwrmgr_tl_errors.2372092366 Jul 30 06:38:11 PM PDT 24 Jul 30 06:38:13 PM PDT 24 31399972 ps
T676 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_rw.1807628495 Jul 30 06:38:00 PM PDT 24 Jul 30 06:38:00 PM PDT 24 40193630 ps
T677 /workspace/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.4185913236 Jul 30 06:38:25 PM PDT 24 Jul 30 06:38:26 PM PDT 24 271934863 ps
T79 /workspace/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.3828890794 Jul 30 06:38:15 PM PDT 24 Jul 30 06:38:17 PM PDT 24 111680363 ps
T678 /workspace/coverage/cover_reg_top/33.pwrmgr_intr_test.4119609638 Jul 30 06:38:54 PM PDT 24 Jul 30 06:38:55 PM PDT 24 45304019 ps
T679 /workspace/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.3466233201 Jul 30 06:38:01 PM PDT 24 Jul 30 06:38:02 PM PDT 24 62485138 ps
T680 /workspace/coverage/cover_reg_top/44.pwrmgr_intr_test.2326003904 Jul 30 06:38:27 PM PDT 24 Jul 30 06:38:28 PM PDT 24 30755096 ps
T681 /workspace/coverage/cover_reg_top/49.pwrmgr_intr_test.1777463005 Jul 30 06:38:25 PM PDT 24 Jul 30 06:38:26 PM PDT 24 21679371 ps
T682 /workspace/coverage/cover_reg_top/36.pwrmgr_intr_test.2508344955 Jul 30 06:38:42 PM PDT 24 Jul 30 06:38:43 PM PDT 24 55840692 ps
T683 /workspace/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.2674358889 Jul 30 06:38:11 PM PDT 24 Jul 30 06:38:12 PM PDT 24 84488642 ps
T684 /workspace/coverage/cover_reg_top/39.pwrmgr_intr_test.1287509654 Jul 30 06:38:25 PM PDT 24 Jul 30 06:38:26 PM PDT 24 20638631 ps
T685 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.347913387 Jul 30 06:37:56 PM PDT 24 Jul 30 06:37:58 PM PDT 24 649138328 ps
T686 /workspace/coverage/cover_reg_top/17.pwrmgr_intr_test.1662414555 Jul 30 06:38:42 PM PDT 24 Jul 30 06:38:43 PM PDT 24 21293329 ps
T687 /workspace/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.1899937156 Jul 30 06:38:10 PM PDT 24 Jul 30 06:38:11 PM PDT 24 42588162 ps
T688 /workspace/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.173976584 Jul 30 06:37:59 PM PDT 24 Jul 30 06:38:00 PM PDT 24 44472266 ps
T689 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.3968264509 Jul 30 06:38:02 PM PDT 24 Jul 30 06:38:05 PM PDT 24 74563919 ps
T690 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.2464146339 Jul 30 06:38:13 PM PDT 24 Jul 30 06:38:16 PM PDT 24 271090480 ps
T691 /workspace/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.814151590 Jul 30 06:38:05 PM PDT 24 Jul 30 06:38:06 PM PDT 24 37649866 ps
T692 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.2320805471 Jul 30 06:38:00 PM PDT 24 Jul 30 06:38:04 PM PDT 24 1061801823 ps
T108 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.4034730469 Jul 30 06:38:14 PM PDT 24 Jul 30 06:38:15 PM PDT 24 33925144 ps
T693 /workspace/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.1463645156 Jul 30 06:38:14 PM PDT 24 Jul 30 06:38:15 PM PDT 24 120870727 ps
T113 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.3223184381 Jul 30 06:38:14 PM PDT 24 Jul 30 06:38:14 PM PDT 24 61710298 ps
T694 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.2852934354 Jul 30 06:38:03 PM PDT 24 Jul 30 06:38:04 PM PDT 24 136482002 ps
T695 /workspace/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.2366040327 Jul 30 06:37:58 PM PDT 24 Jul 30 06:37:59 PM PDT 24 38143659 ps
T696 /workspace/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.2464478233 Jul 30 06:38:01 PM PDT 24 Jul 30 06:38:02 PM PDT 24 77556151 ps
T697 /workspace/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.3050302674 Jul 30 06:38:09 PM PDT 24 Jul 30 06:38:10 PM PDT 24 42405828 ps
T698 /workspace/coverage/cover_reg_top/9.pwrmgr_tl_errors.3852041857 Jul 30 06:38:10 PM PDT 24 Jul 30 06:38:11 PM PDT 24 69842930 ps
T699 /workspace/coverage/cover_reg_top/34.pwrmgr_intr_test.1660791827 Jul 30 06:38:44 PM PDT 24 Jul 30 06:38:44 PM PDT 24 45003465 ps
T700 /workspace/coverage/cover_reg_top/29.pwrmgr_intr_test.437806759 Jul 30 06:38:31 PM PDT 24 Jul 30 06:38:32 PM PDT 24 16723060 ps
T701 /workspace/coverage/cover_reg_top/17.pwrmgr_tl_errors.2248403052 Jul 30 06:38:12 PM PDT 24 Jul 30 06:38:13 PM PDT 24 77056569 ps
T702 /workspace/coverage/cover_reg_top/43.pwrmgr_intr_test.2884796031 Jul 30 06:38:30 PM PDT 24 Jul 30 06:38:31 PM PDT 24 18835639 ps
T703 /workspace/coverage/cover_reg_top/15.pwrmgr_csr_rw.1406534917 Jul 30 06:38:15 PM PDT 24 Jul 30 06:38:16 PM PDT 24 20210199 ps
T704 /workspace/coverage/cover_reg_top/25.pwrmgr_intr_test.1182647093 Jul 30 06:38:19 PM PDT 24 Jul 30 06:38:19 PM PDT 24 16799428 ps
T75 /workspace/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.944006242 Jul 30 06:38:14 PM PDT 24 Jul 30 06:38:16 PM PDT 24 182048675 ps
T80 /workspace/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.3434040960 Jul 30 06:38:21 PM PDT 24 Jul 30 06:38:22 PM PDT 24 306569203 ps
T145 /workspace/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.2098547038 Jul 30 06:38:11 PM PDT 24 Jul 30 06:38:12 PM PDT 24 231369030 ps
T705 /workspace/coverage/cover_reg_top/6.pwrmgr_intr_test.3642078454 Jul 30 06:38:11 PM PDT 24 Jul 30 06:38:11 PM PDT 24 21354473 ps
T706 /workspace/coverage/cover_reg_top/38.pwrmgr_intr_test.2538481756 Jul 30 06:38:24 PM PDT 24 Jul 30 06:38:24 PM PDT 24 49737627 ps
T707 /workspace/coverage/cover_reg_top/42.pwrmgr_intr_test.127145947 Jul 30 06:38:36 PM PDT 24 Jul 30 06:38:37 PM PDT 24 23713502 ps
T146 /workspace/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.3610293646 Jul 30 06:38:13 PM PDT 24 Jul 30 06:38:14 PM PDT 24 109631823 ps
T708 /workspace/coverage/cover_reg_top/41.pwrmgr_intr_test.1578126534 Jul 30 06:38:25 PM PDT 24 Jul 30 06:38:26 PM PDT 24 35205142 ps
T709 /workspace/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.4219837052 Jul 30 06:38:07 PM PDT 24 Jul 30 06:38:08 PM PDT 24 58220795 ps
T710 /workspace/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.3075204650 Jul 30 06:38:12 PM PDT 24 Jul 30 06:38:14 PM PDT 24 109457239 ps
T711 /workspace/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.969248687 Jul 30 06:37:59 PM PDT 24 Jul 30 06:38:00 PM PDT 24 143989156 ps
T712 /workspace/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.3038831582 Jul 30 06:38:07 PM PDT 24 Jul 30 06:38:07 PM PDT 24 36052845 ps
T76 /workspace/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.369950151 Jul 30 06:38:10 PM PDT 24 Jul 30 06:38:12 PM PDT 24 177708144 ps
T713 /workspace/coverage/cover_reg_top/6.pwrmgr_tl_errors.886642029 Jul 30 06:37:58 PM PDT 24 Jul 30 06:37:59 PM PDT 24 31888547 ps
T714 /workspace/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.3118116138 Jul 30 06:38:14 PM PDT 24 Jul 30 06:38:20 PM PDT 24 53354875 ps
T715 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.1449739393 Jul 30 06:37:59 PM PDT 24 Jul 30 06:37:59 PM PDT 24 39830987 ps
T110 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_rw.2856154762 Jul 30 06:38:06 PM PDT 24 Jul 30 06:38:06 PM PDT 24 18317114 ps
T716 /workspace/coverage/cover_reg_top/35.pwrmgr_intr_test.2071450485 Jul 30 06:38:22 PM PDT 24 Jul 30 06:38:22 PM PDT 24 52822646 ps
T717 /workspace/coverage/cover_reg_top/2.pwrmgr_intr_test.1944892525 Jul 30 06:38:12 PM PDT 24 Jul 30 06:38:13 PM PDT 24 20940256 ps
T114 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.3195407458 Jul 30 06:37:55 PM PDT 24 Jul 30 06:37:56 PM PDT 24 97282189 ps
T718 /workspace/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.1393529027 Jul 30 06:38:10 PM PDT 24 Jul 30 06:38:11 PM PDT 24 72977435 ps
T111 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.2832157375 Jul 30 06:38:02 PM PDT 24 Jul 30 06:38:03 PM PDT 24 32539630 ps
T719 /workspace/coverage/cover_reg_top/7.pwrmgr_intr_test.1246762716 Jul 30 06:38:01 PM PDT 24 Jul 30 06:38:02 PM PDT 24 123749204 ps
T720 /workspace/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.644226761 Jul 30 06:37:59 PM PDT 24 Jul 30 06:38:00 PM PDT 24 308824666 ps
T112 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_rw.3608677312 Jul 30 06:37:59 PM PDT 24 Jul 30 06:38:00 PM PDT 24 28280086 ps
T721 /workspace/coverage/cover_reg_top/3.pwrmgr_intr_test.673781752 Jul 30 06:37:57 PM PDT 24 Jul 30 06:37:58 PM PDT 24 20192220 ps
T722 /workspace/coverage/cover_reg_top/8.pwrmgr_intr_test.190068897 Jul 30 06:38:00 PM PDT 24 Jul 30 06:38:00 PM PDT 24 35753742 ps
T723 /workspace/coverage/cover_reg_top/15.pwrmgr_tl_errors.3368905626 Jul 30 06:38:14 PM PDT 24 Jul 30 06:38:16 PM PDT 24 103308949 ps
T724 /workspace/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.4069577172 Jul 30 06:37:58 PM PDT 24 Jul 30 06:38:00 PM PDT 24 107768058 ps
T725 /workspace/coverage/cover_reg_top/47.pwrmgr_intr_test.1140069889 Jul 30 06:38:23 PM PDT 24 Jul 30 06:38:23 PM PDT 24 20605482 ps
T726 /workspace/coverage/cover_reg_top/4.pwrmgr_tl_errors.207428548 Jul 30 06:38:12 PM PDT 24 Jul 30 06:38:14 PM PDT 24 382269272 ps
T727 /workspace/coverage/cover_reg_top/7.pwrmgr_tl_errors.925888952 Jul 30 06:38:02 PM PDT 24 Jul 30 06:38:04 PM PDT 24 91316408 ps
T728 /workspace/coverage/cover_reg_top/5.pwrmgr_csr_rw.781148804 Jul 30 06:38:01 PM PDT 24 Jul 30 06:38:01 PM PDT 24 20129000 ps
T729 /workspace/coverage/cover_reg_top/40.pwrmgr_intr_test.172121250 Jul 30 06:38:25 PM PDT 24 Jul 30 06:38:26 PM PDT 24 44824728 ps
T730 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_rw.306334070 Jul 30 06:37:59 PM PDT 24 Jul 30 06:38:00 PM PDT 24 20175019 ps
T731 /workspace/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.3477682552 Jul 30 06:38:09 PM PDT 24 Jul 30 06:38:10 PM PDT 24 84108029 ps
T732 /workspace/coverage/cover_reg_top/37.pwrmgr_intr_test.3602743775 Jul 30 06:38:32 PM PDT 24 Jul 30 06:38:33 PM PDT 24 21428236 ps
T733 /workspace/coverage/cover_reg_top/19.pwrmgr_intr_test.4221309208 Jul 30 06:38:15 PM PDT 24 Jul 30 06:38:16 PM PDT 24 18137866 ps
T734 /workspace/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.2368884394 Jul 30 06:38:14 PM PDT 24 Jul 30 06:38:15 PM PDT 24 44557707 ps
T735 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.3478287163 Jul 30 06:37:59 PM PDT 24 Jul 30 06:38:00 PM PDT 24 161938826 ps

Test location /workspace/coverage/default/41.pwrmgr_smoke.629406552
Short name T2
Test name
Test status
Simulation time 30168716 ps
CPU time 0.68 seconds
Started Jul 30 06:42:26 PM PDT 24
Finished Jul 30 06:42:27 PM PDT 24
Peak memory 199360 kb
Host smart-851ac46c-81a3-4efb-a77d-d83d0501465b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629406552 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_smoke.629406552
Directory /workspace/41.pwrmgr_smoke/latest

Test location /workspace/coverage/default/24.pwrmgr_reset_invalid.2189938950
Short name T7
Test name
Test status
Simulation time 147373920 ps
CPU time 0.8 seconds
Started Jul 30 06:41:35 PM PDT 24
Finished Jul 30 06:41:36 PM PDT 24
Peak memory 209468 kb
Host smart-30d3ab05-1429-4ec7-aa87-30cc127c8fa1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189938950 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset_invalid.2189938950
Directory /workspace/24.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/15.pwrmgr_aborted_low_power.2184861693
Short name T26
Test name
Test status
Simulation time 89848393 ps
CPU time 0.75 seconds
Started Jul 30 06:41:12 PM PDT 24
Finished Jul 30 06:41:13 PM PDT 24
Peak memory 199020 kb
Host smart-f02abfa6-a8ff-4417-8217-7aa9b5714654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184861693 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_aborted_low_power.2184861693
Directory /workspace/15.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.2937587319
Short name T23
Test name
Test status
Simulation time 182665635 ps
CPU time 1.65 seconds
Started Jul 30 06:38:14 PM PDT 24
Finished Jul 30 06:38:15 PM PDT 24
Peak memory 200464 kb
Host smart-d0f6efdf-85e3-42e0-a2d9-716a90144006
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937587319 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_intg_er
r.2937587319
Directory /workspace/14.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm.1530946898
Short name T19
Test name
Test status
Simulation time 1983654462 ps
CPU time 1.37 seconds
Started Jul 30 06:40:27 PM PDT 24
Finished Jul 30 06:40:28 PM PDT 24
Peak memory 217048 kb
Host smart-4efff887-16c2-45b1-95a0-b731a4da8935
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530946898 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm.1530946898
Directory /workspace/1.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/11.pwrmgr_lowpower_invalid.122492200
Short name T51
Test name
Test status
Simulation time 44630296 ps
CPU time 0.76 seconds
Started Jul 30 06:40:56 PM PDT 24
Finished Jul 30 06:40:57 PM PDT 24
Peak memory 201420 kb
Host smart-9573a174-7638-4972-bf9a-2e9195a8d438
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122492200 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_lowpower_invali
d.122492200
Directory /workspace/11.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/41.pwrmgr_wakeup.1189746702
Short name T54
Test name
Test status
Simulation time 134183275 ps
CPU time 0.85 seconds
Started Jul 30 06:42:00 PM PDT 24
Finished Jul 30 06:42:01 PM PDT 24
Peak memory 198308 kb
Host smart-575c959b-8469-46dc-8e23-a68ee498fcd6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189746702 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_wakeup.1189746702
Directory /workspace/41.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/3.pwrmgr_disable_rom_integrity_check.1762742232
Short name T29
Test name
Test status
Simulation time 55924233 ps
CPU time 0.94 seconds
Started Jul 30 06:40:33 PM PDT 24
Finished Jul 30 06:40:34 PM PDT 24
Peak memory 199124 kb
Host smart-d3595a11-e05f-48d3-81fb-69b1dd036045
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762742232 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_disa
ble_rom_integrity_check.1762742232
Directory /workspace/3.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_tl_errors.744829026
Short name T60
Test name
Test status
Simulation time 358946288 ps
CPU time 1.85 seconds
Started Jul 30 06:38:05 PM PDT 24
Finished Jul 30 06:38:07 PM PDT 24
Peak memory 197660 kb
Host smart-922a51e9-cc73-4c16-9e04-7ff35f21951c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744829026 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_errors.744829026
Directory /workspace/11.pwrmgr_tl_errors/latest

Test location /workspace/coverage/default/20.pwrmgr_aborted_low_power.491347315
Short name T15
Test name
Test status
Simulation time 24889617 ps
CPU time 0.8 seconds
Started Jul 30 06:41:13 PM PDT 24
Finished Jul 30 06:41:14 PM PDT 24
Peak memory 200252 kb
Host smart-3a1dcebf-008e-442e-af45-f4995ce17d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491347315 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_aborted_low_power.491347315
Directory /workspace/20.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/43.pwrmgr_wakeup_reset.1772582677
Short name T44
Test name
Test status
Simulation time 50787321 ps
CPU time 0.68 seconds
Started Jul 30 06:42:20 PM PDT 24
Finished Jul 30 06:42:20 PM PDT 24
Peak memory 199328 kb
Host smart-3052261b-25e5-44a5-bca2-335c95ad7962
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772582677 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_wakeup_reset.1772582677
Directory /workspace/43.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/13.pwrmgr_sec_cm_ctrl_config_regwen.1508788185
Short name T52
Test name
Test status
Simulation time 59417024 ps
CPU time 0.75 seconds
Started Jul 30 06:41:00 PM PDT 24
Finished Jul 30 06:41:00 PM PDT 24
Peak memory 199156 kb
Host smart-b388f43a-56a6-45b5-8073-1a42718bc6d7
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508788185 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_
cm_ctrl_config_regwen.1508788185
Directory /workspace/13.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/cover_reg_top/48.pwrmgr_intr_test.1745155937
Short name T159
Test name
Test status
Simulation time 47717388 ps
CPU time 0.64 seconds
Started Jul 30 06:38:24 PM PDT 24
Finished Jul 30 06:38:24 PM PDT 24
Peak memory 195068 kb
Host smart-d6667857-51f6-40e4-9274-261e2f4c510e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745155937 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.pwrmgr_intr_test.1745155937
Directory /workspace/48.pwrmgr_intr_test/latest

Test location /workspace/coverage/default/13.pwrmgr_reset_invalid.2036881508
Short name T208
Test name
Test status
Simulation time 107270374 ps
CPU time 1.07 seconds
Started Jul 30 06:41:00 PM PDT 24
Finished Jul 30 06:41:02 PM PDT 24
Peak memory 209548 kb
Host smart-0b0e672f-2b14-40cf-b8d5-75cb03c59861
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036881508 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset_invalid.2036881508
Directory /workspace/13.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/28.pwrmgr_esc_clk_rst_malfunc.1081681117
Short name T48
Test name
Test status
Simulation time 44335902 ps
CPU time 0.58 seconds
Started Jul 30 06:41:39 PM PDT 24
Finished Jul 30 06:41:40 PM PDT 24
Peak memory 198028 kb
Host smart-61a9a5f4-3186-4377-9749-3c10050fea7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081681117 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_esc_clk_rst
_malfunc.1081681117
Directory /workspace/28.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/33.pwrmgr_disable_rom_integrity_check.800910327
Short name T137
Test name
Test status
Simulation time 57942943 ps
CPU time 0.69 seconds
Started Jul 30 06:41:43 PM PDT 24
Finished Jul 30 06:41:44 PM PDT 24
Peak memory 199160 kb
Host smart-841e9f6b-4b69-49ce-b409-fcc0565d50a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800910327 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_disa
ble_rom_integrity_check.800910327
Directory /workspace/33.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_csr_rw.2388594545
Short name T104
Test name
Test status
Simulation time 19864536 ps
CPU time 0.7 seconds
Started Jul 30 06:38:13 PM PDT 24
Finished Jul 30 06:38:14 PM PDT 24
Peak memory 196512 kb
Host smart-a7dce8ec-f754-4ac2-8338-9173d3022206
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388594545 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_csr_rw.2388594545
Directory /workspace/18.pwrmgr_csr_rw/latest

Test location /workspace/coverage/default/9.pwrmgr_lowpower_wakeup_race.3283875692
Short name T25
Test name
Test status
Simulation time 68192189 ps
CPU time 0.69 seconds
Started Jul 30 06:40:51 PM PDT 24
Finished Jul 30 06:40:52 PM PDT 24
Peak memory 198292 kb
Host smart-a0e94e82-562a-4039-a13c-02b290bb6d32
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283875692 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_lowpower_wa
keup_race.3283875692
Directory /workspace/9.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/42.pwrmgr_lowpower_invalid.3094170562
Short name T92
Test name
Test status
Simulation time 43866728 ps
CPU time 0.7 seconds
Started Jul 30 06:41:59 PM PDT 24
Finished Jul 30 06:42:00 PM PDT 24
Peak memory 201448 kb
Host smart-7afdf8b1-86da-4ae4-841b-fce6a924bf23
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094170562 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_lowpower_inval
id.3094170562
Directory /workspace/42.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/11.pwrmgr_disable_rom_integrity_check.1992306834
Short name T149
Test name
Test status
Simulation time 143490854 ps
CPU time 0.67 seconds
Started Jul 30 06:41:00 PM PDT 24
Finished Jul 30 06:41:01 PM PDT 24
Peak memory 198444 kb
Host smart-f87b87d7-7b45-4491-842a-e2662f04d7e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992306834 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_dis
able_rom_integrity_check.1992306834
Directory /workspace/11.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/23.pwrmgr_disable_rom_integrity_check.1621816380
Short name T27
Test name
Test status
Simulation time 74605844 ps
CPU time 0.68 seconds
Started Jul 30 06:41:12 PM PDT 24
Finished Jul 30 06:41:13 PM PDT 24
Peak memory 198596 kb
Host smart-eca17610-9598-47a6-9d93-af59121e00b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621816380 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_dis
able_rom_integrity_check.1621816380
Directory /workspace/23.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/3.pwrmgr_lowpower_invalid.1656237196
Short name T1
Test name
Test status
Simulation time 110486635 ps
CPU time 0.66 seconds
Started Jul 30 06:40:30 PM PDT 24
Finished Jul 30 06:40:31 PM PDT 24
Peak memory 201456 kb
Host smart-12988d44-a6fa-420f-9716-f9c2fd392e1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656237196 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_lowpower_invali
d.1656237196
Directory /workspace/3.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_tl_errors.3153488234
Short name T69
Test name
Test status
Simulation time 31015517 ps
CPU time 1.33 seconds
Started Jul 30 06:38:11 PM PDT 24
Finished Jul 30 06:38:12 PM PDT 24
Peak memory 196416 kb
Host smart-26ded2b3-62d6-466f-81b0-ea6ec2560cf2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153488234 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_errors.3153488234
Directory /workspace/14.pwrmgr_tl_errors/latest

Test location /workspace/coverage/default/2.pwrmgr_disable_rom_integrity_check.3727855339
Short name T155
Test name
Test status
Simulation time 61171182 ps
CPU time 0.71 seconds
Started Jul 30 06:40:25 PM PDT 24
Finished Jul 30 06:40:26 PM PDT 24
Peak memory 199172 kb
Host smart-70931772-b80c-440a-8aba-8ad7e447418b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727855339 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_disa
ble_rom_integrity_check.3727855339
Directory /workspace/2.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/46.pwrmgr_aborted_low_power.2842870845
Short name T178
Test name
Test status
Simulation time 53823972 ps
CPU time 0.9 seconds
Started Jul 30 06:42:30 PM PDT 24
Finished Jul 30 06:42:32 PM PDT 24
Peak memory 200256 kb
Host smart-f947c236-6f3d-414e-8028-5ba6adaf22b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842870845 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_aborted_low_power.2842870845
Directory /workspace/46.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/30.pwrmgr_lowpower_invalid.3900366151
Short name T202
Test name
Test status
Simulation time 82506244 ps
CPU time 0.67 seconds
Started Jul 30 06:41:47 PM PDT 24
Finished Jul 30 06:41:48 PM PDT 24
Peak memory 201436 kb
Host smart-c1fdf774-36a1-4958-85a3-95b4846c256b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900366151 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_lowpower_inval
id.3900366151
Directory /workspace/30.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/38.pwrmgr_sec_cm_rstmgr_intersig_mubi.4060665786
Short name T126
Test name
Test status
Simulation time 145151806 ps
CPU time 0.83 seconds
Started Jul 30 06:42:24 PM PDT 24
Finished Jul 30 06:42:25 PM PDT 24
Peak memory 199224 kb
Host smart-20dc4fc0-c501-4ac6-8e25-05d7ae84ba1f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060665786 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4060665786
Directory /workspace/38.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.2098547038
Short name T145
Test name
Test status
Simulation time 231369030 ps
CPU time 1.15 seconds
Started Jul 30 06:38:11 PM PDT 24
Finished Jul 30 06:38:12 PM PDT 24
Peak memory 200384 kb
Host smart-c9dd823a-2a87-4bb2-8fe1-c63fd1d6988f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098547038 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_intg_er
r.2098547038
Directory /workspace/18.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/10.pwrmgr_lowpower_invalid.1955054080
Short name T185
Test name
Test status
Simulation time 51764207 ps
CPU time 0.68 seconds
Started Jul 30 06:41:04 PM PDT 24
Finished Jul 30 06:41:04 PM PDT 24
Peak memory 201488 kb
Host smart-8cb11b50-e17a-4e69-a65a-f3769d189d43
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955054080 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_lowpower_inval
id.1955054080
Directory /workspace/10.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/19.pwrmgr_disable_rom_integrity_check.4220364114
Short name T156
Test name
Test status
Simulation time 55966643 ps
CPU time 0.67 seconds
Started Jul 30 06:41:05 PM PDT 24
Finished Jul 30 06:41:06 PM PDT 24
Peak memory 198356 kb
Host smart-211024c4-2638-4965-9a76-3ecc370c43ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220364114 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_dis
able_rom_integrity_check.4220364114
Directory /workspace/19.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/9.pwrmgr_wakeup.2988915042
Short name T140
Test name
Test status
Simulation time 70679337 ps
CPU time 0.65 seconds
Started Jul 30 06:40:46 PM PDT 24
Finished Jul 30 06:40:47 PM PDT 24
Peak memory 199168 kb
Host smart-c9c34d4f-de73-47ef-997a-8953950d8cbc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988915042 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_wakeup.2988915042
Directory /workspace/9.pwrmgr_wakeup/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.1496442563
Short name T121
Test name
Test status
Simulation time 29988018 ps
CPU time 0.73 seconds
Started Jul 30 06:38:11 PM PDT 24
Finished Jul 30 06:38:12 PM PDT 24
Peak memory 197380 kb
Host smart-e29a320c-083d-450b-b7e5-32827ad9469a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496442563 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sa
me_csr_outstanding.1496442563
Directory /workspace/0.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/default/12.pwrmgr_glitch.1377524847
Short name T18
Test name
Test status
Simulation time 46032221 ps
CPU time 0.69 seconds
Started Jul 30 06:40:59 PM PDT 24
Finished Jul 30 06:41:00 PM PDT 24
Peak memory 198076 kb
Host smart-73bb5e63-f37a-4de6-87f4-8d94ad08b57f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377524847 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_glitch.1377524847
Directory /workspace/12.pwrmgr_glitch/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.3514176335
Short name T61
Test name
Test status
Simulation time 52825342 ps
CPU time 1.02 seconds
Started Jul 30 06:37:58 PM PDT 24
Finished Jul 30 06:37:59 PM PDT 24
Peak memory 195324 kb
Host smart-1594de58-872c-4ffd-abef-2df9f17bf130
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514176335 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.pwrmgr_csr_mem_rw_with_rand_reset.3514176335
Directory /workspace/0.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_intr_test.3053003184
Short name T655
Test name
Test status
Simulation time 33756772 ps
CPU time 0.63 seconds
Started Jul 30 06:38:12 PM PDT 24
Finished Jul 30 06:38:13 PM PDT 24
Peak memory 195088 kb
Host smart-910d9cdb-4976-4c11-a391-b6d272904aeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053003184 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_intr_test.3053003184
Directory /workspace/12.pwrmgr_intr_test/latest

Test location /workspace/coverage/default/0.pwrmgr_lowpower_invalid.3694998157
Short name T195
Test name
Test status
Simulation time 42295237 ps
CPU time 0.72 seconds
Started Jul 30 06:40:17 PM PDT 24
Finished Jul 30 06:40:18 PM PDT 24
Peak memory 201212 kb
Host smart-0e7ad50c-1893-453c-9861-90219cd8bc67
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694998157 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_lowpower_invali
d.3694998157
Directory /workspace/0.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/1.pwrmgr_lowpower_invalid.2342270260
Short name T193
Test name
Test status
Simulation time 52695820 ps
CPU time 0.68 seconds
Started Jul 30 06:40:31 PM PDT 24
Finished Jul 30 06:40:32 PM PDT 24
Peak memory 201432 kb
Host smart-347e5990-fd43-428c-9e0c-8736093d6642
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342270260 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_lowpower_invali
d.2342270260
Directory /workspace/1.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/25.pwrmgr_lowpower_invalid.1486393449
Short name T427
Test name
Test status
Simulation time 51551428 ps
CPU time 0.7 seconds
Started Jul 30 06:41:37 PM PDT 24
Finished Jul 30 06:41:38 PM PDT 24
Peak memory 201492 kb
Host smart-54df6cd0-857d-46d3-91f2-4409bcd2d78c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486393449 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_lowpower_inval
id.1486393449
Directory /workspace/25.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/26.pwrmgr_lowpower_invalid.3560023596
Short name T190
Test name
Test status
Simulation time 55035017 ps
CPU time 0.7 seconds
Started Jul 30 06:41:41 PM PDT 24
Finished Jul 30 06:41:42 PM PDT 24
Peak memory 201448 kb
Host smart-90b6dfab-6566-4b38-ab17-898e04d4326c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560023596 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_lowpower_inval
id.3560023596
Directory /workspace/26.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/31.pwrmgr_lowpower_invalid.2023245641
Short name T180
Test name
Test status
Simulation time 134078750 ps
CPU time 0.64 seconds
Started Jul 30 06:41:46 PM PDT 24
Finished Jul 30 06:41:46 PM PDT 24
Peak memory 201272 kb
Host smart-dd3c4e6e-9d3a-491a-a210-15be90cabe4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023245641 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_lowpower_inval
id.2023245641
Directory /workspace/31.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/33.pwrmgr_wakeup.3629777263
Short name T166
Test name
Test status
Simulation time 39603805 ps
CPU time 0.62 seconds
Started Jul 30 06:41:46 PM PDT 24
Finished Jul 30 06:41:47 PM PDT 24
Peak memory 198220 kb
Host smart-a96e56ae-cd6c-442c-8fe8-87f0981ff0f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629777263 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_wakeup.3629777263
Directory /workspace/33.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/38.pwrmgr_disable_rom_integrity_check.2039723679
Short name T152
Test name
Test status
Simulation time 59784462 ps
CPU time 0.71 seconds
Started Jul 30 06:42:19 PM PDT 24
Finished Jul 30 06:42:20 PM PDT 24
Peak memory 199056 kb
Host smart-7b75cc48-db70-41da-89eb-27c119dd5f14
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039723679 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_dis
able_rom_integrity_check.2039723679
Directory /workspace/38.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/38.pwrmgr_lowpower_invalid.73784171
Short name T203
Test name
Test status
Simulation time 44780253 ps
CPU time 0.73 seconds
Started Jul 30 06:41:46 PM PDT 24
Finished Jul 30 06:41:48 PM PDT 24
Peak memory 201352 kb
Host smart-3e87ed93-cfba-480a-99df-271243c6b1f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73784171 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invali
d_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_lowpower_invalid
.73784171
Directory /workspace/38.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/8.pwrmgr_lowpower_invalid.273224837
Short name T186
Test name
Test status
Simulation time 43610136 ps
CPU time 0.78 seconds
Started Jul 30 06:40:44 PM PDT 24
Finished Jul 30 06:40:45 PM PDT 24
Peak memory 201388 kb
Host smart-e6b550d2-46d5-4f93-8789-80db9d33b98b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273224837 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_lowpower_invalid
.273224837
Directory /workspace/8.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.944006242
Short name T75
Test name
Test status
Simulation time 182048675 ps
CPU time 1.61 seconds
Started Jul 30 06:38:14 PM PDT 24
Finished Jul 30 06:38:16 PM PDT 24
Peak memory 200724 kb
Host smart-be3feb97-4dd9-4969-9e88-db302686870a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944006242 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_intg_err.
944006242
Directory /workspace/0.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.4034730469
Short name T108
Test name
Test status
Simulation time 33925144 ps
CPU time 0.81 seconds
Started Jul 30 06:38:14 PM PDT 24
Finished Jul 30 06:38:15 PM PDT 24
Peak memory 197492 kb
Host smart-24ee2f6f-faa5-437e-a240-d734da1badab
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034730469 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_aliasing.4
034730469
Directory /workspace/0.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.3478287163
Short name T735
Test name
Test status
Simulation time 161938826 ps
CPU time 1.74 seconds
Started Jul 30 06:37:59 PM PDT 24
Finished Jul 30 06:38:00 PM PDT 24
Peak memory 195240 kb
Host smart-0a207263-a0e7-42e4-8215-c5d9db174f9e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478287163 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_bit_bash.3
478287163
Directory /workspace/0.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.3223184381
Short name T113
Test name
Test status
Simulation time 61710298 ps
CPU time 0.61 seconds
Started Jul 30 06:38:14 PM PDT 24
Finished Jul 30 06:38:14 PM PDT 24
Peak memory 195136 kb
Host smart-6fb91bcb-4cb9-42c4-a060-11215bea81bb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223184381 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_hw_reset.3
223184381
Directory /workspace/0.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_rw.3608677312
Short name T112
Test name
Test status
Simulation time 28280086 ps
CPU time 0.64 seconds
Started Jul 30 06:37:59 PM PDT 24
Finished Jul 30 06:38:00 PM PDT 24
Peak memory 195156 kb
Host smart-fe2dd4ca-e5cf-4c19-b079-0185e6da22a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608677312 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_rw.3608677312
Directory /workspace/0.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_intr_test.3496135780
Short name T72
Test name
Test status
Simulation time 44843763 ps
CPU time 0.6 seconds
Started Jul 30 06:38:14 PM PDT 24
Finished Jul 30 06:38:19 PM PDT 24
Peak memory 195052 kb
Host smart-f3691878-d828-411f-82fb-efead962527d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496135780 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_intr_test.3496135780
Directory /workspace/0.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_tl_errors.1389325966
Short name T674
Test name
Test status
Simulation time 101740760 ps
CPU time 1.47 seconds
Started Jul 30 06:38:12 PM PDT 24
Finished Jul 30 06:38:14 PM PDT 24
Peak memory 196552 kb
Host smart-a5a19e74-755a-4f41-bfe2-42eb2e39e480
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389325966 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_errors.1389325966
Directory /workspace/0.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.980009517
Short name T630
Test name
Test status
Simulation time 96144675 ps
CPU time 0.82 seconds
Started Jul 30 06:38:04 PM PDT 24
Finished Jul 30 06:38:05 PM PDT 24
Peak memory 195072 kb
Host smart-78122ab8-365d-45f6-829b-e29b472637c9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980009517 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_aliasing.980009517
Directory /workspace/1.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.3968264509
Short name T689
Test name
Test status
Simulation time 74563919 ps
CPU time 2.82 seconds
Started Jul 30 06:38:02 PM PDT 24
Finished Jul 30 06:38:05 PM PDT 24
Peak memory 195316 kb
Host smart-b5fae66b-ace2-4dfd-a08c-2a141a048fd0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968264509 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_bit_bash.3
968264509
Directory /workspace/1.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.3933405653
Short name T635
Test name
Test status
Simulation time 103160747 ps
CPU time 0.66 seconds
Started Jul 30 06:38:21 PM PDT 24
Finished Jul 30 06:38:21 PM PDT 24
Peak memory 198328 kb
Host smart-a24f3cbf-deea-4553-9231-942a603be6c2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933405653 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_hw_reset.3
933405653
Directory /workspace/1.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.2852934354
Short name T694
Test name
Test status
Simulation time 136482002 ps
CPU time 1.06 seconds
Started Jul 30 06:38:03 PM PDT 24
Finished Jul 30 06:38:04 PM PDT 24
Peak memory 196264 kb
Host smart-44016356-7c66-482b-8488-06a5fe3faf64
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852934354 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.pwrmgr_csr_mem_rw_with_rand_reset.2852934354
Directory /workspace/1.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_rw.306334070
Short name T730
Test name
Test status
Simulation time 20175019 ps
CPU time 0.67 seconds
Started Jul 30 06:37:59 PM PDT 24
Finished Jul 30 06:38:00 PM PDT 24
Peak memory 197368 kb
Host smart-bbc1a425-7195-4bac-8674-f38280027df3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306334070 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_rw.306334070
Directory /workspace/1.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_intr_test.610305613
Short name T653
Test name
Test status
Simulation time 47200827 ps
CPU time 0.58 seconds
Started Jul 30 06:38:02 PM PDT 24
Finished Jul 30 06:38:03 PM PDT 24
Peak memory 195048 kb
Host smart-1e70eb3d-7b7f-4633-8e78-6500d728a686
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610305613 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_intr_test.610305613
Directory /workspace/1.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.173976584
Short name T688
Test name
Test status
Simulation time 44472266 ps
CPU time 0.69 seconds
Started Jul 30 06:37:59 PM PDT 24
Finished Jul 30 06:38:00 PM PDT 24
Peak memory 195120 kb
Host smart-37b5ad41-49df-4359-938e-42f3abfd8ed3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173976584 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sam
e_csr_outstanding.173976584
Directory /workspace/1.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_tl_errors.2676124473
Short name T78
Test name
Test status
Simulation time 72056279 ps
CPU time 1.54 seconds
Started Jul 30 06:38:16 PM PDT 24
Finished Jul 30 06:38:17 PM PDT 24
Peak memory 196448 kb
Host smart-355ad665-868c-48f1-b880-1ebf60838739
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676124473 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_errors.2676124473
Directory /workspace/1.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.4069577172
Short name T724
Test name
Test status
Simulation time 107768058 ps
CPU time 1.13 seconds
Started Jul 30 06:37:58 PM PDT 24
Finished Jul 30 06:38:00 PM PDT 24
Peak memory 200308 kb
Host smart-77334e8d-dc95-4939-b845-e8f7b01926bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069577172 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_intg_err
.4069577172
Directory /workspace/1.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.4219837052
Short name T709
Test name
Test status
Simulation time 58220795 ps
CPU time 1.09 seconds
Started Jul 30 06:38:07 PM PDT 24
Finished Jul 30 06:38:08 PM PDT 24
Peak memory 200604 kb
Host smart-fcaf5c4d-d64d-4e5a-8edd-ad85657d77fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219837052 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.pwrmgr_csr_mem_rw_with_rand_reset.4219837052
Directory /workspace/10.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_csr_rw.2436929800
Short name T101
Test name
Test status
Simulation time 23953508 ps
CPU time 0.69 seconds
Started Jul 30 06:38:09 PM PDT 24
Finished Jul 30 06:38:10 PM PDT 24
Peak memory 197276 kb
Host smart-eb72cc10-0638-4bd3-ac37-965a4719e32e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436929800 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_csr_rw.2436929800
Directory /workspace/10.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_intr_test.3330240848
Short name T657
Test name
Test status
Simulation time 56584262 ps
CPU time 0.63 seconds
Started Jul 30 06:38:07 PM PDT 24
Finished Jul 30 06:38:08 PM PDT 24
Peak memory 195068 kb
Host smart-e61bc886-7284-4153-840e-ee42dd9facf0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330240848 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_intr_test.3330240848
Directory /workspace/10.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.392397362
Short name T118
Test name
Test status
Simulation time 39671247 ps
CPU time 0.89 seconds
Started Jul 30 06:38:06 PM PDT 24
Finished Jul 30 06:38:07 PM PDT 24
Peak memory 195136 kb
Host smart-67c59d09-1650-4969-984a-93cd351862bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392397362 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sa
me_csr_outstanding.392397362
Directory /workspace/10.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_tl_errors.2440776152
Short name T58
Test name
Test status
Simulation time 128912257 ps
CPU time 1.42 seconds
Started Jul 30 06:38:09 PM PDT 24
Finished Jul 30 06:38:10 PM PDT 24
Peak memory 196400 kb
Host smart-33d85400-62ba-4b88-b496-5e3b9a815578
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440776152 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_errors.2440776152
Directory /workspace/10.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.2144998640
Short name T74
Test name
Test status
Simulation time 371083323 ps
CPU time 1.54 seconds
Started Jul 30 06:38:08 PM PDT 24
Finished Jul 30 06:38:09 PM PDT 24
Peak memory 200704 kb
Host smart-72cf2b6b-324f-43da-bc63-c75b21f554e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144998640 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_intg_er
r.2144998640
Directory /workspace/10.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.3466233201
Short name T679
Test name
Test status
Simulation time 62485138 ps
CPU time 0.81 seconds
Started Jul 30 06:38:01 PM PDT 24
Finished Jul 30 06:38:02 PM PDT 24
Peak memory 195240 kb
Host smart-d5d6fe9f-763e-4d04-9524-657e914b0225
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466233201 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.pwrmgr_csr_mem_rw_with_rand_reset.3466233201
Directory /workspace/11.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_csr_rw.2986704749
Short name T633
Test name
Test status
Simulation time 52229667 ps
CPU time 0.63 seconds
Started Jul 30 06:38:10 PM PDT 24
Finished Jul 30 06:38:11 PM PDT 24
Peak memory 197312 kb
Host smart-06e3f054-9535-4339-8884-d30186d925a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986704749 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_csr_rw.2986704749
Directory /workspace/11.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_intr_test.1217947064
Short name T661
Test name
Test status
Simulation time 29857884 ps
CPU time 0.64 seconds
Started Jul 30 06:38:07 PM PDT 24
Finished Jul 30 06:38:08 PM PDT 24
Peak memory 195108 kb
Host smart-f939ad0b-38c6-4faf-80e7-827b3fcaa035
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217947064 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_intr_test.1217947064
Directory /workspace/11.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.1838112767
Short name T120
Test name
Test status
Simulation time 37143653 ps
CPU time 0.84 seconds
Started Jul 30 06:38:14 PM PDT 24
Finished Jul 30 06:38:15 PM PDT 24
Peak memory 198612 kb
Host smart-e82d304b-29c7-46c1-b199-e46650db202a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838112767 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_s
ame_csr_outstanding.1838112767
Directory /workspace/11.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.1116131986
Short name T56
Test name
Test status
Simulation time 165619985 ps
CPU time 1.1 seconds
Started Jul 30 06:38:09 PM PDT 24
Finished Jul 30 06:38:10 PM PDT 24
Peak memory 200604 kb
Host smart-b5d97835-a0c7-4334-9bed-76a2ceb90762
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116131986 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_intg_er
r.1116131986
Directory /workspace/11.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.3118116138
Short name T714
Test name
Test status
Simulation time 53354875 ps
CPU time 0.9 seconds
Started Jul 30 06:38:14 PM PDT 24
Finished Jul 30 06:38:20 PM PDT 24
Peak memory 195264 kb
Host smart-1171cf2e-a637-442d-931b-9aec2d1fefa5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118116138 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.pwrmgr_csr_mem_rw_with_rand_reset.3118116138
Directory /workspace/12.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_csr_rw.1137019836
Short name T652
Test name
Test status
Simulation time 26938797 ps
CPU time 0.63 seconds
Started Jul 30 06:38:09 PM PDT 24
Finished Jul 30 06:38:10 PM PDT 24
Peak memory 197344 kb
Host smart-fc402d29-e392-42e8-b76f-0c3b31fcb454
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137019836 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_csr_rw.1137019836
Directory /workspace/12.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.4266656289
Short name T640
Test name
Test status
Simulation time 300288041 ps
CPU time 0.73 seconds
Started Jul 30 06:38:11 PM PDT 24
Finished Jul 30 06:38:12 PM PDT 24
Peak memory 197368 kb
Host smart-c4622f54-d0b9-4e3f-9de8-68e614fc2a5b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266656289 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_s
ame_csr_outstanding.4266656289
Directory /workspace/12.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_tl_errors.1347903589
Short name T639
Test name
Test status
Simulation time 64579426 ps
CPU time 1.38 seconds
Started Jul 30 06:38:10 PM PDT 24
Finished Jul 30 06:38:12 PM PDT 24
Peak memory 196424 kb
Host smart-a3be51a8-193a-4276-a4df-24ea44c61011
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347903589 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_errors.1347903589
Directory /workspace/12.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.3434040960
Short name T80
Test name
Test status
Simulation time 306569203 ps
CPU time 1.13 seconds
Started Jul 30 06:38:21 PM PDT 24
Finished Jul 30 06:38:22 PM PDT 24
Peak memory 195304 kb
Host smart-ebea1e8d-0281-4d3a-8a36-c54f87706674
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434040960 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_intg_er
r.3434040960
Directory /workspace/12.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.3477682552
Short name T731
Test name
Test status
Simulation time 84108029 ps
CPU time 0.77 seconds
Started Jul 30 06:38:09 PM PDT 24
Finished Jul 30 06:38:10 PM PDT 24
Peak memory 200352 kb
Host smart-b5943dc2-9e14-4bff-bb9f-6190ce15dc75
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477682552 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.pwrmgr_csr_mem_rw_with_rand_reset.3477682552
Directory /workspace/13.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_csr_rw.238333637
Short name T109
Test name
Test status
Simulation time 46592625 ps
CPU time 0.65 seconds
Started Jul 30 06:38:13 PM PDT 24
Finished Jul 30 06:38:14 PM PDT 24
Peak memory 197324 kb
Host smart-62e05707-e4a5-4998-b37d-da1d1a4f04ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238333637 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_csr_rw.238333637
Directory /workspace/13.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_intr_test.436914295
Short name T650
Test name
Test status
Simulation time 112285503 ps
CPU time 0.58 seconds
Started Jul 30 06:38:14 PM PDT 24
Finished Jul 30 06:38:14 PM PDT 24
Peak memory 195080 kb
Host smart-aa81ec20-4084-4eed-8605-d729c892dd85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436914295 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_intr_test.436914295
Directory /workspace/13.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.3038831582
Short name T712
Test name
Test status
Simulation time 36052845 ps
CPU time 0.82 seconds
Started Jul 30 06:38:07 PM PDT 24
Finished Jul 30 06:38:07 PM PDT 24
Peak memory 197412 kb
Host smart-94ea6e78-98fa-40d1-945c-395cd1bea70d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038831582 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_s
ame_csr_outstanding.3038831582
Directory /workspace/13.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_tl_errors.2049522933
Short name T665
Test name
Test status
Simulation time 132258402 ps
CPU time 1.3 seconds
Started Jul 30 06:38:11 PM PDT 24
Finished Jul 30 06:38:12 PM PDT 24
Peak memory 200764 kb
Host smart-7d425e43-baf6-4d43-bca3-8cc462d8b691
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049522933 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_errors.2049522933
Directory /workspace/13.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.3037616258
Short name T642
Test name
Test status
Simulation time 127008199 ps
CPU time 1.08 seconds
Started Jul 30 06:38:07 PM PDT 24
Finished Jul 30 06:38:08 PM PDT 24
Peak memory 195272 kb
Host smart-6626d2a8-30a2-47dd-8872-bf3ee0e087d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037616258 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_intg_er
r.3037616258
Directory /workspace/13.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.1899937156
Short name T687
Test name
Test status
Simulation time 42588162 ps
CPU time 0.88 seconds
Started Jul 30 06:38:10 PM PDT 24
Finished Jul 30 06:38:11 PM PDT 24
Peak memory 195256 kb
Host smart-272f66d8-e198-48ae-ba59-4fb1e3b2e037
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899937156 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.pwrmgr_csr_mem_rw_with_rand_reset.1899937156
Directory /workspace/14.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_csr_rw.962805347
Short name T643
Test name
Test status
Simulation time 26060573 ps
CPU time 0.64 seconds
Started Jul 30 06:38:08 PM PDT 24
Finished Jul 30 06:38:09 PM PDT 24
Peak memory 197276 kb
Host smart-58e80fec-00b2-4a10-ab97-a566ca9960b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962805347 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_csr_rw.962805347
Directory /workspace/14.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_intr_test.4169678185
Short name T73
Test name
Test status
Simulation time 18673499 ps
CPU time 0.64 seconds
Started Jul 30 06:38:09 PM PDT 24
Finished Jul 30 06:38:10 PM PDT 24
Peak memory 195104 kb
Host smart-251b39fb-1a35-42cb-84bc-deeda1607efd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169678185 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_intr_test.4169678185
Directory /workspace/14.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.443443522
Short name T63
Test name
Test status
Simulation time 52146107 ps
CPU time 0.74 seconds
Started Jul 30 06:38:08 PM PDT 24
Finished Jul 30 06:38:09 PM PDT 24
Peak memory 195120 kb
Host smart-0fd7e59c-b5d8-4e15-b5a3-ea0d31754e24
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443443522 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sa
me_csr_outstanding.443443522
Directory /workspace/14.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.1393529027
Short name T718
Test name
Test status
Simulation time 72977435 ps
CPU time 0.92 seconds
Started Jul 30 06:38:10 PM PDT 24
Finished Jul 30 06:38:11 PM PDT 24
Peak memory 200604 kb
Host smart-79eb47c6-d132-495b-a1b5-82a41e205551
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393529027 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.pwrmgr_csr_mem_rw_with_rand_reset.1393529027
Directory /workspace/15.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_csr_rw.1406534917
Short name T703
Test name
Test status
Simulation time 20210199 ps
CPU time 0.66 seconds
Started Jul 30 06:38:15 PM PDT 24
Finished Jul 30 06:38:16 PM PDT 24
Peak memory 197540 kb
Host smart-be6e3d32-8dd3-4f08-8b5e-ef7f19e7cab1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406534917 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_csr_rw.1406534917
Directory /workspace/15.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_intr_test.706495612
Short name T654
Test name
Test status
Simulation time 33049926 ps
CPU time 0.63 seconds
Started Jul 30 06:38:18 PM PDT 24
Finished Jul 30 06:38:18 PM PDT 24
Peak memory 195052 kb
Host smart-a987a259-65ed-4a8c-a80c-0c71e1bc8b05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706495612 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_intr_test.706495612
Directory /workspace/15.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.2710844434
Short name T649
Test name
Test status
Simulation time 64478823 ps
CPU time 0.85 seconds
Started Jul 30 06:38:24 PM PDT 24
Finished Jul 30 06:38:25 PM PDT 24
Peak memory 198396 kb
Host smart-05bdb2a8-259d-4c82-a222-08277721940e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710844434 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_s
ame_csr_outstanding.2710844434
Directory /workspace/15.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_tl_errors.3368905626
Short name T723
Test name
Test status
Simulation time 103308949 ps
CPU time 2.32 seconds
Started Jul 30 06:38:14 PM PDT 24
Finished Jul 30 06:38:16 PM PDT 24
Peak memory 197500 kb
Host smart-6573dcdc-8569-419a-8ea9-2e19c810fc8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368905626 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_errors.3368905626
Directory /workspace/15.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.3828890794
Short name T79
Test name
Test status
Simulation time 111680363 ps
CPU time 1.13 seconds
Started Jul 30 06:38:15 PM PDT 24
Finished Jul 30 06:38:17 PM PDT 24
Peak memory 200436 kb
Host smart-5f444a32-1909-4f14-9a94-3db6b1fd8c3a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828890794 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_intg_er
r.3828890794
Directory /workspace/15.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.955030694
Short name T77
Test name
Test status
Simulation time 59886102 ps
CPU time 0.86 seconds
Started Jul 30 06:38:15 PM PDT 24
Finished Jul 30 06:38:16 PM PDT 24
Peak memory 195292 kb
Host smart-7a68ebf6-83c8-4c99-968f-9341545a3601
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955030694 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.pwrmgr_csr_mem_rw_with_rand_reset.955030694
Directory /workspace/16.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_csr_rw.3521976828
Short name T99
Test name
Test status
Simulation time 20521178 ps
CPU time 0.65 seconds
Started Jul 30 06:38:11 PM PDT 24
Finished Jul 30 06:38:12 PM PDT 24
Peak memory 195144 kb
Host smart-5f9e1083-3ded-4229-aca9-7b9000260e1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521976828 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_csr_rw.3521976828
Directory /workspace/16.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_intr_test.3445047265
Short name T658
Test name
Test status
Simulation time 18659387 ps
CPU time 0.66 seconds
Started Jul 30 06:38:36 PM PDT 24
Finished Jul 30 06:38:37 PM PDT 24
Peak memory 195068 kb
Host smart-c6c87848-ccc4-4360-bbe7-acf62ab10432
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445047265 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_intr_test.3445047265
Directory /workspace/16.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.1060846229
Short name T116
Test name
Test status
Simulation time 170639356 ps
CPU time 0.92 seconds
Started Jul 30 06:38:12 PM PDT 24
Finished Jul 30 06:38:13 PM PDT 24
Peak memory 195112 kb
Host smart-a11d0f6e-a401-44ec-9209-8ecdda72119e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060846229 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_s
ame_csr_outstanding.1060846229
Directory /workspace/16.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_tl_errors.2372092366
Short name T675
Test name
Test status
Simulation time 31399972 ps
CPU time 1.35 seconds
Started Jul 30 06:38:11 PM PDT 24
Finished Jul 30 06:38:13 PM PDT 24
Peak memory 195496 kb
Host smart-7635fb99-0971-48cb-8716-cae9df577245
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372092366 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_errors.2372092366
Directory /workspace/16.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.3075204650
Short name T710
Test name
Test status
Simulation time 109457239 ps
CPU time 1.11 seconds
Started Jul 30 06:38:12 PM PDT 24
Finished Jul 30 06:38:14 PM PDT 24
Peak memory 200672 kb
Host smart-4959e4bb-1d13-472e-ac5d-3e57415a463b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075204650 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_intg_er
r.3075204650
Directory /workspace/16.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.886739639
Short name T648
Test name
Test status
Simulation time 57420329 ps
CPU time 1.41 seconds
Started Jul 30 06:38:12 PM PDT 24
Finished Jul 30 06:38:14 PM PDT 24
Peak memory 198784 kb
Host smart-019277cc-0693-47ea-a2a1-8b15b513a203
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886739639 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.pwrmgr_csr_mem_rw_with_rand_reset.886739639
Directory /workspace/17.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_csr_rw.386266856
Short name T103
Test name
Test status
Simulation time 39172796 ps
CPU time 0.62 seconds
Started Jul 30 06:38:17 PM PDT 24
Finished Jul 30 06:38:18 PM PDT 24
Peak memory 195152 kb
Host smart-67732e0d-6554-441b-97e5-a8b2f067e9d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386266856 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_csr_rw.386266856
Directory /workspace/17.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_intr_test.1662414555
Short name T686
Test name
Test status
Simulation time 21293329 ps
CPU time 0.62 seconds
Started Jul 30 06:38:42 PM PDT 24
Finished Jul 30 06:38:43 PM PDT 24
Peak memory 195044 kb
Host smart-8ca3a96f-a619-4031-aeb1-d463e978cec8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662414555 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_intr_test.1662414555
Directory /workspace/17.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.3321921929
Short name T117
Test name
Test status
Simulation time 53474473 ps
CPU time 0.78 seconds
Started Jul 30 06:38:30 PM PDT 24
Finished Jul 30 06:38:31 PM PDT 24
Peak memory 195180 kb
Host smart-ace051cf-e12f-40e8-9d67-a2323bae3011
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321921929 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_s
ame_csr_outstanding.3321921929
Directory /workspace/17.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_tl_errors.2248403052
Short name T701
Test name
Test status
Simulation time 77056569 ps
CPU time 1.13 seconds
Started Jul 30 06:38:12 PM PDT 24
Finished Jul 30 06:38:13 PM PDT 24
Peak memory 196264 kb
Host smart-b26e3dc9-d4bd-4264-b917-cc0620674cb3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248403052 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_errors.2248403052
Directory /workspace/17.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.1662204867
Short name T57
Test name
Test status
Simulation time 189092403 ps
CPU time 0.99 seconds
Started Jul 30 06:38:12 PM PDT 24
Finished Jul 30 06:38:14 PM PDT 24
Peak memory 200172 kb
Host smart-9872e639-f0f0-4138-98f0-74f2fe4a84f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662204867 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_intg_er
r.1662204867
Directory /workspace/17.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.1463645156
Short name T693
Test name
Test status
Simulation time 120870727 ps
CPU time 0.93 seconds
Started Jul 30 06:38:14 PM PDT 24
Finished Jul 30 06:38:15 PM PDT 24
Peak memory 200588 kb
Host smart-3663e733-1088-4193-a508-f2fb952a9552
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463645156 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.pwrmgr_csr_mem_rw_with_rand_reset.1463645156
Directory /workspace/18.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_intr_test.415468871
Short name T646
Test name
Test status
Simulation time 18819272 ps
CPU time 0.66 seconds
Started Jul 30 06:38:36 PM PDT 24
Finished Jul 30 06:38:37 PM PDT 24
Peak memory 195116 kb
Host smart-ba71b07c-4a94-40bc-9ff8-8284f6ef385d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415468871 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_intr_test.415468871
Directory /workspace/18.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.4185913236
Short name T677
Test name
Test status
Simulation time 271934863 ps
CPU time 0.94 seconds
Started Jul 30 06:38:25 PM PDT 24
Finished Jul 30 06:38:26 PM PDT 24
Peak memory 195196 kb
Host smart-f37c9c59-f1a3-4ce7-9d74-fe5958a5f440
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185913236 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_s
ame_csr_outstanding.4185913236
Directory /workspace/18.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_tl_errors.1984857955
Short name T673
Test name
Test status
Simulation time 64089674 ps
CPU time 1.57 seconds
Started Jul 30 06:38:10 PM PDT 24
Finished Jul 30 06:38:12 PM PDT 24
Peak memory 196424 kb
Host smart-8c53a6b8-ba8d-4ac5-8a9c-ea733263e47a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984857955 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_errors.1984857955
Directory /workspace/18.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.2188734992
Short name T638
Test name
Test status
Simulation time 157082925 ps
CPU time 0.85 seconds
Started Jul 30 06:38:14 PM PDT 24
Finished Jul 30 06:38:15 PM PDT 24
Peak memory 195240 kb
Host smart-2439849b-cac0-4088-915f-355da1da6d1e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188734992 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.pwrmgr_csr_mem_rw_with_rand_reset.2188734992
Directory /workspace/19.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_csr_rw.1672054586
Short name T105
Test name
Test status
Simulation time 17486943 ps
CPU time 0.63 seconds
Started Jul 30 06:38:46 PM PDT 24
Finished Jul 30 06:38:46 PM PDT 24
Peak memory 197292 kb
Host smart-f4bdca2e-37bb-4a8a-95f1-b95cf7ca3dc8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672054586 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_csr_rw.1672054586
Directory /workspace/19.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_intr_test.4221309208
Short name T733
Test name
Test status
Simulation time 18137866 ps
CPU time 0.7 seconds
Started Jul 30 06:38:15 PM PDT 24
Finished Jul 30 06:38:16 PM PDT 24
Peak memory 195028 kb
Host smart-2a838c54-4b3b-49a5-a441-013de2b1f66a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221309208 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_intr_test.4221309208
Directory /workspace/19.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.3872940128
Short name T645
Test name
Test status
Simulation time 34857959 ps
CPU time 0.76 seconds
Started Jul 30 06:38:36 PM PDT 24
Finished Jul 30 06:38:37 PM PDT 24
Peak memory 197384 kb
Host smart-ca303527-c6c7-42eb-b927-9569c51902bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872940128 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_s
ame_csr_outstanding.3872940128
Directory /workspace/19.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_tl_errors.3357731300
Short name T68
Test name
Test status
Simulation time 275376673 ps
CPU time 1.7 seconds
Started Jul 30 06:38:14 PM PDT 24
Finished Jul 30 06:38:16 PM PDT 24
Peak memory 195544 kb
Host smart-edc29881-e9f7-4465-8e86-aa644b6c684c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357731300 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_errors.3357731300
Directory /workspace/19.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.4288984495
Short name T666
Test name
Test status
Simulation time 111715100 ps
CPU time 1.16 seconds
Started Jul 30 06:38:27 PM PDT 24
Finished Jul 30 06:38:28 PM PDT 24
Peak memory 200636 kb
Host smart-05483509-0729-4d0e-9d24-8b072021e080
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288984495 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_intg_er
r.4288984495
Directory /workspace/19.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.3195407458
Short name T114
Test name
Test status
Simulation time 97282189 ps
CPU time 0.79 seconds
Started Jul 30 06:37:55 PM PDT 24
Finished Jul 30 06:37:56 PM PDT 24
Peak memory 195072 kb
Host smart-bf6aca65-1f9f-415a-b9cd-7a503987f787
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195407458 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_aliasing.3
195407458
Directory /workspace/2.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.2320805471
Short name T692
Test name
Test status
Simulation time 1061801823 ps
CPU time 3.57 seconds
Started Jul 30 06:38:00 PM PDT 24
Finished Jul 30 06:38:04 PM PDT 24
Peak memory 195264 kb
Host smart-666fc9b8-8e2a-44c2-85fa-a003bf7b10ca
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320805471 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_bit_bash.2
320805471
Directory /workspace/2.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.1449739393
Short name T715
Test name
Test status
Simulation time 39830987 ps
CPU time 0.64 seconds
Started Jul 30 06:37:59 PM PDT 24
Finished Jul 30 06:37:59 PM PDT 24
Peak memory 195144 kb
Host smart-7e049f07-8229-4fb8-8ec0-d214f988956b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449739393 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_hw_reset.1
449739393
Directory /workspace/2.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.96060020
Short name T671
Test name
Test status
Simulation time 50570253 ps
CPU time 0.75 seconds
Started Jul 30 06:38:08 PM PDT 24
Finished Jul 30 06:38:09 PM PDT 24
Peak memory 195292 kb
Host smart-1e519117-edd5-427e-b5a0-7545184cfb08
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96060020 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.pwrmgr_csr_mem_rw_with_rand_reset.96060020
Directory /workspace/2.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_rw.3173129305
Short name T106
Test name
Test status
Simulation time 20171724 ps
CPU time 0.61 seconds
Started Jul 30 06:38:04 PM PDT 24
Finished Jul 30 06:38:05 PM PDT 24
Peak memory 195120 kb
Host smart-808d676b-5aba-4f97-8e7b-5a5a39dadd8e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173129305 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_rw.3173129305
Directory /workspace/2.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_intr_test.1944892525
Short name T717
Test name
Test status
Simulation time 20940256 ps
CPU time 0.66 seconds
Started Jul 30 06:38:12 PM PDT 24
Finished Jul 30 06:38:13 PM PDT 24
Peak memory 195076 kb
Host smart-744cf2d1-f247-4931-812e-ece1499de27f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944892525 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_intr_test.1944892525
Directory /workspace/2.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.2155177057
Short name T64
Test name
Test status
Simulation time 27885848 ps
CPU time 0.77 seconds
Started Jul 30 06:38:02 PM PDT 24
Finished Jul 30 06:38:03 PM PDT 24
Peak memory 197600 kb
Host smart-5e0b6d4d-4e48-4dc7-9593-8cc141af3317
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155177057 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sa
me_csr_outstanding.2155177057
Directory /workspace/2.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_tl_errors.2525179905
Short name T660
Test name
Test status
Simulation time 114895264 ps
CPU time 1.27 seconds
Started Jul 30 06:38:05 PM PDT 24
Finished Jul 30 06:38:07 PM PDT 24
Peak memory 196540 kb
Host smart-85abe893-6aec-46d2-8f25-0bfa3203144f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525179905 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_errors.2525179905
Directory /workspace/2.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.3915772232
Short name T143
Test name
Test status
Simulation time 96249678 ps
CPU time 1.05 seconds
Started Jul 30 06:37:58 PM PDT 24
Finished Jul 30 06:37:59 PM PDT 24
Peak memory 195132 kb
Host smart-9a2660ff-1bc9-45e3-9d4a-9a80a7b831d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915772232 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_intg_err
.3915772232
Directory /workspace/2.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.pwrmgr_intr_test.2654160135
Short name T644
Test name
Test status
Simulation time 19312249 ps
CPU time 0.63 seconds
Started Jul 30 06:38:14 PM PDT 24
Finished Jul 30 06:38:15 PM PDT 24
Peak memory 195092 kb
Host smart-a0247002-02e9-41b9-931f-cdbe1df613df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654160135 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.pwrmgr_intr_test.2654160135
Directory /workspace/20.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.pwrmgr_intr_test.275121702
Short name T631
Test name
Test status
Simulation time 19952667 ps
CPU time 0.64 seconds
Started Jul 30 06:38:14 PM PDT 24
Finished Jul 30 06:38:15 PM PDT 24
Peak memory 195040 kb
Host smart-61d43cdb-d7d0-4a0e-87e6-906cae433a47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275121702 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.pwrmgr_intr_test.275121702
Directory /workspace/21.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.pwrmgr_intr_test.1117789338
Short name T667
Test name
Test status
Simulation time 108739672 ps
CPU time 0.62 seconds
Started Jul 30 06:38:18 PM PDT 24
Finished Jul 30 06:38:18 PM PDT 24
Peak memory 195084 kb
Host smart-ba3985f0-1dbb-42bd-8518-045253efc314
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117789338 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.pwrmgr_intr_test.1117789338
Directory /workspace/22.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.pwrmgr_intr_test.3383930772
Short name T157
Test name
Test status
Simulation time 37874339 ps
CPU time 0.58 seconds
Started Jul 30 06:38:48 PM PDT 24
Finished Jul 30 06:38:49 PM PDT 24
Peak memory 195044 kb
Host smart-d835edf6-5bd8-4b06-b82f-a78e442631ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383930772 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.pwrmgr_intr_test.3383930772
Directory /workspace/23.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.pwrmgr_intr_test.443627902
Short name T672
Test name
Test status
Simulation time 51857506 ps
CPU time 0.6 seconds
Started Jul 30 06:38:41 PM PDT 24
Finished Jul 30 06:38:42 PM PDT 24
Peak memory 195116 kb
Host smart-3b2442be-4aa4-4153-8e9f-63b762c739b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443627902 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.pwrmgr_intr_test.443627902
Directory /workspace/24.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.pwrmgr_intr_test.1182647093
Short name T704
Test name
Test status
Simulation time 16799428 ps
CPU time 0.61 seconds
Started Jul 30 06:38:19 PM PDT 24
Finished Jul 30 06:38:19 PM PDT 24
Peak memory 195120 kb
Host smart-b88d081b-34aa-4c70-8f52-502b247ec1dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182647093 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.pwrmgr_intr_test.1182647093
Directory /workspace/25.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.pwrmgr_intr_test.3346022899
Short name T651
Test name
Test status
Simulation time 19175191 ps
CPU time 0.61 seconds
Started Jul 30 06:38:17 PM PDT 24
Finished Jul 30 06:38:18 PM PDT 24
Peak memory 195104 kb
Host smart-bd8579ef-68d1-48aa-bc4b-c37076db1ce6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346022899 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.pwrmgr_intr_test.3346022899
Directory /workspace/26.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.pwrmgr_intr_test.2073235837
Short name T637
Test name
Test status
Simulation time 52054266 ps
CPU time 0.68 seconds
Started Jul 30 06:38:45 PM PDT 24
Finished Jul 30 06:38:46 PM PDT 24
Peak memory 195076 kb
Host smart-24a55467-3ac7-4076-9232-8600363b9137
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073235837 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.pwrmgr_intr_test.2073235837
Directory /workspace/27.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.pwrmgr_intr_test.3383866564
Short name T634
Test name
Test status
Simulation time 45328105 ps
CPU time 0.58 seconds
Started Jul 30 06:38:17 PM PDT 24
Finished Jul 30 06:38:18 PM PDT 24
Peak memory 195072 kb
Host smart-f0be64bf-63c0-45c2-bbc3-cd296694436f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383866564 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.pwrmgr_intr_test.3383866564
Directory /workspace/28.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.pwrmgr_intr_test.437806759
Short name T700
Test name
Test status
Simulation time 16723060 ps
CPU time 0.64 seconds
Started Jul 30 06:38:31 PM PDT 24
Finished Jul 30 06:38:32 PM PDT 24
Peak memory 195124 kb
Host smart-355c9c65-ed4c-4185-bfc9-e7bc62879f36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437806759 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.pwrmgr_intr_test.437806759
Directory /workspace/29.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.2832157375
Short name T111
Test name
Test status
Simulation time 32539630 ps
CPU time 0.86 seconds
Started Jul 30 06:38:02 PM PDT 24
Finished Jul 30 06:38:03 PM PDT 24
Peak memory 197396 kb
Host smart-a627be98-f138-4f97-863d-85cd39c8f379
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832157375 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_aliasing.2
832157375
Directory /workspace/3.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.2464146339
Short name T690
Test name
Test status
Simulation time 271090480 ps
CPU time 2.81 seconds
Started Jul 30 06:38:13 PM PDT 24
Finished Jul 30 06:38:16 PM PDT 24
Peak memory 195324 kb
Host smart-7bf38ed5-6cd9-42ea-91c2-8f7dff78ebed
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464146339 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_bit_bash.2
464146339
Directory /workspace/3.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.3143398511
Short name T636
Test name
Test status
Simulation time 46036971 ps
CPU time 0.65 seconds
Started Jul 30 06:38:00 PM PDT 24
Finished Jul 30 06:38:01 PM PDT 24
Peak memory 198360 kb
Host smart-375b5170-e04b-4c41-9740-f9eb20b5efa8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143398511 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_hw_reset.3
143398511
Directory /workspace/3.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.2338628759
Short name T127
Test name
Test status
Simulation time 40228389 ps
CPU time 0.82 seconds
Started Jul 30 06:38:06 PM PDT 24
Finished Jul 30 06:38:07 PM PDT 24
Peak memory 195264 kb
Host smart-02b896c4-e4e7-44cd-ba84-02728536d913
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338628759 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.pwrmgr_csr_mem_rw_with_rand_reset.2338628759
Directory /workspace/3.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_rw.1807628495
Short name T676
Test name
Test status
Simulation time 40193630 ps
CPU time 0.64 seconds
Started Jul 30 06:38:00 PM PDT 24
Finished Jul 30 06:38:00 PM PDT 24
Peak memory 195168 kb
Host smart-f6ce5757-351b-42f8-bd69-1aa4e5e4721b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807628495 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_rw.1807628495
Directory /workspace/3.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_intr_test.673781752
Short name T721
Test name
Test status
Simulation time 20192220 ps
CPU time 0.61 seconds
Started Jul 30 06:37:57 PM PDT 24
Finished Jul 30 06:37:58 PM PDT 24
Peak memory 195060 kb
Host smart-4553be7f-3bc0-4f25-8549-5a7010fac269
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673781752 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_intr_test.673781752
Directory /workspace/3.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.3050302674
Short name T697
Test name
Test status
Simulation time 42405828 ps
CPU time 0.9 seconds
Started Jul 30 06:38:09 PM PDT 24
Finished Jul 30 06:38:10 PM PDT 24
Peak memory 198408 kb
Host smart-de8fb3da-a425-4e18-973d-5211d31cfe22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050302674 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sa
me_csr_outstanding.3050302674
Directory /workspace/3.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_tl_errors.3651260294
Short name T663
Test name
Test status
Simulation time 38460475 ps
CPU time 1.04 seconds
Started Jul 30 06:37:56 PM PDT 24
Finished Jul 30 06:37:57 PM PDT 24
Peak memory 196216 kb
Host smart-1bf911c0-0a98-46c0-ab6a-2bc1ed564a0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651260294 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_errors.3651260294
Directory /workspace/3.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.1189752939
Short name T22
Test name
Test status
Simulation time 237087394 ps
CPU time 1.18 seconds
Started Jul 30 06:38:01 PM PDT 24
Finished Jul 30 06:38:03 PM PDT 24
Peak memory 200468 kb
Host smart-12ad67db-8243-437c-88d3-3d18eba9a4a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189752939 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_intg_err
.1189752939
Directory /workspace/3.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.pwrmgr_intr_test.1685776712
Short name T669
Test name
Test status
Simulation time 67692905 ps
CPU time 0.62 seconds
Started Jul 30 06:38:18 PM PDT 24
Finished Jul 30 06:38:19 PM PDT 24
Peak memory 195076 kb
Host smart-fe31acfe-7d85-4e7f-9169-7f5fedf7c578
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685776712 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.pwrmgr_intr_test.1685776712
Directory /workspace/30.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.pwrmgr_intr_test.178212086
Short name T629
Test name
Test status
Simulation time 18717690 ps
CPU time 0.62 seconds
Started Jul 30 06:38:25 PM PDT 24
Finished Jul 30 06:38:25 PM PDT 24
Peak memory 195056 kb
Host smart-b8d9894f-d19c-4bca-9ba1-cc3adcb34f93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178212086 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.pwrmgr_intr_test.178212086
Directory /workspace/31.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.pwrmgr_intr_test.3705329071
Short name T158
Test name
Test status
Simulation time 25963291 ps
CPU time 0.65 seconds
Started Jul 30 06:38:46 PM PDT 24
Finished Jul 30 06:38:47 PM PDT 24
Peak memory 195084 kb
Host smart-9713b855-ca26-4e6a-8756-30ec3cb8961d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705329071 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.pwrmgr_intr_test.3705329071
Directory /workspace/32.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.pwrmgr_intr_test.4119609638
Short name T678
Test name
Test status
Simulation time 45304019 ps
CPU time 0.58 seconds
Started Jul 30 06:38:54 PM PDT 24
Finished Jul 30 06:38:55 PM PDT 24
Peak memory 194928 kb
Host smart-c8a87993-7d87-4f44-bb81-62c82c018920
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119609638 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.pwrmgr_intr_test.4119609638
Directory /workspace/33.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.pwrmgr_intr_test.1660791827
Short name T699
Test name
Test status
Simulation time 45003465 ps
CPU time 0.61 seconds
Started Jul 30 06:38:44 PM PDT 24
Finished Jul 30 06:38:44 PM PDT 24
Peak memory 195116 kb
Host smart-a82c6c9a-c6db-4f39-ad33-765fc7d0295d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660791827 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.pwrmgr_intr_test.1660791827
Directory /workspace/34.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.pwrmgr_intr_test.2071450485
Short name T716
Test name
Test status
Simulation time 52822646 ps
CPU time 0.62 seconds
Started Jul 30 06:38:22 PM PDT 24
Finished Jul 30 06:38:22 PM PDT 24
Peak memory 195032 kb
Host smart-9a825f25-c757-4b5d-b54d-190f7d4ea7f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071450485 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.pwrmgr_intr_test.2071450485
Directory /workspace/35.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.pwrmgr_intr_test.2508344955
Short name T682
Test name
Test status
Simulation time 55840692 ps
CPU time 0.64 seconds
Started Jul 30 06:38:42 PM PDT 24
Finished Jul 30 06:38:43 PM PDT 24
Peak memory 195072 kb
Host smart-1504cb6b-73d3-45a6-b7aa-415e858e72b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508344955 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.pwrmgr_intr_test.2508344955
Directory /workspace/36.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.pwrmgr_intr_test.3602743775
Short name T732
Test name
Test status
Simulation time 21428236 ps
CPU time 0.62 seconds
Started Jul 30 06:38:32 PM PDT 24
Finished Jul 30 06:38:33 PM PDT 24
Peak memory 195068 kb
Host smart-9e64bb61-9d77-459b-9195-0403a3ecec36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602743775 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.pwrmgr_intr_test.3602743775
Directory /workspace/37.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.pwrmgr_intr_test.2538481756
Short name T706
Test name
Test status
Simulation time 49737627 ps
CPU time 0.6 seconds
Started Jul 30 06:38:24 PM PDT 24
Finished Jul 30 06:38:24 PM PDT 24
Peak memory 195096 kb
Host smart-033d1966-e3f9-47f6-91e6-9e4121aff00c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538481756 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.pwrmgr_intr_test.2538481756
Directory /workspace/38.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.pwrmgr_intr_test.1287509654
Short name T684
Test name
Test status
Simulation time 20638631 ps
CPU time 0.6 seconds
Started Jul 30 06:38:25 PM PDT 24
Finished Jul 30 06:38:26 PM PDT 24
Peak memory 195248 kb
Host smart-de4992d3-bb51-4ea4-b14e-0780d394135e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287509654 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.pwrmgr_intr_test.1287509654
Directory /workspace/39.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.1883924287
Short name T100
Test name
Test status
Simulation time 27935180 ps
CPU time 0.77 seconds
Started Jul 30 06:37:57 PM PDT 24
Finished Jul 30 06:37:57 PM PDT 24
Peak memory 195100 kb
Host smart-1a849022-fd9b-4909-a0dc-8adac547009b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883924287 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_aliasing.1
883924287
Directory /workspace/4.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.347913387
Short name T685
Test name
Test status
Simulation time 649138328 ps
CPU time 1.99 seconds
Started Jul 30 06:37:56 PM PDT 24
Finished Jul 30 06:37:58 PM PDT 24
Peak memory 195276 kb
Host smart-69869509-bb72-400d-bda4-c191d36648ea
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347913387 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_bit_bash.347913387
Directory /workspace/4.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.3897546889
Short name T647
Test name
Test status
Simulation time 35615005 ps
CPU time 0.71 seconds
Started Jul 30 06:37:58 PM PDT 24
Finished Jul 30 06:37:59 PM PDT 24
Peak memory 198292 kb
Host smart-916a39e5-78aa-4728-b983-8c9bc9733eb6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897546889 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_hw_reset.3
897546889
Directory /workspace/4.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.2226745409
Short name T59
Test name
Test status
Simulation time 70493769 ps
CPU time 0.79 seconds
Started Jul 30 06:37:58 PM PDT 24
Finished Jul 30 06:37:59 PM PDT 24
Peak memory 200564 kb
Host smart-2ae0c719-2170-40f6-a36a-95d1146a1005
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226745409 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.pwrmgr_csr_mem_rw_with_rand_reset.2226745409
Directory /workspace/4.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_rw.2856154762
Short name T110
Test name
Test status
Simulation time 18317114 ps
CPU time 0.72 seconds
Started Jul 30 06:38:06 PM PDT 24
Finished Jul 30 06:38:06 PM PDT 24
Peak memory 195136 kb
Host smart-920f7505-61c9-4a77-b833-3f1647a0c7a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856154762 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_rw.2856154762
Directory /workspace/4.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_intr_test.3527359128
Short name T656
Test name
Test status
Simulation time 22139751 ps
CPU time 0.62 seconds
Started Jul 30 06:37:57 PM PDT 24
Finished Jul 30 06:37:58 PM PDT 24
Peak memory 195096 kb
Host smart-a6eb0646-db7d-42a4-b6af-b5aa7071ffab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527359128 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_intr_test.3527359128
Directory /workspace/4.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.2104948845
Short name T122
Test name
Test status
Simulation time 28352360 ps
CPU time 0.76 seconds
Started Jul 30 06:37:59 PM PDT 24
Finished Jul 30 06:38:00 PM PDT 24
Peak memory 195232 kb
Host smart-d6540ded-b658-4cb5-b0dc-5f5e4164e3dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104948845 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sa
me_csr_outstanding.2104948845
Directory /workspace/4.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_tl_errors.207428548
Short name T726
Test name
Test status
Simulation time 382269272 ps
CPU time 1.27 seconds
Started Jul 30 06:38:12 PM PDT 24
Finished Jul 30 06:38:14 PM PDT 24
Peak memory 195512 kb
Host smart-6cc29f3d-275c-4880-87f5-fc879019eccc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207428548 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_errors.207428548
Directory /workspace/4.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.369950151
Short name T76
Test name
Test status
Simulation time 177708144 ps
CPU time 1.63 seconds
Started Jul 30 06:38:10 PM PDT 24
Finished Jul 30 06:38:12 PM PDT 24
Peak memory 195400 kb
Host smart-e1507c7d-35dc-4ea9-b6dd-22ff82d348d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369950151 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_intg_err.
369950151
Directory /workspace/4.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.pwrmgr_intr_test.172121250
Short name T729
Test name
Test status
Simulation time 44824728 ps
CPU time 0.6 seconds
Started Jul 30 06:38:25 PM PDT 24
Finished Jul 30 06:38:26 PM PDT 24
Peak memory 195248 kb
Host smart-a8828a0a-ebd7-4aad-bb19-da6968b02419
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172121250 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.pwrmgr_intr_test.172121250
Directory /workspace/40.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.pwrmgr_intr_test.1578126534
Short name T708
Test name
Test status
Simulation time 35205142 ps
CPU time 0.61 seconds
Started Jul 30 06:38:25 PM PDT 24
Finished Jul 30 06:38:26 PM PDT 24
Peak memory 195252 kb
Host smart-a5359a0f-7433-4d71-990a-cbc01c44d4fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578126534 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.pwrmgr_intr_test.1578126534
Directory /workspace/41.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.pwrmgr_intr_test.127145947
Short name T707
Test name
Test status
Simulation time 23713502 ps
CPU time 0.61 seconds
Started Jul 30 06:38:36 PM PDT 24
Finished Jul 30 06:38:37 PM PDT 24
Peak memory 195076 kb
Host smart-253f98f9-cc48-4328-9777-b3d05012c9ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127145947 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.pwrmgr_intr_test.127145947
Directory /workspace/42.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.pwrmgr_intr_test.2884796031
Short name T702
Test name
Test status
Simulation time 18835639 ps
CPU time 0.61 seconds
Started Jul 30 06:38:30 PM PDT 24
Finished Jul 30 06:38:31 PM PDT 24
Peak memory 195072 kb
Host smart-f2bca271-f7ae-4c57-b6bf-976c3f97efbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884796031 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.pwrmgr_intr_test.2884796031
Directory /workspace/43.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.pwrmgr_intr_test.2326003904
Short name T680
Test name
Test status
Simulation time 30755096 ps
CPU time 0.64 seconds
Started Jul 30 06:38:27 PM PDT 24
Finished Jul 30 06:38:28 PM PDT 24
Peak memory 195040 kb
Host smart-5b62765c-6082-46e1-b9fa-ec446feb00ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326003904 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.pwrmgr_intr_test.2326003904
Directory /workspace/44.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.pwrmgr_intr_test.2537602250
Short name T668
Test name
Test status
Simulation time 44696483 ps
CPU time 0.62 seconds
Started Jul 30 06:38:23 PM PDT 24
Finished Jul 30 06:38:24 PM PDT 24
Peak memory 195068 kb
Host smart-2f80c01c-ec9e-4e97-a4a3-7a68a6d94b21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537602250 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.pwrmgr_intr_test.2537602250
Directory /workspace/45.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.pwrmgr_intr_test.3541959123
Short name T71
Test name
Test status
Simulation time 47283034 ps
CPU time 0.66 seconds
Started Jul 30 06:38:33 PM PDT 24
Finished Jul 30 06:38:34 PM PDT 24
Peak memory 195076 kb
Host smart-4b5ce283-4c49-465b-a19b-d7013b4c20c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541959123 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.pwrmgr_intr_test.3541959123
Directory /workspace/46.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.pwrmgr_intr_test.1140069889
Short name T725
Test name
Test status
Simulation time 20605482 ps
CPU time 0.6 seconds
Started Jul 30 06:38:23 PM PDT 24
Finished Jul 30 06:38:23 PM PDT 24
Peak memory 195100 kb
Host smart-cddb86fc-6320-4c19-a810-4e6ba2c88dc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140069889 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.pwrmgr_intr_test.1140069889
Directory /workspace/47.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.pwrmgr_intr_test.1777463005
Short name T681
Test name
Test status
Simulation time 21679371 ps
CPU time 0.67 seconds
Started Jul 30 06:38:25 PM PDT 24
Finished Jul 30 06:38:26 PM PDT 24
Peak memory 195052 kb
Host smart-7308642f-b91f-49d2-b60d-99250a1027db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777463005 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.pwrmgr_intr_test.1777463005
Directory /workspace/49.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.1530253031
Short name T24
Test name
Test status
Simulation time 55563997 ps
CPU time 1.02 seconds
Started Jul 30 06:37:59 PM PDT 24
Finished Jul 30 06:38:00 PM PDT 24
Peak memory 196252 kb
Host smart-2cb176f9-fcd2-4c4a-bbf3-221dec68be7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530253031 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.pwrmgr_csr_mem_rw_with_rand_reset.1530253031
Directory /workspace/5.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_csr_rw.781148804
Short name T728
Test name
Test status
Simulation time 20129000 ps
CPU time 0.6 seconds
Started Jul 30 06:38:01 PM PDT 24
Finished Jul 30 06:38:01 PM PDT 24
Peak memory 195160 kb
Host smart-2fe7b68f-00d9-46d1-8a7f-e0215fe24a72
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781148804 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_csr_rw.781148804
Directory /workspace/5.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_intr_test.655367512
Short name T160
Test name
Test status
Simulation time 49332065 ps
CPU time 0.6 seconds
Started Jul 30 06:38:14 PM PDT 24
Finished Jul 30 06:38:15 PM PDT 24
Peak memory 195064 kb
Host smart-38a2348d-b6dd-4ff8-8fbb-51cc39a5d7f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655367512 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_intr_test.655367512
Directory /workspace/5.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.2464478233
Short name T696
Test name
Test status
Simulation time 77556151 ps
CPU time 0.74 seconds
Started Jul 30 06:38:01 PM PDT 24
Finished Jul 30 06:38:02 PM PDT 24
Peak memory 195236 kb
Host smart-6ee69bae-aa31-4675-8d47-af6e829456cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464478233 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sa
me_csr_outstanding.2464478233
Directory /workspace/5.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_tl_errors.1970908657
Short name T70
Test name
Test status
Simulation time 289619804 ps
CPU time 2.93 seconds
Started Jul 30 06:38:00 PM PDT 24
Finished Jul 30 06:38:03 PM PDT 24
Peak memory 197448 kb
Host smart-10a25075-1286-4f90-8074-183348d7ad61
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970908657 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_errors.1970908657
Directory /workspace/5.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.644226761
Short name T720
Test name
Test status
Simulation time 308824666 ps
CPU time 1.08 seconds
Started Jul 30 06:37:59 PM PDT 24
Finished Jul 30 06:38:00 PM PDT 24
Peak memory 200720 kb
Host smart-6f90804f-6781-4c90-894e-58734beb58e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644226761 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_intg_err.
644226761
Directory /workspace/5.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.2366040327
Short name T695
Test name
Test status
Simulation time 38143659 ps
CPU time 0.77 seconds
Started Jul 30 06:37:58 PM PDT 24
Finished Jul 30 06:37:59 PM PDT 24
Peak memory 195256 kb
Host smart-8e8d8924-2afb-4dde-a782-fc200c8af131
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366040327 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.pwrmgr_csr_mem_rw_with_rand_reset.2366040327
Directory /workspace/6.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_csr_rw.1171520854
Short name T115
Test name
Test status
Simulation time 20420140 ps
CPU time 0.65 seconds
Started Jul 30 06:37:59 PM PDT 24
Finished Jul 30 06:38:00 PM PDT 24
Peak memory 197260 kb
Host smart-44853e6a-9457-489c-8ba2-4fae64502b8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171520854 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_csr_rw.1171520854
Directory /workspace/6.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_intr_test.3642078454
Short name T705
Test name
Test status
Simulation time 21354473 ps
CPU time 0.61 seconds
Started Jul 30 06:38:11 PM PDT 24
Finished Jul 30 06:38:11 PM PDT 24
Peak memory 195116 kb
Host smart-20915652-4398-498f-8b43-996ff7afc3a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642078454 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_intr_test.3642078454
Directory /workspace/6.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.3469716767
Short name T664
Test name
Test status
Simulation time 46538566 ps
CPU time 0.73 seconds
Started Jul 30 06:38:10 PM PDT 24
Finished Jul 30 06:38:11 PM PDT 24
Peak memory 197408 kb
Host smart-8b6fbd42-cebe-49d3-b41c-47ffd9af76d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469716767 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sa
me_csr_outstanding.3469716767
Directory /workspace/6.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_tl_errors.886642029
Short name T713
Test name
Test status
Simulation time 31888547 ps
CPU time 1.31 seconds
Started Jul 30 06:37:58 PM PDT 24
Finished Jul 30 06:37:59 PM PDT 24
Peak memory 196360 kb
Host smart-c29477f0-3520-4aba-8d70-b432b8322fec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886642029 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_errors.886642029
Directory /workspace/6.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.969248687
Short name T711
Test name
Test status
Simulation time 143989156 ps
CPU time 1.15 seconds
Started Jul 30 06:37:59 PM PDT 24
Finished Jul 30 06:38:00 PM PDT 24
Peak memory 200324 kb
Host smart-281e19c5-70ae-4b20-a6e8-9c013211204e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969248687 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_intg_err.
969248687
Directory /workspace/6.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.2981018531
Short name T670
Test name
Test status
Simulation time 53033120 ps
CPU time 0.91 seconds
Started Jul 30 06:38:00 PM PDT 24
Finished Jul 30 06:38:01 PM PDT 24
Peak memory 195232 kb
Host smart-1f664b20-689f-4d4b-aa1c-ee1d3734330c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981018531 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.pwrmgr_csr_mem_rw_with_rand_reset.2981018531
Directory /workspace/7.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_csr_rw.2080185303
Short name T102
Test name
Test status
Simulation time 85298710 ps
CPU time 0.62 seconds
Started Jul 30 06:38:14 PM PDT 24
Finished Jul 30 06:38:14 PM PDT 24
Peak memory 198300 kb
Host smart-142b2b66-506d-4d78-bb8c-88067d42bd01
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080185303 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_csr_rw.2080185303
Directory /workspace/7.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_intr_test.1246762716
Short name T719
Test name
Test status
Simulation time 123749204 ps
CPU time 0.63 seconds
Started Jul 30 06:38:01 PM PDT 24
Finished Jul 30 06:38:02 PM PDT 24
Peak memory 195044 kb
Host smart-58de5b92-942b-4297-8a80-c04357121c3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246762716 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_intr_test.1246762716
Directory /workspace/7.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.478352895
Short name T119
Test name
Test status
Simulation time 29880833 ps
CPU time 0.79 seconds
Started Jul 30 06:38:11 PM PDT 24
Finished Jul 30 06:38:11 PM PDT 24
Peak memory 195064 kb
Host smart-127339d8-02f3-4972-bf2a-4952080cf4bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478352895 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sam
e_csr_outstanding.478352895
Directory /workspace/7.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_tl_errors.925888952
Short name T727
Test name
Test status
Simulation time 91316408 ps
CPU time 2.07 seconds
Started Jul 30 06:38:02 PM PDT 24
Finished Jul 30 06:38:04 PM PDT 24
Peak memory 196472 kb
Host smart-5c9248f0-f0ce-4e65-a8a1-64bfe2d7b475
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925888952 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_errors.925888952
Directory /workspace/7.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.1568855645
Short name T144
Test name
Test status
Simulation time 252419887 ps
CPU time 1.15 seconds
Started Jul 30 06:38:09 PM PDT 24
Finished Jul 30 06:38:10 PM PDT 24
Peak memory 200664 kb
Host smart-5a001f8e-6126-451e-9a3c-992e6c9e24e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568855645 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_intg_err
.1568855645
Directory /workspace/7.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.2333067832
Short name T641
Test name
Test status
Simulation time 60407821 ps
CPU time 0.67 seconds
Started Jul 30 06:38:12 PM PDT 24
Finished Jul 30 06:38:12 PM PDT 24
Peak memory 195320 kb
Host smart-ba4af1ad-3b5a-4b5d-97b3-b5324beea057
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333067832 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.pwrmgr_csr_mem_rw_with_rand_reset.2333067832
Directory /workspace/8.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_csr_rw.2668302703
Short name T632
Test name
Test status
Simulation time 33382917 ps
CPU time 0.66 seconds
Started Jul 30 06:38:12 PM PDT 24
Finished Jul 30 06:38:13 PM PDT 24
Peak memory 195136 kb
Host smart-4f262355-a355-49bf-a67f-2576f771ee5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668302703 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_csr_rw.2668302703
Directory /workspace/8.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_intr_test.190068897
Short name T722
Test name
Test status
Simulation time 35753742 ps
CPU time 0.6 seconds
Started Jul 30 06:38:00 PM PDT 24
Finished Jul 30 06:38:00 PM PDT 24
Peak memory 195072 kb
Host smart-557f7257-03ff-4f0f-89a0-051d096a1e3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190068897 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_intr_test.190068897
Directory /workspace/8.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.2368884394
Short name T734
Test name
Test status
Simulation time 44557707 ps
CPU time 0.73 seconds
Started Jul 30 06:38:14 PM PDT 24
Finished Jul 30 06:38:15 PM PDT 24
Peak memory 197340 kb
Host smart-eb5e1ce7-74a0-43a3-97ad-597708800fb9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368884394 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sa
me_csr_outstanding.2368884394
Directory /workspace/8.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_tl_errors.3525144721
Short name T659
Test name
Test status
Simulation time 757204884 ps
CPU time 2.19 seconds
Started Jul 30 06:38:11 PM PDT 24
Finished Jul 30 06:38:13 PM PDT 24
Peak memory 196564 kb
Host smart-ab5b27b2-5040-4800-9fab-695921ef93dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525144721 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_errors.3525144721
Directory /workspace/8.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.2800529902
Short name T93
Test name
Test status
Simulation time 180219247 ps
CPU time 1.08 seconds
Started Jul 30 06:38:02 PM PDT 24
Finished Jul 30 06:38:03 PM PDT 24
Peak memory 200712 kb
Host smart-83494b97-56d0-4680-818d-176696c51409
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800529902 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_intg_err
.2800529902
Directory /workspace/8.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.814151590
Short name T691
Test name
Test status
Simulation time 37649866 ps
CPU time 0.74 seconds
Started Jul 30 06:38:05 PM PDT 24
Finished Jul 30 06:38:06 PM PDT 24
Peak memory 195328 kb
Host smart-2b4d2ca3-6a98-4758-8b98-353dd13636dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814151590 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.pwrmgr_csr_mem_rw_with_rand_reset.814151590
Directory /workspace/9.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_csr_rw.1900063896
Short name T107
Test name
Test status
Simulation time 17815558 ps
CPU time 0.72 seconds
Started Jul 30 06:38:08 PM PDT 24
Finished Jul 30 06:38:09 PM PDT 24
Peak memory 197272 kb
Host smart-156eb8dd-0232-46c8-b197-e2aad50832bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900063896 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_csr_rw.1900063896
Directory /workspace/9.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_intr_test.3063741679
Short name T662
Test name
Test status
Simulation time 39981566 ps
CPU time 0.6 seconds
Started Jul 30 06:38:06 PM PDT 24
Finished Jul 30 06:38:07 PM PDT 24
Peak memory 195044 kb
Host smart-4f1f538d-8128-4ada-b6b2-09e1d259ff9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063741679 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_intr_test.3063741679
Directory /workspace/9.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.2674358889
Short name T683
Test name
Test status
Simulation time 84488642 ps
CPU time 0.79 seconds
Started Jul 30 06:38:11 PM PDT 24
Finished Jul 30 06:38:12 PM PDT 24
Peak memory 197944 kb
Host smart-ab689d7d-22ac-4318-8ffe-cd5af140536a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674358889 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sa
me_csr_outstanding.2674358889
Directory /workspace/9.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_tl_errors.3852041857
Short name T698
Test name
Test status
Simulation time 69842930 ps
CPU time 1.61 seconds
Started Jul 30 06:38:10 PM PDT 24
Finished Jul 30 06:38:11 PM PDT 24
Peak memory 196460 kb
Host smart-df81641e-bd84-4270-8bf3-52504145005f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852041857 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_errors.3852041857
Directory /workspace/9.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.3610293646
Short name T146
Test name
Test status
Simulation time 109631823 ps
CPU time 1.15 seconds
Started Jul 30 06:38:13 PM PDT 24
Finished Jul 30 06:38:14 PM PDT 24
Peak memory 195264 kb
Host smart-04b934b1-5a6e-40a6-98de-c9cf7e2787c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610293646 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_intg_err
.3610293646
Directory /workspace/9.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.pwrmgr_aborted_low_power.3529715986
Short name T468
Test name
Test status
Simulation time 71840312 ps
CPU time 0.95 seconds
Started Jul 30 06:40:21 PM PDT 24
Finished Jul 30 06:40:22 PM PDT 24
Peak memory 200240 kb
Host smart-c829a87c-2381-4cd1-97bf-72acc793ac14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529715986 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_aborted_low_power.3529715986
Directory /workspace/0.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/0.pwrmgr_disable_rom_integrity_check.4228245012
Short name T393
Test name
Test status
Simulation time 63862965 ps
CPU time 0.82 seconds
Started Jul 30 06:40:23 PM PDT 24
Finished Jul 30 06:40:24 PM PDT 24
Peak memory 198548 kb
Host smart-47d78edb-9904-49cf-9571-6c817100cf6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228245012 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_disa
ble_rom_integrity_check.4228245012
Directory /workspace/0.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/0.pwrmgr_esc_clk_rst_malfunc.3848829105
Short name T446
Test name
Test status
Simulation time 32940419 ps
CPU time 0.61 seconds
Started Jul 30 06:40:18 PM PDT 24
Finished Jul 30 06:40:18 PM PDT 24
Peak memory 198068 kb
Host smart-89d2f8e0-8b6d-4010-bdf8-1dec71d234cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848829105 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_esc_clk_rst_
malfunc.3848829105
Directory /workspace/0.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/0.pwrmgr_escalation_timeout.3888520155
Short name T583
Test name
Test status
Simulation time 632569522 ps
CPU time 0.95 seconds
Started Jul 30 06:40:13 PM PDT 24
Finished Jul 30 06:40:14 PM PDT 24
Peak memory 198124 kb
Host smart-f7acebb8-eb2f-439b-a1fc-4830f5886fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888520155 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_escalation_timeout.3888520155
Directory /workspace/0.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/0.pwrmgr_glitch.3420798187
Short name T367
Test name
Test status
Simulation time 35666136 ps
CPU time 0.59 seconds
Started Jul 30 06:40:18 PM PDT 24
Finished Jul 30 06:40:19 PM PDT 24
Peak memory 198136 kb
Host smart-3ea0c8a1-6232-4007-8ad6-15f909e2e3f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420798187 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_glitch.3420798187
Directory /workspace/0.pwrmgr_glitch/latest

Test location /workspace/coverage/default/0.pwrmgr_global_esc.563242265
Short name T286
Test name
Test status
Simulation time 34062914 ps
CPU time 0.6 seconds
Started Jul 30 06:40:19 PM PDT 24
Finished Jul 30 06:40:20 PM PDT 24
Peak memory 197976 kb
Host smart-79af6075-e6f9-46e0-a03a-146208125186
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563242265 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_global_esc.563242265
Directory /workspace/0.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/0.pwrmgr_reset.4019383118
Short name T227
Test name
Test status
Simulation time 162251089 ps
CPU time 0.82 seconds
Started Jul 30 06:40:15 PM PDT 24
Finished Jul 30 06:40:16 PM PDT 24
Peak memory 198408 kb
Host smart-777fbee1-23bf-445d-8f7a-4ba331d305af
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019383118 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset.4019383118
Directory /workspace/0.pwrmgr_reset/latest

Test location /workspace/coverage/default/0.pwrmgr_reset_invalid.1070890548
Short name T523
Test name
Test status
Simulation time 123185727 ps
CPU time 0.8 seconds
Started Jul 30 06:40:19 PM PDT 24
Finished Jul 30 06:40:20 PM PDT 24
Peak memory 201340 kb
Host smart-9433ae65-d1d6-4084-8027-0c05bffcf9b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070890548 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset_invalid.1070890548
Directory /workspace/0.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm.3188479407
Short name T21
Test name
Test status
Simulation time 656006587 ps
CPU time 1.63 seconds
Started Jul 30 06:40:23 PM PDT 24
Finished Jul 30 06:40:24 PM PDT 24
Peak memory 218772 kb
Host smart-a92505b0-9f54-41a1-bb0c-4d9ed5ddb6a0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188479407 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm.3188479407
Directory /workspace/0.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm_rstmgr_intersig_mubi.215070798
Short name T388
Test name
Test status
Simulation time 56109121 ps
CPU time 0.76 seconds
Started Jul 30 06:40:16 PM PDT 24
Finished Jul 30 06:40:17 PM PDT 24
Peak memory 198084 kb
Host smart-e1ba7a8a-05cb-4f36-8ae2-a32fd0cdd907
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215070798 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.215070798
Directory /workspace/0.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/0.pwrmgr_smoke.1376655137
Short name T11
Test name
Test status
Simulation time 37129306 ps
CPU time 0.61 seconds
Started Jul 30 06:40:15 PM PDT 24
Finished Jul 30 06:40:15 PM PDT 24
Peak memory 198492 kb
Host smart-f2cf55ce-585d-4e57-a257-06c67b99bbe8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376655137 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_smoke.1376655137
Directory /workspace/0.pwrmgr_smoke/latest

Test location /workspace/coverage/default/1.pwrmgr_aborted_low_power.1867253784
Short name T13
Test name
Test status
Simulation time 60110583 ps
CPU time 0.84 seconds
Started Jul 30 06:40:19 PM PDT 24
Finished Jul 30 06:40:20 PM PDT 24
Peak memory 200016 kb
Host smart-bcf5c255-19e3-4ce6-9c0d-55817b72070d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867253784 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_aborted_low_power.1867253784
Directory /workspace/1.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/1.pwrmgr_disable_rom_integrity_check.3215051396
Short name T490
Test name
Test status
Simulation time 60853448 ps
CPU time 0.83 seconds
Started Jul 30 06:40:30 PM PDT 24
Finished Jul 30 06:40:31 PM PDT 24
Peak memory 199080 kb
Host smart-d1af4a6f-d9e3-40c1-bd7b-42c660ca0b42
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215051396 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_disa
ble_rom_integrity_check.3215051396
Directory /workspace/1.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/1.pwrmgr_esc_clk_rst_malfunc.587514971
Short name T591
Test name
Test status
Simulation time 29744361 ps
CPU time 0.64 seconds
Started Jul 30 06:40:23 PM PDT 24
Finished Jul 30 06:40:24 PM PDT 24
Peak memory 198024 kb
Host smart-29745c69-358d-456c-a2fd-2f0ef749f32a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587514971 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_esc_clk_rst_m
alfunc.587514971
Directory /workspace/1.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/1.pwrmgr_escalation_timeout.1126892272
Short name T310
Test name
Test status
Simulation time 159727596 ps
CPU time 0.98 seconds
Started Jul 30 06:40:23 PM PDT 24
Finished Jul 30 06:40:24 PM PDT 24
Peak memory 198084 kb
Host smart-1b60ffd4-17d2-43a4-a6c1-4e6eebdc58d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126892272 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_escalation_timeout.1126892272
Directory /workspace/1.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/1.pwrmgr_glitch.1864734233
Short name T520
Test name
Test status
Simulation time 70867364 ps
CPU time 0.65 seconds
Started Jul 30 06:40:24 PM PDT 24
Finished Jul 30 06:40:25 PM PDT 24
Peak memory 197432 kb
Host smart-e7d6115f-5f9c-4b55-ace9-185febb21e67
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864734233 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_glitch.1864734233
Directory /workspace/1.pwrmgr_glitch/latest

Test location /workspace/coverage/default/1.pwrmgr_global_esc.2931614551
Short name T231
Test name
Test status
Simulation time 29641507 ps
CPU time 0.57 seconds
Started Jul 30 06:40:24 PM PDT 24
Finished Jul 30 06:40:25 PM PDT 24
Peak memory 198464 kb
Host smart-d995a1bf-d902-48a0-b8e2-874747b77f58
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931614551 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_global_esc.2931614551
Directory /workspace/1.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/1.pwrmgr_reset.459699198
Short name T346
Test name
Test status
Simulation time 68621593 ps
CPU time 0.75 seconds
Started Jul 30 06:40:26 PM PDT 24
Finished Jul 30 06:40:27 PM PDT 24
Peak memory 199248 kb
Host smart-99da6334-b6f1-413c-a403-29df2589e471
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459699198 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset.459699198
Directory /workspace/1.pwrmgr_reset/latest

Test location /workspace/coverage/default/1.pwrmgr_reset_invalid.2615588613
Short name T323
Test name
Test status
Simulation time 184518296 ps
CPU time 0.8 seconds
Started Jul 30 06:40:28 PM PDT 24
Finished Jul 30 06:40:29 PM PDT 24
Peak memory 209580 kb
Host smart-f0252b07-0f40-40a7-a6db-fadc5e081a2e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615588613 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset_invalid.2615588613
Directory /workspace/1.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm_rstmgr_intersig_mubi.69092200
Short name T40
Test name
Test status
Simulation time 60691115 ps
CPU time 0.82 seconds
Started Jul 30 06:40:24 PM PDT 24
Finished Jul 30 06:40:25 PM PDT 24
Peak memory 198160 kb
Host smart-a81aeba5-b344-4fcd-8ba4-97f85d0095e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69092200 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_rstmgr_intersig_mu
bi.69092200
Directory /workspace/1.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/1.pwrmgr_smoke.403485859
Short name T369
Test name
Test status
Simulation time 29924671 ps
CPU time 0.65 seconds
Started Jul 30 06:40:21 PM PDT 24
Finished Jul 30 06:40:21 PM PDT 24
Peak memory 198500 kb
Host smart-f70ed7b3-df9b-47dc-ba88-397e108ee5dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403485859 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_smoke.403485859
Directory /workspace/1.pwrmgr_smoke/latest

Test location /workspace/coverage/default/10.pwrmgr_aborted_low_power.2800091802
Short name T498
Test name
Test status
Simulation time 36586998 ps
CPU time 0.72 seconds
Started Jul 30 06:40:53 PM PDT 24
Finished Jul 30 06:40:53 PM PDT 24
Peak memory 198724 kb
Host smart-c43fd70f-8441-4aa6-971c-e09a9c3b2d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800091802 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_aborted_low_power.2800091802
Directory /workspace/10.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/10.pwrmgr_disable_rom_integrity_check.139804026
Short name T136
Test name
Test status
Simulation time 86603832 ps
CPU time 0.63 seconds
Started Jul 30 06:40:57 PM PDT 24
Finished Jul 30 06:40:58 PM PDT 24
Peak memory 199092 kb
Host smart-16d9223f-d0de-4d87-9bbe-09360dc01cff
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139804026 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_disa
ble_rom_integrity_check.139804026
Directory /workspace/10.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/10.pwrmgr_esc_clk_rst_malfunc.3622340336
Short name T260
Test name
Test status
Simulation time 32969351 ps
CPU time 0.63 seconds
Started Jul 30 06:40:49 PM PDT 24
Finished Jul 30 06:40:50 PM PDT 24
Peak memory 198052 kb
Host smart-04e31667-3b9c-484b-9dbe-6ecc89049896
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622340336 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_esc_clk_rst
_malfunc.3622340336
Directory /workspace/10.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/10.pwrmgr_escalation_timeout.1536067566
Short name T448
Test name
Test status
Simulation time 608572514 ps
CPU time 0.95 seconds
Started Jul 30 06:40:57 PM PDT 24
Finished Jul 30 06:40:58 PM PDT 24
Peak memory 198088 kb
Host smart-bc4be4b6-ddcf-49c9-a867-eb11ff7e5406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536067566 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_escalation_timeout.1536067566
Directory /workspace/10.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/10.pwrmgr_glitch.1219680187
Short name T287
Test name
Test status
Simulation time 51212137 ps
CPU time 0.63 seconds
Started Jul 30 06:40:54 PM PDT 24
Finished Jul 30 06:40:54 PM PDT 24
Peak memory 198044 kb
Host smart-c45ce1d8-ad65-4b93-8e65-1a5aac8acb7d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219680187 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_glitch.1219680187
Directory /workspace/10.pwrmgr_glitch/latest

Test location /workspace/coverage/default/10.pwrmgr_global_esc.583373040
Short name T391
Test name
Test status
Simulation time 30295484 ps
CPU time 0.61 seconds
Started Jul 30 06:40:54 PM PDT 24
Finished Jul 30 06:40:55 PM PDT 24
Peak memory 198128 kb
Host smart-640d6828-80e2-4b72-a672-9a1e555c2faf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583373040 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_global_esc.583373040
Directory /workspace/10.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/10.pwrmgr_reset.51486482
Short name T45
Test name
Test status
Simulation time 62198278 ps
CPU time 0.76 seconds
Started Jul 30 06:40:50 PM PDT 24
Finished Jul 30 06:40:51 PM PDT 24
Peak memory 198484 kb
Host smart-ffb4d3b3-7e29-458b-bfdb-fa7b7b91bfb5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51486482 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset.51486482
Directory /workspace/10.pwrmgr_reset/latest

Test location /workspace/coverage/default/10.pwrmgr_reset_invalid.2728203681
Short name T430
Test name
Test status
Simulation time 125155184 ps
CPU time 0.85 seconds
Started Jul 30 06:40:58 PM PDT 24
Finished Jul 30 06:40:59 PM PDT 24
Peak memory 209500 kb
Host smart-2dc55ea0-455f-46d9-af60-a102683e877d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728203681 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset_invalid.2728203681
Directory /workspace/10.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/10.pwrmgr_sec_cm_rstmgr_intersig_mubi.2894278810
Short name T589
Test name
Test status
Simulation time 228388558 ps
CPU time 0.74 seconds
Started Jul 30 06:40:53 PM PDT 24
Finished Jul 30 06:40:54 PM PDT 24
Peak memory 199564 kb
Host smart-4c843a9a-5169-4825-8467-29a69292a69e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894278810 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2894278810
Directory /workspace/10.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/10.pwrmgr_smoke.4102420457
Short name T85
Test name
Test status
Simulation time 116550092 ps
CPU time 0.66 seconds
Started Jul 30 06:40:51 PM PDT 24
Finished Jul 30 06:40:51 PM PDT 24
Peak memory 198544 kb
Host smart-85a09c73-860b-4819-bd82-6a2fce7dfc06
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102420457 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_smoke.4102420457
Directory /workspace/10.pwrmgr_smoke/latest

Test location /workspace/coverage/default/11.pwrmgr_aborted_low_power.2912354336
Short name T86
Test name
Test status
Simulation time 113030932 ps
CPU time 0.81 seconds
Started Jul 30 06:40:52 PM PDT 24
Finished Jul 30 06:40:53 PM PDT 24
Peak memory 200000 kb
Host smart-fd712563-974c-4a65-9649-a2243c0db23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912354336 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_aborted_low_power.2912354336
Directory /workspace/11.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/11.pwrmgr_esc_clk_rst_malfunc.3008938509
Short name T497
Test name
Test status
Simulation time 36962001 ps
CPU time 0.6 seconds
Started Jul 30 06:40:59 PM PDT 24
Finished Jul 30 06:40:59 PM PDT 24
Peak memory 198040 kb
Host smart-9dfec2ce-2a53-4669-bc50-bb6c102b64b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008938509 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_esc_clk_rst
_malfunc.3008938509
Directory /workspace/11.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/11.pwrmgr_escalation_timeout.3547237319
Short name T365
Test name
Test status
Simulation time 639052094 ps
CPU time 0.93 seconds
Started Jul 30 06:41:04 PM PDT 24
Finished Jul 30 06:41:05 PM PDT 24
Peak memory 198452 kb
Host smart-32b588d4-1f20-4fee-9527-ce2cfc312a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547237319 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_escalation_timeout.3547237319
Directory /workspace/11.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/11.pwrmgr_glitch.456736091
Short name T411
Test name
Test status
Simulation time 32825497 ps
CPU time 0.65 seconds
Started Jul 30 06:40:57 PM PDT 24
Finished Jul 30 06:40:58 PM PDT 24
Peak memory 198096 kb
Host smart-e1a550f4-d834-47dd-b660-0f1737ae6356
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456736091 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_glitch.456736091
Directory /workspace/11.pwrmgr_glitch/latest

Test location /workspace/coverage/default/11.pwrmgr_global_esc.1843808991
Short name T524
Test name
Test status
Simulation time 80315055 ps
CPU time 0.61 seconds
Started Jul 30 06:40:58 PM PDT 24
Finished Jul 30 06:40:59 PM PDT 24
Peak memory 198104 kb
Host smart-88d2bb2b-f1e8-403b-8867-c81932895376
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843808991 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_global_esc.1843808991
Directory /workspace/11.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/11.pwrmgr_reset.3475872095
Short name T521
Test name
Test status
Simulation time 64034699 ps
CPU time 0.78 seconds
Started Jul 30 06:40:56 PM PDT 24
Finished Jul 30 06:40:57 PM PDT 24
Peak memory 199076 kb
Host smart-f79b5f2f-bb06-4750-a6ce-544fd22be9df
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475872095 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset.3475872095
Directory /workspace/11.pwrmgr_reset/latest

Test location /workspace/coverage/default/11.pwrmgr_reset_invalid.389967542
Short name T233
Test name
Test status
Simulation time 102684487 ps
CPU time 1.01 seconds
Started Jul 30 06:40:57 PM PDT 24
Finished Jul 30 06:40:58 PM PDT 24
Peak memory 209528 kb
Host smart-96ca909d-ed93-4109-a2fb-a57db5f655a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389967542 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset_invalid.389967542
Directory /workspace/11.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/11.pwrmgr_sec_cm_rstmgr_intersig_mubi.2198839575
Short name T124
Test name
Test status
Simulation time 251525540 ps
CPU time 0.78 seconds
Started Jul 30 06:40:57 PM PDT 24
Finished Jul 30 06:40:58 PM PDT 24
Peak memory 197944 kb
Host smart-8090940a-9144-4fc8-8f65-fae483eadee6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198839575 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2198839575
Directory /workspace/11.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/11.pwrmgr_smoke.3959491308
Short name T386
Test name
Test status
Simulation time 27779748 ps
CPU time 0.65 seconds
Started Jul 30 06:40:59 PM PDT 24
Finished Jul 30 06:40:59 PM PDT 24
Peak memory 198520 kb
Host smart-f11b26a9-c8bd-40ed-8540-66983eddf70e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959491308 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_smoke.3959491308
Directory /workspace/11.pwrmgr_smoke/latest

Test location /workspace/coverage/default/12.pwrmgr_aborted_low_power.4076670518
Short name T333
Test name
Test status
Simulation time 114749094 ps
CPU time 0.83 seconds
Started Jul 30 06:41:00 PM PDT 24
Finished Jul 30 06:41:01 PM PDT 24
Peak memory 200196 kb
Host smart-897dd8ab-c1a6-44d6-a678-5d911a7db9eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076670518 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_aborted_low_power.4076670518
Directory /workspace/12.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/12.pwrmgr_disable_rom_integrity_check.534144010
Short name T162
Test name
Test status
Simulation time 62661758 ps
CPU time 0.77 seconds
Started Jul 30 06:41:02 PM PDT 24
Finished Jul 30 06:41:03 PM PDT 24
Peak memory 199084 kb
Host smart-745d2fc6-21cc-47be-82f1-4ba9c6e5bc97
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534144010 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_disa
ble_rom_integrity_check.534144010
Directory /workspace/12.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/12.pwrmgr_esc_clk_rst_malfunc.1756397200
Short name T129
Test name
Test status
Simulation time 29115733 ps
CPU time 0.64 seconds
Started Jul 30 06:40:57 PM PDT 24
Finished Jul 30 06:40:58 PM PDT 24
Peak memory 197316 kb
Host smart-73025d5f-3733-4b59-9d09-7a08cf79a977
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756397200 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_esc_clk_rst
_malfunc.1756397200
Directory /workspace/12.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/12.pwrmgr_escalation_timeout.2581919206
Short name T334
Test name
Test status
Simulation time 175782027 ps
CPU time 1.03 seconds
Started Jul 30 06:41:11 PM PDT 24
Finished Jul 30 06:41:12 PM PDT 24
Peak memory 198012 kb
Host smart-150e342f-ef1b-4e32-9a4e-c9e29f6bb27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581919206 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_escalation_timeout.2581919206
Directory /workspace/12.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/12.pwrmgr_global_esc.2512434202
Short name T549
Test name
Test status
Simulation time 79618381 ps
CPU time 0.67 seconds
Started Jul 30 06:41:05 PM PDT 24
Finished Jul 30 06:41:05 PM PDT 24
Peak memory 198424 kb
Host smart-868044d7-af75-4d5b-897d-f87e88205b4d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512434202 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_global_esc.2512434202
Directory /workspace/12.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/12.pwrmgr_lowpower_invalid.2375849042
Short name T177
Test name
Test status
Simulation time 54082172 ps
CPU time 0.64 seconds
Started Jul 30 06:41:00 PM PDT 24
Finished Jul 30 06:41:01 PM PDT 24
Peak memory 201188 kb
Host smart-7f9ecf09-15d8-4702-8428-a76cabe2ce2f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375849042 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_lowpower_inval
id.2375849042
Directory /workspace/12.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/12.pwrmgr_reset.2724322388
Short name T517
Test name
Test status
Simulation time 131018360 ps
CPU time 0.71 seconds
Started Jul 30 06:41:00 PM PDT 24
Finished Jul 30 06:41:01 PM PDT 24
Peak memory 199168 kb
Host smart-6f506812-6198-48df-9fc6-f03c439aea88
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724322388 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset.2724322388
Directory /workspace/12.pwrmgr_reset/latest

Test location /workspace/coverage/default/12.pwrmgr_reset_invalid.4024842825
Short name T41
Test name
Test status
Simulation time 165202810 ps
CPU time 0.79 seconds
Started Jul 30 06:40:58 PM PDT 24
Finished Jul 30 06:40:59 PM PDT 24
Peak memory 209460 kb
Host smart-67ce3ea3-c3de-4bff-946b-c8ea0822d819
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024842825 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset_invalid.4024842825
Directory /workspace/12.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/12.pwrmgr_sec_cm_rstmgr_intersig_mubi.311339226
Short name T338
Test name
Test status
Simulation time 109117338 ps
CPU time 0.77 seconds
Started Jul 30 06:40:59 PM PDT 24
Finished Jul 30 06:41:00 PM PDT 24
Peak memory 198032 kb
Host smart-3e82e589-d787-4067-bb8c-f77fc6bdfafa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311339226 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_rstmgr_intersig_
mubi.311339226
Directory /workspace/12.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/12.pwrmgr_smoke.2503242417
Short name T302
Test name
Test status
Simulation time 36815883 ps
CPU time 0.66 seconds
Started Jul 30 06:40:59 PM PDT 24
Finished Jul 30 06:41:00 PM PDT 24
Peak memory 198548 kb
Host smart-1a3e6981-0c38-4095-b088-974693232bdf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503242417 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_smoke.2503242417
Directory /workspace/12.pwrmgr_smoke/latest

Test location /workspace/coverage/default/13.pwrmgr_aborted_low_power.2735529367
Short name T98
Test name
Test status
Simulation time 40815259 ps
CPU time 0.65 seconds
Started Jul 30 06:41:11 PM PDT 24
Finished Jul 30 06:41:11 PM PDT 24
Peak memory 198540 kb
Host smart-5359be89-cdfa-4106-94d7-4aae05c53ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735529367 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_aborted_low_power.2735529367
Directory /workspace/13.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/13.pwrmgr_disable_rom_integrity_check.1230317981
Short name T135
Test name
Test status
Simulation time 64947137 ps
CPU time 0.78 seconds
Started Jul 30 06:41:03 PM PDT 24
Finished Jul 30 06:41:04 PM PDT 24
Peak memory 199148 kb
Host smart-691f3af9-0cd8-4ac7-a9f7-af26ba29e85d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230317981 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_dis
able_rom_integrity_check.1230317981
Directory /workspace/13.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/13.pwrmgr_esc_clk_rst_malfunc.392500339
Short name T508
Test name
Test status
Simulation time 30236866 ps
CPU time 0.64 seconds
Started Jul 30 06:41:00 PM PDT 24
Finished Jul 30 06:41:01 PM PDT 24
Peak memory 198032 kb
Host smart-b6246a82-ad55-4f2b-80b3-bc2770ed124a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392500339 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_esc_clk_rst_
malfunc.392500339
Directory /workspace/13.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/13.pwrmgr_escalation_timeout.599591569
Short name T470
Test name
Test status
Simulation time 164187072 ps
CPU time 0.92 seconds
Started Jul 30 06:41:00 PM PDT 24
Finished Jul 30 06:41:01 PM PDT 24
Peak memory 198056 kb
Host smart-22bc6996-9eb1-4d1f-b849-edc40de9fc96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599591569 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_escalation_timeout.599591569
Directory /workspace/13.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/13.pwrmgr_glitch.4025309563
Short name T483
Test name
Test status
Simulation time 45557059 ps
CPU time 0.6 seconds
Started Jul 30 06:40:59 PM PDT 24
Finished Jul 30 06:41:00 PM PDT 24
Peak memory 198076 kb
Host smart-4439f6fd-a1c1-4db5-b5db-4e73d55ac908
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025309563 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_glitch.4025309563
Directory /workspace/13.pwrmgr_glitch/latest

Test location /workspace/coverage/default/13.pwrmgr_global_esc.441939202
Short name T238
Test name
Test status
Simulation time 54805127 ps
CPU time 0.6 seconds
Started Jul 30 06:41:05 PM PDT 24
Finished Jul 30 06:41:05 PM PDT 24
Peak memory 198420 kb
Host smart-2299466b-0896-4353-a896-06ad8e948e4d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441939202 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_global_esc.441939202
Directory /workspace/13.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/13.pwrmgr_lowpower_invalid.1960001911
Short name T200
Test name
Test status
Simulation time 84317705 ps
CPU time 0.7 seconds
Started Jul 30 06:41:02 PM PDT 24
Finished Jul 30 06:41:03 PM PDT 24
Peak memory 201424 kb
Host smart-5ef2eec8-a8f1-4397-8cca-e608aa782ed6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960001911 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_lowpower_inval
id.1960001911
Directory /workspace/13.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/13.pwrmgr_reset.184413074
Short name T291
Test name
Test status
Simulation time 88755429 ps
CPU time 0.88 seconds
Started Jul 30 06:41:00 PM PDT 24
Finished Jul 30 06:41:01 PM PDT 24
Peak memory 199180 kb
Host smart-06ced372-99ee-4fe2-9490-f9feb17c8d59
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184413074 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset.184413074
Directory /workspace/13.pwrmgr_reset/latest

Test location /workspace/coverage/default/13.pwrmgr_sec_cm_rstmgr_intersig_mubi.1120324386
Short name T65
Test name
Test status
Simulation time 132535229 ps
CPU time 0.71 seconds
Started Jul 30 06:40:59 PM PDT 24
Finished Jul 30 06:41:00 PM PDT 24
Peak memory 198188 kb
Host smart-358fce0d-10da-4b4d-a1ef-daf4b5f7d22a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120324386 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1120324386
Directory /workspace/13.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/13.pwrmgr_smoke.2343566424
Short name T319
Test name
Test status
Simulation time 56522205 ps
CPU time 0.66 seconds
Started Jul 30 06:41:00 PM PDT 24
Finished Jul 30 06:41:01 PM PDT 24
Peak memory 199328 kb
Host smart-7ab39a4c-3840-4e7e-a610-0f5c68822a16
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343566424 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_smoke.2343566424
Directory /workspace/13.pwrmgr_smoke/latest

Test location /workspace/coverage/default/14.pwrmgr_aborted_low_power.2708170924
Short name T179
Test name
Test status
Simulation time 29505458 ps
CPU time 0.96 seconds
Started Jul 30 06:41:08 PM PDT 24
Finished Jul 30 06:41:09 PM PDT 24
Peak memory 200928 kb
Host smart-806fd204-546d-4706-9f74-4f44d44b4866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708170924 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_aborted_low_power.2708170924
Directory /workspace/14.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/14.pwrmgr_disable_rom_integrity_check.3694294744
Short name T463
Test name
Test status
Simulation time 163494414 ps
CPU time 0.63 seconds
Started Jul 30 06:41:07 PM PDT 24
Finished Jul 30 06:41:08 PM PDT 24
Peak memory 198556 kb
Host smart-c650f376-f1c8-4b79-b0c5-b5de809a3cae
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694294744 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_dis
able_rom_integrity_check.3694294744
Directory /workspace/14.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/14.pwrmgr_esc_clk_rst_malfunc.1366351552
Short name T428
Test name
Test status
Simulation time 30934851 ps
CPU time 0.63 seconds
Started Jul 30 06:41:03 PM PDT 24
Finished Jul 30 06:41:04 PM PDT 24
Peak memory 197340 kb
Host smart-b49a18d1-4839-4fa6-8468-11102479d726
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366351552 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_esc_clk_rst
_malfunc.1366351552
Directory /workspace/14.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/14.pwrmgr_escalation_timeout.2782056615
Short name T485
Test name
Test status
Simulation time 755998185 ps
CPU time 0.92 seconds
Started Jul 30 06:41:04 PM PDT 24
Finished Jul 30 06:41:05 PM PDT 24
Peak memory 198176 kb
Host smart-a3987967-c471-4494-af91-7107f0ab1ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782056615 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_escalation_timeout.2782056615
Directory /workspace/14.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/14.pwrmgr_glitch.1065616034
Short name T624
Test name
Test status
Simulation time 40504209 ps
CPU time 0.65 seconds
Started Jul 30 06:41:02 PM PDT 24
Finished Jul 30 06:41:03 PM PDT 24
Peak memory 197220 kb
Host smart-08ff4207-8a17-4aa7-91d8-4dba90c26dfe
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065616034 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_glitch.1065616034
Directory /workspace/14.pwrmgr_glitch/latest

Test location /workspace/coverage/default/14.pwrmgr_global_esc.3023872548
Short name T500
Test name
Test status
Simulation time 40600177 ps
CPU time 0.58 seconds
Started Jul 30 06:42:34 PM PDT 24
Finished Jul 30 06:42:35 PM PDT 24
Peak memory 197904 kb
Host smart-c885b034-d3ed-4bc6-b7d7-cf36e2099cf8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023872548 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_global_esc.3023872548
Directory /workspace/14.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/14.pwrmgr_lowpower_invalid.4227908973
Short name T174
Test name
Test status
Simulation time 170384302 ps
CPU time 0.68 seconds
Started Jul 30 06:41:00 PM PDT 24
Finished Jul 30 06:41:01 PM PDT 24
Peak memory 201172 kb
Host smart-856f3042-7cec-4ec1-a374-cbe727e9d511
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227908973 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_lowpower_inval
id.4227908973
Directory /workspace/14.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/14.pwrmgr_reset.4229762299
Short name T43
Test name
Test status
Simulation time 54102309 ps
CPU time 0.77 seconds
Started Jul 30 06:41:04 PM PDT 24
Finished Jul 30 06:41:05 PM PDT 24
Peak memory 199168 kb
Host smart-7c8a49f6-ac3e-4c2d-ad12-92c7cdc00cfd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229762299 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset.4229762299
Directory /workspace/14.pwrmgr_reset/latest

Test location /workspace/coverage/default/14.pwrmgr_reset_invalid.548777554
Short name T616
Test name
Test status
Simulation time 163717337 ps
CPU time 0.77 seconds
Started Jul 30 06:41:02 PM PDT 24
Finished Jul 30 06:41:03 PM PDT 24
Peak memory 209520 kb
Host smart-60277919-a4a5-4f34-a53b-72cc058e4ee9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548777554 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset_invalid.548777554
Directory /workspace/14.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/14.pwrmgr_sec_cm_rstmgr_intersig_mubi.3518146949
Short name T248
Test name
Test status
Simulation time 60648497 ps
CPU time 0.87 seconds
Started Jul 30 06:41:01 PM PDT 24
Finished Jul 30 06:41:02 PM PDT 24
Peak memory 198352 kb
Host smart-f2d16ade-8c76-454b-86c1-f3e94d923d83
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518146949 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3518146949
Directory /workspace/14.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/14.pwrmgr_smoke.4197055296
Short name T299
Test name
Test status
Simulation time 36378548 ps
CPU time 0.65 seconds
Started Jul 30 06:41:03 PM PDT 24
Finished Jul 30 06:41:03 PM PDT 24
Peak memory 198532 kb
Host smart-e997a11f-3dbd-4ae7-ae52-ba3d292681cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197055296 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_smoke.4197055296
Directory /workspace/14.pwrmgr_smoke/latest

Test location /workspace/coverage/default/15.pwrmgr_disable_rom_integrity_check.1300804054
Short name T495
Test name
Test status
Simulation time 61840654 ps
CPU time 0.68 seconds
Started Jul 30 06:41:06 PM PDT 24
Finished Jul 30 06:41:07 PM PDT 24
Peak memory 199196 kb
Host smart-f893202d-2283-4299-abf6-102919b46d0a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300804054 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_dis
able_rom_integrity_check.1300804054
Directory /workspace/15.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/15.pwrmgr_esc_clk_rst_malfunc.2518314731
Short name T277
Test name
Test status
Simulation time 40331471 ps
CPU time 0.6 seconds
Started Jul 30 06:41:07 PM PDT 24
Finished Jul 30 06:41:08 PM PDT 24
Peak memory 198088 kb
Host smart-f30f94a7-624f-49ec-9ee7-19b7fa3690b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518314731 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_esc_clk_rst
_malfunc.2518314731
Directory /workspace/15.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/15.pwrmgr_escalation_timeout.2616718983
Short name T487
Test name
Test status
Simulation time 166742200 ps
CPU time 0.97 seconds
Started Jul 30 06:41:07 PM PDT 24
Finished Jul 30 06:41:08 PM PDT 24
Peak memory 198108 kb
Host smart-dd4cc148-470d-4908-bc52-aeff9694d8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616718983 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_escalation_timeout.2616718983
Directory /workspace/15.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/15.pwrmgr_glitch.3685355213
Short name T466
Test name
Test status
Simulation time 43007024 ps
CPU time 0.62 seconds
Started Jul 30 06:41:06 PM PDT 24
Finished Jul 30 06:41:07 PM PDT 24
Peak memory 198140 kb
Host smart-b3bd4c8b-9b86-4c91-86c8-a14ba0f1d0bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685355213 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_glitch.3685355213
Directory /workspace/15.pwrmgr_glitch/latest

Test location /workspace/coverage/default/15.pwrmgr_global_esc.3653418258
Short name T283
Test name
Test status
Simulation time 30754946 ps
CPU time 0.63 seconds
Started Jul 30 06:41:07 PM PDT 24
Finished Jul 30 06:41:08 PM PDT 24
Peak memory 198148 kb
Host smart-7ac76d2e-f089-467c-ae13-09a3f7847469
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653418258 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_global_esc.3653418258
Directory /workspace/15.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/15.pwrmgr_lowpower_invalid.2795594550
Short name T197
Test name
Test status
Simulation time 45957375 ps
CPU time 0.72 seconds
Started Jul 30 06:41:07 PM PDT 24
Finished Jul 30 06:41:08 PM PDT 24
Peak memory 201452 kb
Host smart-e80d3592-ab7c-4ae4-b686-7b861dab6dbf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795594550 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_lowpower_inval
id.2795594550
Directory /workspace/15.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/15.pwrmgr_reset.2204974337
Short name T357
Test name
Test status
Simulation time 87940695 ps
CPU time 0.75 seconds
Started Jul 30 06:41:05 PM PDT 24
Finished Jul 30 06:41:05 PM PDT 24
Peak memory 198328 kb
Host smart-fcab3f18-1b85-4461-a1d8-5aaa3ffd0278
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204974337 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset.2204974337
Directory /workspace/15.pwrmgr_reset/latest

Test location /workspace/coverage/default/15.pwrmgr_reset_invalid.3477148727
Short name T532
Test name
Test status
Simulation time 98539884 ps
CPU time 1.12 seconds
Started Jul 30 06:41:05 PM PDT 24
Finished Jul 30 06:41:07 PM PDT 24
Peak memory 209340 kb
Host smart-109e4666-4465-4108-874a-be229d97e530
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477148727 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset_invalid.3477148727
Directory /workspace/15.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/15.pwrmgr_sec_cm_rstmgr_intersig_mubi.347628370
Short name T207
Test name
Test status
Simulation time 89509406 ps
CPU time 0.68 seconds
Started Jul 30 06:41:04 PM PDT 24
Finished Jul 30 06:41:05 PM PDT 24
Peak memory 198332 kb
Host smart-f107f837-8da0-4b8a-b4af-f40a9d3afcfe
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347628370 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_rstmgr_intersig_
mubi.347628370
Directory /workspace/15.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/15.pwrmgr_smoke.3915076352
Short name T290
Test name
Test status
Simulation time 65611430 ps
CPU time 0.66 seconds
Started Jul 30 06:41:04 PM PDT 24
Finished Jul 30 06:41:05 PM PDT 24
Peak memory 198588 kb
Host smart-e1f9d9f6-efa0-4e3f-99fa-5eb830077764
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915076352 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_smoke.3915076352
Directory /workspace/15.pwrmgr_smoke/latest

Test location /workspace/coverage/default/16.pwrmgr_aborted_low_power.216762564
Short name T459
Test name
Test status
Simulation time 106664200 ps
CPU time 0.8 seconds
Started Jul 30 06:41:02 PM PDT 24
Finished Jul 30 06:41:03 PM PDT 24
Peak memory 200140 kb
Host smart-9401a12b-20ba-4e60-8e79-40633ce80d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216762564 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_aborted_low_power.216762564
Directory /workspace/16.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/16.pwrmgr_disable_rom_integrity_check.2443994891
Short name T554
Test name
Test status
Simulation time 72131278 ps
CPU time 0.75 seconds
Started Jul 30 06:42:15 PM PDT 24
Finished Jul 30 06:42:16 PM PDT 24
Peak memory 196232 kb
Host smart-61ccfaf1-6dc3-424a-b6cd-af09d149adb9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443994891 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_dis
able_rom_integrity_check.2443994891
Directory /workspace/16.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/16.pwrmgr_esc_clk_rst_malfunc.2532558919
Short name T506
Test name
Test status
Simulation time 39851290 ps
CPU time 0.59 seconds
Started Jul 30 06:41:11 PM PDT 24
Finished Jul 30 06:41:12 PM PDT 24
Peak memory 197228 kb
Host smart-19ded784-ba0f-4648-bc46-18a92362de95
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532558919 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_esc_clk_rst
_malfunc.2532558919
Directory /workspace/16.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/16.pwrmgr_escalation_timeout.3670888046
Short name T426
Test name
Test status
Simulation time 167051473 ps
CPU time 0.99 seconds
Started Jul 30 06:41:11 PM PDT 24
Finished Jul 30 06:41:22 PM PDT 24
Peak memory 198004 kb
Host smart-5a883a8d-6094-4a00-bc69-2bfb805ba8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670888046 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_escalation_timeout.3670888046
Directory /workspace/16.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/16.pwrmgr_glitch.479635575
Short name T237
Test name
Test status
Simulation time 51181642 ps
CPU time 0.61 seconds
Started Jul 30 06:41:11 PM PDT 24
Finished Jul 30 06:41:12 PM PDT 24
Peak memory 198120 kb
Host smart-5019b9c9-de08-4bc5-b92a-e716c2c4ebd3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479635575 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_glitch.479635575
Directory /workspace/16.pwrmgr_glitch/latest

Test location /workspace/coverage/default/16.pwrmgr_global_esc.3271851211
Short name T438
Test name
Test status
Simulation time 23076154 ps
CPU time 0.58 seconds
Started Jul 30 06:41:00 PM PDT 24
Finished Jul 30 06:41:01 PM PDT 24
Peak memory 198096 kb
Host smart-1b54ddfe-a917-4bd8-9b12-a446c242184b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271851211 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_global_esc.3271851211
Directory /workspace/16.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/16.pwrmgr_lowpower_invalid.3552946123
Short name T172
Test name
Test status
Simulation time 42822985 ps
CPU time 0.72 seconds
Started Jul 30 06:42:15 PM PDT 24
Finished Jul 30 06:42:16 PM PDT 24
Peak memory 198376 kb
Host smart-0c276ae8-237d-4a84-b9e2-309e8c0f9cf2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552946123 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_lowpower_inval
id.3552946123
Directory /workspace/16.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/16.pwrmgr_reset.2888039851
Short name T313
Test name
Test status
Simulation time 94885896 ps
CPU time 0.74 seconds
Started Jul 30 06:42:31 PM PDT 24
Finished Jul 30 06:42:32 PM PDT 24
Peak memory 198204 kb
Host smart-35ec25a7-a829-41e8-a18e-d521752fe931
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888039851 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset.2888039851
Directory /workspace/16.pwrmgr_reset/latest

Test location /workspace/coverage/default/16.pwrmgr_reset_invalid.1603411372
Short name T34
Test name
Test status
Simulation time 112399961 ps
CPU time 0.94 seconds
Started Jul 30 06:41:11 PM PDT 24
Finished Jul 30 06:41:12 PM PDT 24
Peak memory 209380 kb
Host smart-1772f2ce-a8ee-4719-af2b-701fe50acd06
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603411372 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset_invalid.1603411372
Directory /workspace/16.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/16.pwrmgr_sec_cm_rstmgr_intersig_mubi.4277666601
Short name T395
Test name
Test status
Simulation time 53578403 ps
CPU time 0.8 seconds
Started Jul 30 06:41:05 PM PDT 24
Finished Jul 30 06:41:06 PM PDT 24
Peak memory 198108 kb
Host smart-048f0c2d-6fe4-4ff2-b36b-59c8876aa066
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277666601 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4277666601
Directory /workspace/16.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/16.pwrmgr_smoke.3245500620
Short name T511
Test name
Test status
Simulation time 157487387 ps
CPU time 0.62 seconds
Started Jul 30 06:42:36 PM PDT 24
Finished Jul 30 06:42:37 PM PDT 24
Peak memory 198332 kb
Host smart-e367f237-f874-4c97-9fc1-ea6373eca4c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245500620 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_smoke.3245500620
Directory /workspace/16.pwrmgr_smoke/latest

Test location /workspace/coverage/default/17.pwrmgr_aborted_low_power.2208751813
Short name T422
Test name
Test status
Simulation time 23832179 ps
CPU time 0.6 seconds
Started Jul 30 06:41:12 PM PDT 24
Finished Jul 30 06:41:13 PM PDT 24
Peak memory 198572 kb
Host smart-17b4a117-5fa2-46d7-8189-6b99bb83ce87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208751813 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_aborted_low_power.2208751813
Directory /workspace/17.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/17.pwrmgr_disable_rom_integrity_check.1512142655
Short name T569
Test name
Test status
Simulation time 58208388 ps
CPU time 0.7 seconds
Started Jul 30 06:41:06 PM PDT 24
Finished Jul 30 06:41:09 PM PDT 24
Peak memory 199172 kb
Host smart-f441ff00-5acb-49fc-9403-e4587df2fa9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512142655 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_dis
able_rom_integrity_check.1512142655
Directory /workspace/17.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/17.pwrmgr_esc_clk_rst_malfunc.2649693138
Short name T418
Test name
Test status
Simulation time 31747885 ps
CPU time 0.63 seconds
Started Jul 30 06:41:06 PM PDT 24
Finished Jul 30 06:41:07 PM PDT 24
Peak memory 198040 kb
Host smart-aadb4406-1be7-45d1-89b4-62cb5636e4e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649693138 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_esc_clk_rst
_malfunc.2649693138
Directory /workspace/17.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/17.pwrmgr_escalation_timeout.2973467531
Short name T376
Test name
Test status
Simulation time 162495212 ps
CPU time 0.98 seconds
Started Jul 30 06:41:07 PM PDT 24
Finished Jul 30 06:41:08 PM PDT 24
Peak memory 197996 kb
Host smart-c1006694-63a8-4f88-b583-bb0018d77762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973467531 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_escalation_timeout.2973467531
Directory /workspace/17.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/17.pwrmgr_glitch.2224006034
Short name T239
Test name
Test status
Simulation time 61156045 ps
CPU time 0.62 seconds
Started Jul 30 06:41:11 PM PDT 24
Finished Jul 30 06:41:11 PM PDT 24
Peak memory 198052 kb
Host smart-e06627d0-8fe3-4944-b5dd-4ba8df60628a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224006034 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_glitch.2224006034
Directory /workspace/17.pwrmgr_glitch/latest

Test location /workspace/coverage/default/17.pwrmgr_global_esc.698127935
Short name T473
Test name
Test status
Simulation time 62603135 ps
CPU time 0.6 seconds
Started Jul 30 06:41:05 PM PDT 24
Finished Jul 30 06:41:06 PM PDT 24
Peak memory 198172 kb
Host smart-acd63254-6685-4fdc-bbae-16ded18fae8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698127935 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_global_esc.698127935
Directory /workspace/17.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/17.pwrmgr_lowpower_invalid.140810123
Short name T199
Test name
Test status
Simulation time 41598602 ps
CPU time 0.71 seconds
Started Jul 30 06:41:07 PM PDT 24
Finished Jul 30 06:41:08 PM PDT 24
Peak memory 201648 kb
Host smart-3b0627fb-e8e1-4bab-95f9-2a714153eb46
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140810123 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_lowpower_invali
d.140810123
Directory /workspace/17.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/17.pwrmgr_reset.2698118930
Short name T347
Test name
Test status
Simulation time 76498903 ps
CPU time 0.71 seconds
Started Jul 30 06:41:38 PM PDT 24
Finished Jul 30 06:41:39 PM PDT 24
Peak memory 199148 kb
Host smart-0b6aad07-bfe8-4994-a6e3-53fafeb80559
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698118930 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset.2698118930
Directory /workspace/17.pwrmgr_reset/latest

Test location /workspace/coverage/default/17.pwrmgr_reset_invalid.683485109
Short name T403
Test name
Test status
Simulation time 108674821 ps
CPU time 0.89 seconds
Started Jul 30 06:41:07 PM PDT 24
Finished Jul 30 06:41:08 PM PDT 24
Peak memory 209520 kb
Host smart-12d36757-6c26-4206-a567-1d75c9382835
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683485109 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset_invalid.683485109
Directory /workspace/17.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/17.pwrmgr_sec_cm_rstmgr_intersig_mubi.2091238513
Short name T489
Test name
Test status
Simulation time 52727942 ps
CPU time 0.77 seconds
Started Jul 30 06:41:04 PM PDT 24
Finished Jul 30 06:41:05 PM PDT 24
Peak memory 198320 kb
Host smart-48e66d6d-66a5-4030-9e8b-8dae16b80fe2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091238513 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2091238513
Directory /workspace/17.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/17.pwrmgr_smoke.3851714534
Short name T123
Test name
Test status
Simulation time 39481691 ps
CPU time 0.64 seconds
Started Jul 30 06:41:07 PM PDT 24
Finished Jul 30 06:41:09 PM PDT 24
Peak memory 198524 kb
Host smart-abc814a2-1d82-4011-bcd7-0fecc895884e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851714534 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_smoke.3851714534
Directory /workspace/17.pwrmgr_smoke/latest

Test location /workspace/coverage/default/18.pwrmgr_aborted_low_power.3055160182
Short name T95
Test name
Test status
Simulation time 39911534 ps
CPU time 0.84 seconds
Started Jul 30 06:41:05 PM PDT 24
Finished Jul 30 06:41:06 PM PDT 24
Peak memory 199896 kb
Host smart-74e8dba7-1af2-45d3-9590-0e11bbc9db6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055160182 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_aborted_low_power.3055160182
Directory /workspace/18.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/18.pwrmgr_disable_rom_integrity_check.2336428537
Short name T147
Test name
Test status
Simulation time 86295167 ps
CPU time 0.72 seconds
Started Jul 30 06:41:09 PM PDT 24
Finished Jul 30 06:41:10 PM PDT 24
Peak memory 198528 kb
Host smart-331d0a43-db52-4e00-81fc-58c10a4809ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336428537 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_dis
able_rom_integrity_check.2336428537
Directory /workspace/18.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/18.pwrmgr_esc_clk_rst_malfunc.4288552184
Short name T525
Test name
Test status
Simulation time 39242699 ps
CPU time 0.58 seconds
Started Jul 30 06:41:06 PM PDT 24
Finished Jul 30 06:41:07 PM PDT 24
Peak memory 198024 kb
Host smart-f62c3f5d-6c25-4828-b18e-62de2e9ee38a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288552184 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_esc_clk_rst
_malfunc.4288552184
Directory /workspace/18.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/18.pwrmgr_escalation_timeout.4025896243
Short name T329
Test name
Test status
Simulation time 323753611 ps
CPU time 0.96 seconds
Started Jul 30 06:41:09 PM PDT 24
Finished Jul 30 06:41:21 PM PDT 24
Peak memory 198456 kb
Host smart-dd79e531-45c6-42b0-9cf9-ca893a370f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025896243 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_escalation_timeout.4025896243
Directory /workspace/18.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/18.pwrmgr_glitch.2176894093
Short name T573
Test name
Test status
Simulation time 39349838 ps
CPU time 0.61 seconds
Started Jul 30 06:42:15 PM PDT 24
Finished Jul 30 06:42:16 PM PDT 24
Peak memory 195160 kb
Host smart-3c4dd467-5729-4bc8-af62-5d830ef4a0eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176894093 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_glitch.2176894093
Directory /workspace/18.pwrmgr_glitch/latest

Test location /workspace/coverage/default/18.pwrmgr_global_esc.2132761286
Short name T379
Test name
Test status
Simulation time 89135343 ps
CPU time 0.61 seconds
Started Jul 30 06:41:07 PM PDT 24
Finished Jul 30 06:41:08 PM PDT 24
Peak memory 198424 kb
Host smart-f3d9c31a-c7ff-4a23-a568-5db7ecd12ac8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132761286 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_global_esc.2132761286
Directory /workspace/18.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/18.pwrmgr_lowpower_invalid.3660036133
Short name T510
Test name
Test status
Simulation time 45204588 ps
CPU time 0.75 seconds
Started Jul 30 06:41:11 PM PDT 24
Finished Jul 30 06:41:12 PM PDT 24
Peak memory 201372 kb
Host smart-cf36b630-fd8b-40eb-b31d-28cc30e65bac
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660036133 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_lowpower_inval
id.3660036133
Directory /workspace/18.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/18.pwrmgr_lowpower_wakeup_race.735598949
Short name T206
Test name
Test status
Simulation time 73191589 ps
CPU time 0.63 seconds
Started Jul 30 06:41:11 PM PDT 24
Finished Jul 30 06:41:11 PM PDT 24
Peak memory 198172 kb
Host smart-838c468d-f1d3-4f79-9d53-cef86b32b97d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735598949 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_lowpower_wa
keup_race.735598949
Directory /workspace/18.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/18.pwrmgr_reset.760727926
Short name T444
Test name
Test status
Simulation time 37107848 ps
CPU time 0.72 seconds
Started Jul 30 06:41:04 PM PDT 24
Finished Jul 30 06:41:05 PM PDT 24
Peak memory 199188 kb
Host smart-44054c4f-c1c2-4a67-bd55-26f9ff8fd21f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760727926 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset.760727926
Directory /workspace/18.pwrmgr_reset/latest

Test location /workspace/coverage/default/18.pwrmgr_reset_invalid.1792346789
Short name T370
Test name
Test status
Simulation time 163287430 ps
CPU time 0.77 seconds
Started Jul 30 06:41:06 PM PDT 24
Finished Jul 30 06:41:07 PM PDT 24
Peak memory 201332 kb
Host smart-943b3bd7-3087-4398-ade7-4a0e88d739b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792346789 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset_invalid.1792346789
Directory /workspace/18.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/18.pwrmgr_sec_cm_rstmgr_intersig_mubi.959611315
Short name T461
Test name
Test status
Simulation time 118945586 ps
CPU time 0.76 seconds
Started Jul 30 06:41:06 PM PDT 24
Finished Jul 30 06:41:06 PM PDT 24
Peak memory 197932 kb
Host smart-7e0d3994-44d4-49a5-8783-0bf86a2bb1e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959611315 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_rstmgr_intersig_
mubi.959611315
Directory /workspace/18.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/18.pwrmgr_smoke.1144722086
Short name T284
Test name
Test status
Simulation time 30492940 ps
CPU time 0.65 seconds
Started Jul 30 06:41:08 PM PDT 24
Finished Jul 30 06:41:08 PM PDT 24
Peak memory 198508 kb
Host smart-65f34008-6e4d-48cb-a094-dcadaed8bfa0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144722086 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_smoke.1144722086
Directory /workspace/18.pwrmgr_smoke/latest

Test location /workspace/coverage/default/19.pwrmgr_aborted_low_power.403025102
Short name T595
Test name
Test status
Simulation time 68842959 ps
CPU time 0.81 seconds
Started Jul 30 06:41:07 PM PDT 24
Finished Jul 30 06:41:12 PM PDT 24
Peak memory 200276 kb
Host smart-a035666c-bae8-4f79-ada8-a89e3a538a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403025102 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_aborted_low_power.403025102
Directory /workspace/19.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/19.pwrmgr_esc_clk_rst_malfunc.2141734913
Short name T133
Test name
Test status
Simulation time 29984157 ps
CPU time 0.62 seconds
Started Jul 30 06:41:04 PM PDT 24
Finished Jul 30 06:41:05 PM PDT 24
Peak memory 198092 kb
Host smart-1a3a4cee-d606-4e51-9255-99d9a7bfdf54
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141734913 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_esc_clk_rst
_malfunc.2141734913
Directory /workspace/19.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/19.pwrmgr_escalation_timeout.2100896720
Short name T512
Test name
Test status
Simulation time 936577736 ps
CPU time 0.93 seconds
Started Jul 30 06:41:05 PM PDT 24
Finished Jul 30 06:41:06 PM PDT 24
Peak memory 198132 kb
Host smart-c4a199c7-d0fd-4baa-805c-cb6362cba772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100896720 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_escalation_timeout.2100896720
Directory /workspace/19.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/19.pwrmgr_glitch.2411898938
Short name T571
Test name
Test status
Simulation time 23006705 ps
CPU time 0.62 seconds
Started Jul 30 06:41:05 PM PDT 24
Finished Jul 30 06:41:05 PM PDT 24
Peak memory 198172 kb
Host smart-812cd754-955c-4d2f-92fd-76ffb86166b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411898938 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_glitch.2411898938
Directory /workspace/19.pwrmgr_glitch/latest

Test location /workspace/coverage/default/19.pwrmgr_global_esc.1931075740
Short name T47
Test name
Test status
Simulation time 36376704 ps
CPU time 0.63 seconds
Started Jul 30 06:42:15 PM PDT 24
Finished Jul 30 06:42:16 PM PDT 24
Peak memory 196964 kb
Host smart-3d1d9292-a90c-45b4-b836-a7f8e9188353
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931075740 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_global_esc.1931075740
Directory /workspace/19.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/19.pwrmgr_lowpower_invalid.3044801248
Short name T175
Test name
Test status
Simulation time 243933281 ps
CPU time 0.65 seconds
Started Jul 30 06:41:12 PM PDT 24
Finished Jul 30 06:41:12 PM PDT 24
Peak memory 201424 kb
Host smart-1e9b9510-4ff9-4d1e-8e55-43977abc78d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044801248 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_lowpower_inval
id.3044801248
Directory /workspace/19.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/19.pwrmgr_reset.1132592106
Short name T5
Test name
Test status
Simulation time 41650571 ps
CPU time 0.75 seconds
Started Jul 30 06:41:10 PM PDT 24
Finished Jul 30 06:41:10 PM PDT 24
Peak memory 199236 kb
Host smart-602c3bf3-e223-46d4-b353-b6dee02c250c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132592106 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset.1132592106
Directory /workspace/19.pwrmgr_reset/latest

Test location /workspace/coverage/default/19.pwrmgr_reset_invalid.3191481214
Short name T211
Test name
Test status
Simulation time 152019759 ps
CPU time 0.81 seconds
Started Jul 30 06:41:06 PM PDT 24
Finished Jul 30 06:41:07 PM PDT 24
Peak memory 209700 kb
Host smart-50ca03b5-f5f2-4bc9-9b4b-26d47a34271e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191481214 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset_invalid.3191481214
Directory /workspace/19.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/19.pwrmgr_sec_cm_rstmgr_intersig_mubi.2388122673
Short name T576
Test name
Test status
Simulation time 76601351 ps
CPU time 0.82 seconds
Started Jul 30 06:41:10 PM PDT 24
Finished Jul 30 06:41:11 PM PDT 24
Peak memory 198160 kb
Host smart-4ebf514f-3a7a-4117-83dd-55a7dd75bfd1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388122673 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2388122673
Directory /workspace/19.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/19.pwrmgr_smoke.4056879454
Short name T257
Test name
Test status
Simulation time 32164958 ps
CPU time 0.71 seconds
Started Jul 30 06:41:08 PM PDT 24
Finished Jul 30 06:41:09 PM PDT 24
Peak memory 199344 kb
Host smart-00ebbd20-f62c-4c19-89a2-16010e429e8e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056879454 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_smoke.4056879454
Directory /workspace/19.pwrmgr_smoke/latest

Test location /workspace/coverage/default/2.pwrmgr_aborted_low_power.1554133133
Short name T594
Test name
Test status
Simulation time 21314801 ps
CPU time 0.74 seconds
Started Jul 30 06:40:29 PM PDT 24
Finished Jul 30 06:40:30 PM PDT 24
Peak memory 199248 kb
Host smart-e5121168-0bb2-4e1d-9339-7fde81c3c5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554133133 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_aborted_low_power.1554133133
Directory /workspace/2.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/2.pwrmgr_esc_clk_rst_malfunc.1470539438
Short name T361
Test name
Test status
Simulation time 32798131 ps
CPU time 0.58 seconds
Started Jul 30 06:40:25 PM PDT 24
Finished Jul 30 06:40:26 PM PDT 24
Peak memory 198040 kb
Host smart-c04175e4-e8d2-4a4e-84e2-89965d945bb8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470539438 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_esc_clk_rst_
malfunc.1470539438
Directory /workspace/2.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/2.pwrmgr_escalation_timeout.2247696197
Short name T553
Test name
Test status
Simulation time 159880787 ps
CPU time 1.09 seconds
Started Jul 30 06:40:28 PM PDT 24
Finished Jul 30 06:40:29 PM PDT 24
Peak memory 198112 kb
Host smart-27f7cdbb-749f-4916-95e5-76e6b6cd43a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247696197 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_escalation_timeout.2247696197
Directory /workspace/2.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/2.pwrmgr_glitch.4233314367
Short name T618
Test name
Test status
Simulation time 35529579 ps
CPU time 0.63 seconds
Started Jul 30 06:40:25 PM PDT 24
Finished Jul 30 06:40:26 PM PDT 24
Peak memory 198052 kb
Host smart-67cb8191-08fe-48b9-8ba8-3fc757987f4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233314367 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_glitch.4233314367
Directory /workspace/2.pwrmgr_glitch/latest

Test location /workspace/coverage/default/2.pwrmgr_global_esc.994443080
Short name T226
Test name
Test status
Simulation time 54652998 ps
CPU time 0.57 seconds
Started Jul 30 06:40:30 PM PDT 24
Finished Jul 30 06:40:31 PM PDT 24
Peak memory 198364 kb
Host smart-30e77d7f-73f2-461e-aabc-c2ea7a84f9f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994443080 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_global_esc.994443080
Directory /workspace/2.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/2.pwrmgr_lowpower_invalid.1508327822
Short name T176
Test name
Test status
Simulation time 54190185 ps
CPU time 0.7 seconds
Started Jul 30 06:40:24 PM PDT 24
Finished Jul 30 06:40:25 PM PDT 24
Peak memory 201476 kb
Host smart-d5605210-5c3c-4824-9ffb-db7b19394bef
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508327822 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_lowpower_invali
d.1508327822
Directory /workspace/2.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/2.pwrmgr_reset.3400912626
Short name T216
Test name
Test status
Simulation time 118823287 ps
CPU time 0.72 seconds
Started Jul 30 06:40:26 PM PDT 24
Finished Jul 30 06:40:27 PM PDT 24
Peak memory 199172 kb
Host smart-61264070-5df8-487c-acce-6229e4f2394c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400912626 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset.3400912626
Directory /workspace/2.pwrmgr_reset/latest

Test location /workspace/coverage/default/2.pwrmgr_reset_invalid.1833937459
Short name T322
Test name
Test status
Simulation time 178096958 ps
CPU time 0.78 seconds
Started Jul 30 06:40:26 PM PDT 24
Finished Jul 30 06:40:26 PM PDT 24
Peak memory 209564 kb
Host smart-d1133cbe-0b14-4cd0-9e98-e61fd582fdc9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833937459 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset_invalid.1833937459
Directory /workspace/2.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm.269130824
Short name T30
Test name
Test status
Simulation time 1136199321 ps
CPU time 1.46 seconds
Started Jul 30 06:40:27 PM PDT 24
Finished Jul 30 06:40:28 PM PDT 24
Peak memory 218096 kb
Host smart-cbbcfe17-9540-462f-bab9-91065fcc230c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269130824 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm.269130824
Directory /workspace/2.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm_rstmgr_intersig_mubi.2605683847
Short name T402
Test name
Test status
Simulation time 59970650 ps
CPU time 0.74 seconds
Started Jul 30 06:40:23 PM PDT 24
Finished Jul 30 06:40:24 PM PDT 24
Peak memory 198176 kb
Host smart-c44886f5-9b6d-4495-8790-d66729d7d5f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605683847 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2605683847
Directory /workspace/2.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/2.pwrmgr_smoke.693417390
Short name T545
Test name
Test status
Simulation time 39406264 ps
CPU time 0.66 seconds
Started Jul 30 06:40:28 PM PDT 24
Finished Jul 30 06:40:28 PM PDT 24
Peak memory 199420 kb
Host smart-cdc0cd22-a533-4d4b-b1c8-981f1b1162f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693417390 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_smoke.693417390
Directory /workspace/2.pwrmgr_smoke/latest

Test location /workspace/coverage/default/20.pwrmgr_disable_rom_integrity_check.3113907209
Short name T150
Test name
Test status
Simulation time 72497110 ps
CPU time 0.72 seconds
Started Jul 30 06:41:18 PM PDT 24
Finished Jul 30 06:41:18 PM PDT 24
Peak memory 199168 kb
Host smart-d2e75b76-fa1e-46d9-bf54-157b5e6745a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113907209 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_dis
able_rom_integrity_check.3113907209
Directory /workspace/20.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/20.pwrmgr_esc_clk_rst_malfunc.939201741
Short name T543
Test name
Test status
Simulation time 30032726 ps
CPU time 0.62 seconds
Started Jul 30 06:41:09 PM PDT 24
Finished Jul 30 06:41:10 PM PDT 24
Peak memory 198056 kb
Host smart-9c907ed4-b7f0-4d29-b629-b496defb461b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939201741 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_esc_clk_rst_
malfunc.939201741
Directory /workspace/20.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/20.pwrmgr_escalation_timeout.2088695866
Short name T509
Test name
Test status
Simulation time 726138546 ps
CPU time 0.97 seconds
Started Jul 30 06:41:09 PM PDT 24
Finished Jul 30 06:41:11 PM PDT 24
Peak memory 198056 kb
Host smart-8e306bf3-f469-4229-8cad-a5db3f2db317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088695866 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_escalation_timeout.2088695866
Directory /workspace/20.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/20.pwrmgr_glitch.1969253905
Short name T472
Test name
Test status
Simulation time 46466742 ps
CPU time 0.61 seconds
Started Jul 30 06:41:09 PM PDT 24
Finished Jul 30 06:41:10 PM PDT 24
Peak memory 197476 kb
Host smart-ebb44e61-b1c0-45dd-bccc-320ebe0641e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969253905 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_glitch.1969253905
Directory /workspace/20.pwrmgr_glitch/latest

Test location /workspace/coverage/default/20.pwrmgr_global_esc.1436755927
Short name T622
Test name
Test status
Simulation time 83340097 ps
CPU time 0.59 seconds
Started Jul 30 06:41:07 PM PDT 24
Finished Jul 30 06:41:08 PM PDT 24
Peak memory 198140 kb
Host smart-d601d58a-7d73-4b8a-83de-250c6198df70
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436755927 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_global_esc.1436755927
Directory /workspace/20.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/20.pwrmgr_lowpower_invalid.3062488144
Short name T192
Test name
Test status
Simulation time 88680083 ps
CPU time 0.67 seconds
Started Jul 30 06:41:12 PM PDT 24
Finished Jul 30 06:41:13 PM PDT 24
Peak memory 201596 kb
Host smart-9481001c-4e71-4a66-966d-e61bc0414d31
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062488144 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_lowpower_inval
id.3062488144
Directory /workspace/20.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/20.pwrmgr_reset.1484835814
Short name T315
Test name
Test status
Simulation time 70105672 ps
CPU time 0.68 seconds
Started Jul 30 06:41:08 PM PDT 24
Finished Jul 30 06:41:08 PM PDT 24
Peak memory 199112 kb
Host smart-d443c520-7657-4a26-ba05-f5c2911f7490
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484835814 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset.1484835814
Directory /workspace/20.pwrmgr_reset/latest

Test location /workspace/coverage/default/20.pwrmgr_reset_invalid.2851574087
Short name T378
Test name
Test status
Simulation time 287451810 ps
CPU time 0.78 seconds
Started Jul 30 06:41:14 PM PDT 24
Finished Jul 30 06:41:15 PM PDT 24
Peak memory 209576 kb
Host smart-3281d4e3-c8ba-4cb1-9818-3882746e4a9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851574087 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset_invalid.2851574087
Directory /workspace/20.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/20.pwrmgr_sec_cm_rstmgr_intersig_mubi.3404001846
Short name T33
Test name
Test status
Simulation time 101342491 ps
CPU time 0.69 seconds
Started Jul 30 06:41:08 PM PDT 24
Finished Jul 30 06:41:09 PM PDT 24
Peak memory 198112 kb
Host smart-2532f65d-fd44-4439-8946-52056e90e8a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404001846 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3404001846
Directory /workspace/20.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/20.pwrmgr_smoke.879478989
Short name T84
Test name
Test status
Simulation time 52334315 ps
CPU time 0.61 seconds
Started Jul 30 06:41:09 PM PDT 24
Finished Jul 30 06:41:10 PM PDT 24
Peak memory 199428 kb
Host smart-4396e238-a0d3-4638-b3f4-efb2cde2d8b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879478989 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_smoke.879478989
Directory /workspace/20.pwrmgr_smoke/latest

Test location /workspace/coverage/default/21.pwrmgr_aborted_low_power.626640412
Short name T555
Test name
Test status
Simulation time 26335129 ps
CPU time 0.78 seconds
Started Jul 30 06:41:14 PM PDT 24
Finished Jul 30 06:41:15 PM PDT 24
Peak memory 200152 kb
Host smart-75f44173-3cc2-4651-bc1d-ff85b2697a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626640412 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_aborted_low_power.626640412
Directory /workspace/21.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/21.pwrmgr_disable_rom_integrity_check.3979519253
Short name T518
Test name
Test status
Simulation time 68879949 ps
CPU time 0.69 seconds
Started Jul 30 06:41:19 PM PDT 24
Finished Jul 30 06:41:21 PM PDT 24
Peak memory 198500 kb
Host smart-6c7b843d-1477-4685-8a44-6dd5a67dfee3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979519253 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_dis
able_rom_integrity_check.3979519253
Directory /workspace/21.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/21.pwrmgr_esc_clk_rst_malfunc.453760227
Short name T491
Test name
Test status
Simulation time 37783909 ps
CPU time 0.58 seconds
Started Jul 30 06:41:12 PM PDT 24
Finished Jul 30 06:41:12 PM PDT 24
Peak memory 198092 kb
Host smart-a74c78b8-fea6-4727-9048-0ce7ed10a343
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453760227 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_esc_clk_rst_
malfunc.453760227
Directory /workspace/21.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/21.pwrmgr_escalation_timeout.2072213750
Short name T259
Test name
Test status
Simulation time 640272345 ps
CPU time 0.94 seconds
Started Jul 30 06:41:25 PM PDT 24
Finished Jul 30 06:41:26 PM PDT 24
Peak memory 198116 kb
Host smart-1aa86807-2021-475b-b310-36796e6f97e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072213750 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_escalation_timeout.2072213750
Directory /workspace/21.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/21.pwrmgr_glitch.77735322
Short name T219
Test name
Test status
Simulation time 79395241 ps
CPU time 0.62 seconds
Started Jul 30 06:41:09 PM PDT 24
Finished Jul 30 06:41:10 PM PDT 24
Peak memory 198000 kb
Host smart-d3475178-5526-4d38-af81-963876d018c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77735322 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_glitch.77735322
Directory /workspace/21.pwrmgr_glitch/latest

Test location /workspace/coverage/default/21.pwrmgr_global_esc.3439403833
Short name T623
Test name
Test status
Simulation time 43981004 ps
CPU time 0.63 seconds
Started Jul 30 06:41:20 PM PDT 24
Finished Jul 30 06:41:21 PM PDT 24
Peak memory 198096 kb
Host smart-6ca1583e-4281-4702-9093-d6ff9a76a18f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439403833 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_global_esc.3439403833
Directory /workspace/21.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/21.pwrmgr_lowpower_invalid.4274116286
Short name T196
Test name
Test status
Simulation time 55418435 ps
CPU time 0.72 seconds
Started Jul 30 06:41:10 PM PDT 24
Finished Jul 30 06:41:11 PM PDT 24
Peak memory 201440 kb
Host smart-d70d5120-5025-4ad3-8dbd-3c70288eb949
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274116286 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_lowpower_inval
id.4274116286
Directory /workspace/21.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/21.pwrmgr_reset.2283445471
Short name T366
Test name
Test status
Simulation time 90425475 ps
CPU time 0.67 seconds
Started Jul 30 06:41:10 PM PDT 24
Finished Jul 30 06:41:11 PM PDT 24
Peak memory 198372 kb
Host smart-7d10f69a-efd8-4ee4-9dfd-07ddc07bf60e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283445471 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset.2283445471
Directory /workspace/21.pwrmgr_reset/latest

Test location /workspace/coverage/default/21.pwrmgr_reset_invalid.3835932609
Short name T455
Test name
Test status
Simulation time 317076967 ps
CPU time 0.74 seconds
Started Jul 30 06:41:19 PM PDT 24
Finished Jul 30 06:41:21 PM PDT 24
Peak memory 209508 kb
Host smart-a5522870-0059-4b13-8f41-19e1daea2b42
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835932609 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset_invalid.3835932609
Directory /workspace/21.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/21.pwrmgr_sec_cm_ctrl_config_regwen.1713412083
Short name T62
Test name
Test status
Simulation time 66432474 ps
CPU time 0.64 seconds
Started Jul 30 06:41:12 PM PDT 24
Finished Jul 30 06:41:13 PM PDT 24
Peak memory 198600 kb
Host smart-2fc1321d-3cb8-40e1-bbb6-b16f71ee2947
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713412083 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_
cm_ctrl_config_regwen.1713412083
Directory /workspace/21.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/21.pwrmgr_sec_cm_rstmgr_intersig_mubi.383846619
Short name T276
Test name
Test status
Simulation time 72310782 ps
CPU time 0.8 seconds
Started Jul 30 06:41:09 PM PDT 24
Finished Jul 30 06:41:10 PM PDT 24
Peak memory 197992 kb
Host smart-e999c7a9-1dac-45fd-afcd-95196663069e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383846619 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_rstmgr_intersig_
mubi.383846619
Directory /workspace/21.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/21.pwrmgr_smoke.2783877060
Short name T398
Test name
Test status
Simulation time 37452860 ps
CPU time 0.67 seconds
Started Jul 30 06:41:12 PM PDT 24
Finished Jul 30 06:41:13 PM PDT 24
Peak memory 199360 kb
Host smart-28e98f4a-3976-4251-a056-e8aa242b5fef
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783877060 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_smoke.2783877060
Directory /workspace/21.pwrmgr_smoke/latest

Test location /workspace/coverage/default/22.pwrmgr_aborted_low_power.1928725880
Short name T435
Test name
Test status
Simulation time 91819731 ps
CPU time 0.62 seconds
Started Jul 30 06:41:12 PM PDT 24
Finished Jul 30 06:41:13 PM PDT 24
Peak memory 198568 kb
Host smart-2e18fc39-7394-46fe-834d-5b711ccdcd6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928725880 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_aborted_low_power.1928725880
Directory /workspace/22.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/22.pwrmgr_disable_rom_integrity_check.2388591712
Short name T163
Test name
Test status
Simulation time 56454059 ps
CPU time 0.82 seconds
Started Jul 30 06:41:20 PM PDT 24
Finished Jul 30 06:41:21 PM PDT 24
Peak memory 198596 kb
Host smart-7ea6fa00-2866-43c3-a278-c1e66b05f523
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388591712 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_dis
able_rom_integrity_check.2388591712
Directory /workspace/22.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/22.pwrmgr_esc_clk_rst_malfunc.3742062641
Short name T328
Test name
Test status
Simulation time 45187023 ps
CPU time 0.6 seconds
Started Jul 30 06:41:14 PM PDT 24
Finished Jul 30 06:41:14 PM PDT 24
Peak memory 198012 kb
Host smart-95bfac8a-af71-42fd-b81f-8d8a5069aca1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742062641 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_esc_clk_rst
_malfunc.3742062641
Directory /workspace/22.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/22.pwrmgr_escalation_timeout.2922566592
Short name T460
Test name
Test status
Simulation time 168866176 ps
CPU time 1 seconds
Started Jul 30 06:41:14 PM PDT 24
Finished Jul 30 06:41:15 PM PDT 24
Peak memory 198416 kb
Host smart-2e49a7ce-decb-40d8-b0ad-e43e77a4a893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922566592 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_escalation_timeout.2922566592
Directory /workspace/22.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/22.pwrmgr_glitch.2884906925
Short name T602
Test name
Test status
Simulation time 43324200 ps
CPU time 0.69 seconds
Started Jul 30 06:41:19 PM PDT 24
Finished Jul 30 06:41:20 PM PDT 24
Peak memory 198100 kb
Host smart-12feff46-a726-4a36-82df-d468c9390847
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884906925 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_glitch.2884906925
Directory /workspace/22.pwrmgr_glitch/latest

Test location /workspace/coverage/default/22.pwrmgr_global_esc.627352661
Short name T349
Test name
Test status
Simulation time 68727487 ps
CPU time 0.6 seconds
Started Jul 30 06:41:12 PM PDT 24
Finished Jul 30 06:41:13 PM PDT 24
Peak memory 198392 kb
Host smart-3ab26da5-c1e6-4398-8e71-0cf17735c2fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627352661 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_global_esc.627352661
Directory /workspace/22.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/22.pwrmgr_lowpower_invalid.518020969
Short name T189
Test name
Test status
Simulation time 43331846 ps
CPU time 0.72 seconds
Started Jul 30 06:41:25 PM PDT 24
Finished Jul 30 06:41:26 PM PDT 24
Peak memory 201444 kb
Host smart-158e24d5-31a0-42d7-bb81-af0559150afd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518020969 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_lowpower_invali
d.518020969
Directory /workspace/22.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/22.pwrmgr_reset.1126493829
Short name T225
Test name
Test status
Simulation time 48921388 ps
CPU time 0.77 seconds
Started Jul 30 06:41:12 PM PDT 24
Finished Jul 30 06:41:13 PM PDT 24
Peak memory 199152 kb
Host smart-c3215e7f-793f-4d42-b708-0d15ee35b2d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126493829 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset.1126493829
Directory /workspace/22.pwrmgr_reset/latest

Test location /workspace/coverage/default/22.pwrmgr_reset_invalid.168941157
Short name T235
Test name
Test status
Simulation time 100973557 ps
CPU time 0.96 seconds
Started Jul 30 06:41:16 PM PDT 24
Finished Jul 30 06:41:17 PM PDT 24
Peak memory 209584 kb
Host smart-83391df8-32b0-4ac1-87a0-dbb5a0e0080b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168941157 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset_invalid.168941157
Directory /workspace/22.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/22.pwrmgr_sec_cm_rstmgr_intersig_mubi.3339515064
Short name T464
Test name
Test status
Simulation time 67727343 ps
CPU time 0.88 seconds
Started Jul 30 06:41:15 PM PDT 24
Finished Jul 30 06:41:16 PM PDT 24
Peak memory 199080 kb
Host smart-496ab4d0-6c8f-4817-b2e7-371170cfe860
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339515064 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3339515064
Directory /workspace/22.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/22.pwrmgr_smoke.810731825
Short name T246
Test name
Test status
Simulation time 32309005 ps
CPU time 0.65 seconds
Started Jul 30 06:41:10 PM PDT 24
Finished Jul 30 06:41:10 PM PDT 24
Peak memory 199340 kb
Host smart-a0c8cd83-2ec4-4bd4-96fd-9fe56330c1b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810731825 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_smoke.810731825
Directory /workspace/22.pwrmgr_smoke/latest

Test location /workspace/coverage/default/23.pwrmgr_aborted_low_power.3162156976
Short name T481
Test name
Test status
Simulation time 41100429 ps
CPU time 0.59 seconds
Started Jul 30 06:41:24 PM PDT 24
Finished Jul 30 06:41:25 PM PDT 24
Peak memory 198560 kb
Host smart-00859de6-ccdd-4214-af99-be342bde260f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162156976 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_aborted_low_power.3162156976
Directory /workspace/23.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/23.pwrmgr_esc_clk_rst_malfunc.2406702449
Short name T362
Test name
Test status
Simulation time 28415154 ps
CPU time 0.64 seconds
Started Jul 30 06:41:14 PM PDT 24
Finished Jul 30 06:41:14 PM PDT 24
Peak memory 198032 kb
Host smart-34f887b2-4afd-480d-bd68-3a479992eb0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406702449 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_esc_clk_rst
_malfunc.2406702449
Directory /workspace/23.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/23.pwrmgr_escalation_timeout.3727841
Short name T539
Test name
Test status
Simulation time 635384879 ps
CPU time 0.96 seconds
Started Jul 30 06:41:14 PM PDT 24
Finished Jul 30 06:41:15 PM PDT 24
Peak memory 198116 kb
Host smart-8c748732-fd20-4c64-9018-8ff5c07d23e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727841 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_escalation_timeout.3727841
Directory /workspace/23.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/23.pwrmgr_glitch.1067934534
Short name T307
Test name
Test status
Simulation time 63639647 ps
CPU time 0.7 seconds
Started Jul 30 06:41:14 PM PDT 24
Finished Jul 30 06:41:15 PM PDT 24
Peak memory 198064 kb
Host smart-acb78ad2-79d4-4651-87da-56ea74901127
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067934534 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_glitch.1067934534
Directory /workspace/23.pwrmgr_glitch/latest

Test location /workspace/coverage/default/23.pwrmgr_global_esc.582261654
Short name T297
Test name
Test status
Simulation time 24167091 ps
CPU time 0.61 seconds
Started Jul 30 06:41:19 PM PDT 24
Finished Jul 30 06:41:20 PM PDT 24
Peak memory 198076 kb
Host smart-f9afbfc8-4d06-4b45-a586-88194e7bc276
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582261654 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_global_esc.582261654
Directory /workspace/23.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/23.pwrmgr_lowpower_invalid.4212831081
Short name T204
Test name
Test status
Simulation time 80063182 ps
CPU time 0.79 seconds
Started Jul 30 06:41:18 PM PDT 24
Finished Jul 30 06:41:19 PM PDT 24
Peak memory 201424 kb
Host smart-b93e4c61-a503-4425-afa0-1b745133af9e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212831081 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_lowpower_inval
id.4212831081
Directory /workspace/23.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/23.pwrmgr_reset.1889888308
Short name T419
Test name
Test status
Simulation time 89054854 ps
CPU time 0.8 seconds
Started Jul 30 06:41:15 PM PDT 24
Finished Jul 30 06:41:16 PM PDT 24
Peak memory 199180 kb
Host smart-12ce5a24-d085-4f78-b2d0-cea11cc4e7db
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889888308 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset.1889888308
Directory /workspace/23.pwrmgr_reset/latest

Test location /workspace/coverage/default/23.pwrmgr_reset_invalid.933840383
Short name T475
Test name
Test status
Simulation time 121437395 ps
CPU time 0.83 seconds
Started Jul 30 06:41:17 PM PDT 24
Finished Jul 30 06:41:18 PM PDT 24
Peak memory 209500 kb
Host smart-0eb84426-0531-4671-9a88-3d3993100467
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933840383 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset_invalid.933840383
Directory /workspace/23.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/23.pwrmgr_sec_cm_rstmgr_intersig_mubi.3379701763
Short name T560
Test name
Test status
Simulation time 55788214 ps
CPU time 0.79 seconds
Started Jul 30 06:41:21 PM PDT 24
Finished Jul 30 06:41:22 PM PDT 24
Peak memory 198156 kb
Host smart-2098a601-b1e9-4984-a97b-ecc63bf59ae4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379701763 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3379701763
Directory /workspace/23.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/23.pwrmgr_smoke.438044149
Short name T82
Test name
Test status
Simulation time 31688999 ps
CPU time 0.7 seconds
Started Jul 30 06:41:13 PM PDT 24
Finished Jul 30 06:41:14 PM PDT 24
Peak memory 199384 kb
Host smart-1592cf7f-7ec9-4e79-bfb0-bfd5a33301ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438044149 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_smoke.438044149
Directory /workspace/23.pwrmgr_smoke/latest

Test location /workspace/coverage/default/24.pwrmgr_aborted_low_power.657394418
Short name T544
Test name
Test status
Simulation time 68870836 ps
CPU time 0.78 seconds
Started Jul 30 06:41:30 PM PDT 24
Finished Jul 30 06:41:30 PM PDT 24
Peak memory 199180 kb
Host smart-7df0c24f-d4d3-4eed-aa1f-59b293bc89b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657394418 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_aborted_low_power.657394418
Directory /workspace/24.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/24.pwrmgr_disable_rom_integrity_check.2753550154
Short name T614
Test name
Test status
Simulation time 106759918 ps
CPU time 0.61 seconds
Started Jul 30 06:41:33 PM PDT 24
Finished Jul 30 06:41:33 PM PDT 24
Peak memory 198392 kb
Host smart-297e5f33-660b-4402-91d8-c4f074f634b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753550154 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_dis
able_rom_integrity_check.2753550154
Directory /workspace/24.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/24.pwrmgr_esc_clk_rst_malfunc.3418732490
Short name T600
Test name
Test status
Simulation time 41937164 ps
CPU time 0.61 seconds
Started Jul 30 06:41:32 PM PDT 24
Finished Jul 30 06:41:33 PM PDT 24
Peak memory 198012 kb
Host smart-58d0f582-e7d8-483c-add8-543637ce7f29
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418732490 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_esc_clk_rst
_malfunc.3418732490
Directory /workspace/24.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/24.pwrmgr_escalation_timeout.4018090411
Short name T540
Test name
Test status
Simulation time 316973537 ps
CPU time 0.97 seconds
Started Jul 30 06:41:35 PM PDT 24
Finished Jul 30 06:41:36 PM PDT 24
Peak memory 198072 kb
Host smart-6445e053-4819-4ef0-92c1-b663c2477237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018090411 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_escalation_timeout.4018090411
Directory /workspace/24.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/24.pwrmgr_glitch.3488478133
Short name T437
Test name
Test status
Simulation time 29982707 ps
CPU time 0.61 seconds
Started Jul 30 06:41:26 PM PDT 24
Finished Jul 30 06:41:27 PM PDT 24
Peak memory 198124 kb
Host smart-dbe2c47c-1380-4bfa-9300-cc0893a1f42b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488478133 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_glitch.3488478133
Directory /workspace/24.pwrmgr_glitch/latest

Test location /workspace/coverage/default/24.pwrmgr_global_esc.3631066212
Short name T266
Test name
Test status
Simulation time 43341668 ps
CPU time 0.61 seconds
Started Jul 30 06:41:32 PM PDT 24
Finished Jul 30 06:41:33 PM PDT 24
Peak memory 197984 kb
Host smart-9ddda6fa-bf42-478f-b3f6-55be1cf20f33
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631066212 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_global_esc.3631066212
Directory /workspace/24.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/24.pwrmgr_lowpower_invalid.1558689692
Short name T170
Test name
Test status
Simulation time 74472971 ps
CPU time 0.67 seconds
Started Jul 30 06:41:39 PM PDT 24
Finished Jul 30 06:41:40 PM PDT 24
Peak memory 201352 kb
Host smart-f804a0ff-ac64-4f2e-aab3-49977ff5d381
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558689692 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_lowpower_inval
id.1558689692
Directory /workspace/24.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/24.pwrmgr_reset.1878936176
Short name T242
Test name
Test status
Simulation time 52116129 ps
CPU time 0.8 seconds
Started Jul 30 06:41:11 PM PDT 24
Finished Jul 30 06:41:12 PM PDT 24
Peak memory 199108 kb
Host smart-b5d98b0e-b200-4f61-9d5d-ee82df36a63e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878936176 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset.1878936176
Directory /workspace/24.pwrmgr_reset/latest

Test location /workspace/coverage/default/24.pwrmgr_sec_cm_rstmgr_intersig_mubi.2521726893
Short name T316
Test name
Test status
Simulation time 54250784 ps
CPU time 0.84 seconds
Started Jul 30 06:41:44 PM PDT 24
Finished Jul 30 06:41:45 PM PDT 24
Peak memory 198140 kb
Host smart-6853ae59-8223-4460-ac7f-c1a0864998d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521726893 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2521726893
Directory /workspace/24.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/24.pwrmgr_smoke.2429113933
Short name T83
Test name
Test status
Simulation time 56169949 ps
CPU time 0.63 seconds
Started Jul 30 06:41:18 PM PDT 24
Finished Jul 30 06:41:19 PM PDT 24
Peak memory 198512 kb
Host smart-97c5dc75-ec16-475e-927a-3dad7284b0c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429113933 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_smoke.2429113933
Directory /workspace/24.pwrmgr_smoke/latest

Test location /workspace/coverage/default/25.pwrmgr_aborted_low_power.2307736134
Short name T55
Test name
Test status
Simulation time 91721199 ps
CPU time 0.73 seconds
Started Jul 30 06:41:33 PM PDT 24
Finished Jul 30 06:41:34 PM PDT 24
Peak memory 198932 kb
Host smart-f813c2e0-cf88-475a-81ad-a0ea6e37c254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307736134 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_aborted_low_power.2307736134
Directory /workspace/25.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/25.pwrmgr_disable_rom_integrity_check.1986353869
Short name T551
Test name
Test status
Simulation time 70754004 ps
CPU time 0.76 seconds
Started Jul 30 06:41:33 PM PDT 24
Finished Jul 30 06:41:34 PM PDT 24
Peak memory 198604 kb
Host smart-7361d029-30d2-4043-b770-3fc9a03ee35a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986353869 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_dis
able_rom_integrity_check.1986353869
Directory /workspace/25.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/25.pwrmgr_esc_clk_rst_malfunc.2029476135
Short name T439
Test name
Test status
Simulation time 29887514 ps
CPU time 0.65 seconds
Started Jul 30 06:41:44 PM PDT 24
Finished Jul 30 06:41:45 PM PDT 24
Peak memory 198012 kb
Host smart-cf89fcb9-33f3-41ed-95d5-c9a70d28d331
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029476135 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_esc_clk_rst
_malfunc.2029476135
Directory /workspace/25.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/25.pwrmgr_escalation_timeout.1227099560
Short name T130
Test name
Test status
Simulation time 576293698 ps
CPU time 0.9 seconds
Started Jul 30 06:41:33 PM PDT 24
Finished Jul 30 06:41:34 PM PDT 24
Peak memory 198084 kb
Host smart-63e59296-6870-4a25-8ecd-7f33eb0e9ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227099560 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_escalation_timeout.1227099560
Directory /workspace/25.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/25.pwrmgr_glitch.2775650322
Short name T577
Test name
Test status
Simulation time 76069582 ps
CPU time 0.61 seconds
Started Jul 30 06:41:33 PM PDT 24
Finished Jul 30 06:41:33 PM PDT 24
Peak memory 198156 kb
Host smart-b584be27-3eb9-4ea0-b654-607b48e529a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775650322 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_glitch.2775650322
Directory /workspace/25.pwrmgr_glitch/latest

Test location /workspace/coverage/default/25.pwrmgr_global_esc.2480707565
Short name T563
Test name
Test status
Simulation time 22162965 ps
CPU time 0.61 seconds
Started Jul 30 06:41:33 PM PDT 24
Finished Jul 30 06:41:34 PM PDT 24
Peak memory 198096 kb
Host smart-5a6184b1-1157-42a4-8947-e18388cb2659
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480707565 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_global_esc.2480707565
Directory /workspace/25.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/25.pwrmgr_reset.1631646517
Short name T253
Test name
Test status
Simulation time 69437616 ps
CPU time 0.71 seconds
Started Jul 30 06:41:29 PM PDT 24
Finished Jul 30 06:41:29 PM PDT 24
Peak memory 199116 kb
Host smart-da5396c3-a713-41df-a6e8-ad48c6adc258
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631646517 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset.1631646517
Directory /workspace/25.pwrmgr_reset/latest

Test location /workspace/coverage/default/25.pwrmgr_reset_invalid.665342659
Short name T326
Test name
Test status
Simulation time 126262799 ps
CPU time 0.85 seconds
Started Jul 30 06:41:31 PM PDT 24
Finished Jul 30 06:41:32 PM PDT 24
Peak memory 209508 kb
Host smart-9ed8f811-e7d8-4279-a3b8-58ea25802f33
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665342659 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset_invalid.665342659
Directory /workspace/25.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/25.pwrmgr_sec_cm_rstmgr_intersig_mubi.3226929101
Short name T617
Test name
Test status
Simulation time 62471155 ps
CPU time 0.82 seconds
Started Jul 30 06:41:35 PM PDT 24
Finished Jul 30 06:41:36 PM PDT 24
Peak memory 198376 kb
Host smart-b82520a4-ea9c-4758-b36f-ed95efcca713
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226929101 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3226929101
Directory /workspace/25.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/25.pwrmgr_smoke.1706953852
Short name T516
Test name
Test status
Simulation time 62742566 ps
CPU time 0.63 seconds
Started Jul 30 06:41:30 PM PDT 24
Finished Jul 30 06:41:31 PM PDT 24
Peak memory 199404 kb
Host smart-ef915bbc-f436-407c-a4ef-5fe51b835e50
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706953852 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_smoke.1706953852
Directory /workspace/25.pwrmgr_smoke/latest

Test location /workspace/coverage/default/26.pwrmgr_aborted_low_power.3228390780
Short name T94
Test name
Test status
Simulation time 25358232 ps
CPU time 0.67 seconds
Started Jul 30 06:41:33 PM PDT 24
Finished Jul 30 06:41:34 PM PDT 24
Peak memory 199176 kb
Host smart-048687ae-6473-457e-ad45-cc2037b60c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228390780 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_aborted_low_power.3228390780
Directory /workspace/26.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/26.pwrmgr_disable_rom_integrity_check.419388545
Short name T377
Test name
Test status
Simulation time 97897857 ps
CPU time 0.65 seconds
Started Jul 30 06:41:43 PM PDT 24
Finished Jul 30 06:41:44 PM PDT 24
Peak memory 198464 kb
Host smart-f67b93f0-c21e-4204-8257-82c6d6e2e13b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419388545 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_disa
ble_rom_integrity_check.419388545
Directory /workspace/26.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/26.pwrmgr_esc_clk_rst_malfunc.1847956162
Short name T232
Test name
Test status
Simulation time 35528131 ps
CPU time 0.58 seconds
Started Jul 30 06:41:31 PM PDT 24
Finished Jul 30 06:41:32 PM PDT 24
Peak memory 198268 kb
Host smart-ba34dbff-ad3a-47d3-a08e-5542a1698e14
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847956162 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_esc_clk_rst
_malfunc.1847956162
Directory /workspace/26.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/26.pwrmgr_escalation_timeout.814784759
Short name T128
Test name
Test status
Simulation time 160208466 ps
CPU time 0.96 seconds
Started Jul 30 06:41:38 PM PDT 24
Finished Jul 30 06:41:39 PM PDT 24
Peak memory 198124 kb
Host smart-011da54d-2183-42f8-8fc0-7ab742900a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814784759 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_escalation_timeout.814784759
Directory /workspace/26.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/26.pwrmgr_glitch.1452903150
Short name T343
Test name
Test status
Simulation time 57010267 ps
CPU time 0.64 seconds
Started Jul 30 06:41:36 PM PDT 24
Finished Jul 30 06:41:37 PM PDT 24
Peak memory 198092 kb
Host smart-dc1baf35-632e-41f4-a54e-bbb2f69e2ff7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452903150 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_glitch.1452903150
Directory /workspace/26.pwrmgr_glitch/latest

Test location /workspace/coverage/default/26.pwrmgr_global_esc.3363758779
Short name T280
Test name
Test status
Simulation time 33745935 ps
CPU time 0.63 seconds
Started Jul 30 06:41:33 PM PDT 24
Finished Jul 30 06:41:34 PM PDT 24
Peak memory 198448 kb
Host smart-391e26ec-6525-4be3-88f8-ca1fc5e69c19
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363758779 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_global_esc.3363758779
Directory /workspace/26.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/26.pwrmgr_reset.4089787879
Short name T574
Test name
Test status
Simulation time 34491478 ps
CPU time 0.66 seconds
Started Jul 30 06:41:38 PM PDT 24
Finished Jul 30 06:41:39 PM PDT 24
Peak memory 198316 kb
Host smart-cca70e7a-c854-44d7-ad60-b8df4f6166e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089787879 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset.4089787879
Directory /workspace/26.pwrmgr_reset/latest

Test location /workspace/coverage/default/26.pwrmgr_reset_invalid.1675618392
Short name T245
Test name
Test status
Simulation time 119169337 ps
CPU time 0.82 seconds
Started Jul 30 06:41:35 PM PDT 24
Finished Jul 30 06:41:36 PM PDT 24
Peak memory 209700 kb
Host smart-3a9b4554-a7ff-4a01-8497-83d80a741ff2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675618392 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset_invalid.1675618392
Directory /workspace/26.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/26.pwrmgr_sec_cm_rstmgr_intersig_mubi.4114912755
Short name T493
Test name
Test status
Simulation time 79575477 ps
CPU time 0.8 seconds
Started Jul 30 06:41:37 PM PDT 24
Finished Jul 30 06:41:38 PM PDT 24
Peak memory 198196 kb
Host smart-7b9ee86e-adcc-4782-9e92-2d0482ad8777
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114912755 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4114912755
Directory /workspace/26.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/26.pwrmgr_smoke.1372655467
Short name T256
Test name
Test status
Simulation time 28222455 ps
CPU time 0.71 seconds
Started Jul 30 06:41:37 PM PDT 24
Finished Jul 30 06:41:38 PM PDT 24
Peak memory 199384 kb
Host smart-21b673c3-022d-47e8-8e3b-153b6c3159e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372655467 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_smoke.1372655467
Directory /workspace/26.pwrmgr_smoke/latest

Test location /workspace/coverage/default/27.pwrmgr_aborted_low_power.3562632086
Short name T14
Test name
Test status
Simulation time 30416260 ps
CPU time 0.75 seconds
Started Jul 30 06:41:43 PM PDT 24
Finished Jul 30 06:41:44 PM PDT 24
Peak memory 198940 kb
Host smart-a600ea11-b54e-43bb-a291-73939d0c8f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562632086 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_aborted_low_power.3562632086
Directory /workspace/27.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/27.pwrmgr_disable_rom_integrity_check.2719914636
Short name T626
Test name
Test status
Simulation time 55553442 ps
CPU time 0.7 seconds
Started Jul 30 06:41:37 PM PDT 24
Finished Jul 30 06:41:38 PM PDT 24
Peak memory 199188 kb
Host smart-85e08e0c-4bf3-4dc1-b86a-f69886dd24e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719914636 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_dis
able_rom_integrity_check.2719914636
Directory /workspace/27.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/27.pwrmgr_esc_clk_rst_malfunc.652367803
Short name T331
Test name
Test status
Simulation time 32092651 ps
CPU time 0.6 seconds
Started Jul 30 06:41:47 PM PDT 24
Finished Jul 30 06:41:48 PM PDT 24
Peak memory 197340 kb
Host smart-c52ad3c8-13c7-45a9-9100-88d324246ba3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652367803 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_esc_clk_rst_
malfunc.652367803
Directory /workspace/27.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/27.pwrmgr_escalation_timeout.2399919282
Short name T450
Test name
Test status
Simulation time 588955483 ps
CPU time 1 seconds
Started Jul 30 06:41:45 PM PDT 24
Finished Jul 30 06:41:46 PM PDT 24
Peak memory 198112 kb
Host smart-c7c52e20-8024-4de5-8c0c-1d8beceecfd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399919282 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_escalation_timeout.2399919282
Directory /workspace/27.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/27.pwrmgr_glitch.2000032836
Short name T274
Test name
Test status
Simulation time 37599313 ps
CPU time 0.59 seconds
Started Jul 30 06:41:43 PM PDT 24
Finished Jul 30 06:41:44 PM PDT 24
Peak memory 197364 kb
Host smart-c1c50435-ca58-40a6-8239-71a7bcd8b2aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000032836 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_glitch.2000032836
Directory /workspace/27.pwrmgr_glitch/latest

Test location /workspace/coverage/default/27.pwrmgr_global_esc.865521780
Short name T263
Test name
Test status
Simulation time 69085448 ps
CPU time 0.6 seconds
Started Jul 30 06:41:44 PM PDT 24
Finished Jul 30 06:41:45 PM PDT 24
Peak memory 198112 kb
Host smart-b7a3c095-2fda-4a23-ab51-ff1e07476ae3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865521780 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_global_esc.865521780
Directory /workspace/27.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/27.pwrmgr_lowpower_invalid.860383989
Short name T184
Test name
Test status
Simulation time 40828776 ps
CPU time 0.73 seconds
Started Jul 30 06:41:40 PM PDT 24
Finished Jul 30 06:41:41 PM PDT 24
Peak memory 201248 kb
Host smart-4327293a-a68a-4859-9b52-74fbe4a4615e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860383989 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_lowpower_invali
d.860383989
Directory /workspace/27.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/27.pwrmgr_reset.4164159148
Short name T221
Test name
Test status
Simulation time 58217337 ps
CPU time 0.67 seconds
Started Jul 30 06:41:42 PM PDT 24
Finished Jul 30 06:41:43 PM PDT 24
Peak memory 198336 kb
Host smart-9ce4e2b2-6e5b-403d-8656-bcfc525a0776
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164159148 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset.4164159148
Directory /workspace/27.pwrmgr_reset/latest

Test location /workspace/coverage/default/27.pwrmgr_reset_invalid.4076891475
Short name T314
Test name
Test status
Simulation time 104274372 ps
CPU time 0.97 seconds
Started Jul 30 06:41:40 PM PDT 24
Finished Jul 30 06:41:41 PM PDT 24
Peak memory 209580 kb
Host smart-de843e29-5af2-407b-8e09-77c6a5ae5d45
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076891475 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset_invalid.4076891475
Directory /workspace/27.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/27.pwrmgr_sec_cm_rstmgr_intersig_mubi.399373305
Short name T405
Test name
Test status
Simulation time 73511909 ps
CPU time 0.72 seconds
Started Jul 30 06:41:40 PM PDT 24
Finished Jul 30 06:41:41 PM PDT 24
Peak memory 198160 kb
Host smart-0cc04e8b-0fc8-439b-b1f2-6297c38a0e39
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399373305 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_rstmgr_intersig_
mubi.399373305
Directory /workspace/27.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/27.pwrmgr_smoke.661285533
Short name T321
Test name
Test status
Simulation time 43867943 ps
CPU time 0.64 seconds
Started Jul 30 06:41:40 PM PDT 24
Finished Jul 30 06:41:41 PM PDT 24
Peak memory 198464 kb
Host smart-fe0ffeb7-03b5-4ec8-8c84-1c6a3f890859
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661285533 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_smoke.661285533
Directory /workspace/27.pwrmgr_smoke/latest

Test location /workspace/coverage/default/28.pwrmgr_aborted_low_power.3497674367
Short name T96
Test name
Test status
Simulation time 30782162 ps
CPU time 0.96 seconds
Started Jul 30 06:41:45 PM PDT 24
Finished Jul 30 06:41:46 PM PDT 24
Peak memory 200964 kb
Host smart-f1bdb9bc-2403-4427-aff7-501a017a46a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497674367 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_aborted_low_power.3497674367
Directory /workspace/28.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/28.pwrmgr_disable_rom_integrity_check.3543691305
Short name T164
Test name
Test status
Simulation time 119016424 ps
CPU time 0.67 seconds
Started Jul 30 06:41:36 PM PDT 24
Finished Jul 30 06:41:37 PM PDT 24
Peak memory 198464 kb
Host smart-a2401572-8347-4605-bb00-db56037ac7cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543691305 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_dis
able_rom_integrity_check.3543691305
Directory /workspace/28.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/28.pwrmgr_escalation_timeout.1311189594
Short name T400
Test name
Test status
Simulation time 310109560 ps
CPU time 0.95 seconds
Started Jul 30 06:41:36 PM PDT 24
Finished Jul 30 06:41:37 PM PDT 24
Peak memory 198168 kb
Host smart-65bd235f-8c31-48b1-891a-6c87613d05a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311189594 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_escalation_timeout.1311189594
Directory /workspace/28.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/28.pwrmgr_glitch.2261481078
Short name T218
Test name
Test status
Simulation time 55418864 ps
CPU time 0.68 seconds
Started Jul 30 06:41:49 PM PDT 24
Finished Jul 30 06:41:50 PM PDT 24
Peak memory 197372 kb
Host smart-1ba74e77-4b92-46ab-8f4f-b7435ca07d2f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261481078 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_glitch.2261481078
Directory /workspace/28.pwrmgr_glitch/latest

Test location /workspace/coverage/default/28.pwrmgr_global_esc.2267256835
Short name T587
Test name
Test status
Simulation time 48978759 ps
CPU time 0.6 seconds
Started Jul 30 06:41:37 PM PDT 24
Finished Jul 30 06:41:38 PM PDT 24
Peak memory 198356 kb
Host smart-b874431e-10ce-4c7c-8a47-fd31071da0d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267256835 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_global_esc.2267256835
Directory /workspace/28.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/28.pwrmgr_lowpower_invalid.2500502484
Short name T611
Test name
Test status
Simulation time 40142056 ps
CPU time 0.68 seconds
Started Jul 30 06:41:41 PM PDT 24
Finished Jul 30 06:41:42 PM PDT 24
Peak memory 201432 kb
Host smart-6e6bdf2d-c133-4f95-867b-553fa653ac77
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500502484 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_lowpower_inval
id.2500502484
Directory /workspace/28.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/28.pwrmgr_reset.1983145628
Short name T229
Test name
Test status
Simulation time 46965520 ps
CPU time 0.69 seconds
Started Jul 30 06:41:33 PM PDT 24
Finished Jul 30 06:41:34 PM PDT 24
Peak memory 198400 kb
Host smart-6afaf141-8fc9-47e5-88d5-7eb2447b1fd2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983145628 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset.1983145628
Directory /workspace/28.pwrmgr_reset/latest

Test location /workspace/coverage/default/28.pwrmgr_reset_invalid.1378220390
Short name T344
Test name
Test status
Simulation time 127608851 ps
CPU time 0.84 seconds
Started Jul 30 06:41:45 PM PDT 24
Finished Jul 30 06:41:46 PM PDT 24
Peak memory 201316 kb
Host smart-768f89dd-3292-415f-90d9-d1a2ee176352
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378220390 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset_invalid.1378220390
Directory /workspace/28.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/28.pwrmgr_sec_cm_rstmgr_intersig_mubi.3799320133
Short name T371
Test name
Test status
Simulation time 92929582 ps
CPU time 0.8 seconds
Started Jul 30 06:41:33 PM PDT 24
Finished Jul 30 06:41:34 PM PDT 24
Peak memory 199336 kb
Host smart-98e76918-d2d0-4867-94ef-bc10e8b59ac6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799320133 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3799320133
Directory /workspace/28.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/28.pwrmgr_smoke.691705587
Short name T586
Test name
Test status
Simulation time 29720576 ps
CPU time 0.68 seconds
Started Jul 30 06:41:43 PM PDT 24
Finished Jul 30 06:41:44 PM PDT 24
Peak memory 199408 kb
Host smart-a1706504-b0a9-421b-a5d2-c76ed6372f8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691705587 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_smoke.691705587
Directory /workspace/28.pwrmgr_smoke/latest

Test location /workspace/coverage/default/28.pwrmgr_stress_all.3525067019
Short name T89
Test name
Test status
Simulation time 173243802 ps
CPU time 0.76 seconds
Started Jul 30 06:41:40 PM PDT 24
Finished Jul 30 06:41:40 PM PDT 24
Peak memory 198808 kb
Host smart-2413569c-9ac1-4bb9-bdfb-d8ede8e46d0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525067019 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_stress_all.3525067019
Directory /workspace/28.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/29.pwrmgr_aborted_low_power.818253618
Short name T530
Test name
Test status
Simulation time 37379968 ps
CPU time 1.14 seconds
Started Jul 30 06:41:40 PM PDT 24
Finished Jul 30 06:41:42 PM PDT 24
Peak memory 200988 kb
Host smart-777e0d40-ba6a-49fd-93b2-f558529467d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818253618 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_aborted_low_power.818253618
Directory /workspace/29.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/29.pwrmgr_disable_rom_integrity_check.3579195430
Short name T568
Test name
Test status
Simulation time 136193490 ps
CPU time 0.65 seconds
Started Jul 30 06:41:36 PM PDT 24
Finished Jul 30 06:41:37 PM PDT 24
Peak memory 198460 kb
Host smart-60dc62dd-0e79-4bac-91d5-6ba79cb4e87c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579195430 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_dis
able_rom_integrity_check.3579195430
Directory /workspace/29.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/29.pwrmgr_esc_clk_rst_malfunc.3794795544
Short name T228
Test name
Test status
Simulation time 38537753 ps
CPU time 0.59 seconds
Started Jul 30 06:41:37 PM PDT 24
Finished Jul 30 06:41:38 PM PDT 24
Peak memory 197688 kb
Host smart-33ac3f94-52af-4a60-87d0-83dcdefe8dda
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794795544 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_esc_clk_rst
_malfunc.3794795544
Directory /workspace/29.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/29.pwrmgr_escalation_timeout.1004174627
Short name T599
Test name
Test status
Simulation time 318149569 ps
CPU time 0.94 seconds
Started Jul 30 06:41:43 PM PDT 24
Finished Jul 30 06:41:46 PM PDT 24
Peak memory 198036 kb
Host smart-7492cc4e-7494-4877-a66f-14b685d688e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004174627 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_escalation_timeout.1004174627
Directory /workspace/29.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/29.pwrmgr_glitch.1950575237
Short name T360
Test name
Test status
Simulation time 212334980 ps
CPU time 0.6 seconds
Started Jul 30 06:41:44 PM PDT 24
Finished Jul 30 06:41:45 PM PDT 24
Peak memory 198140 kb
Host smart-4d6361ce-ef0b-4cb2-b59c-2b7a8043373f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950575237 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_glitch.1950575237
Directory /workspace/29.pwrmgr_glitch/latest

Test location /workspace/coverage/default/29.pwrmgr_global_esc.2085988170
Short name T37
Test name
Test status
Simulation time 322694040 ps
CPU time 0.59 seconds
Started Jul 30 06:41:46 PM PDT 24
Finished Jul 30 06:41:47 PM PDT 24
Peak memory 198412 kb
Host smart-53e987d9-39e4-4bd7-82e6-c320eb3e877a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085988170 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_global_esc.2085988170
Directory /workspace/29.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/29.pwrmgr_lowpower_invalid.915657432
Short name T191
Test name
Test status
Simulation time 44836290 ps
CPU time 0.71 seconds
Started Jul 30 06:41:39 PM PDT 24
Finished Jul 30 06:41:40 PM PDT 24
Peak memory 201408 kb
Host smart-5f32736c-29c2-4164-85e7-62703f9bc9f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915657432 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_lowpower_invali
d.915657432
Directory /workspace/29.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/29.pwrmgr_reset.1242857909
Short name T289
Test name
Test status
Simulation time 67141106 ps
CPU time 0.76 seconds
Started Jul 30 06:41:46 PM PDT 24
Finished Jul 30 06:41:47 PM PDT 24
Peak memory 199192 kb
Host smart-5bf5bb33-2afb-4ab1-9a3f-8e3bd7628314
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242857909 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset.1242857909
Directory /workspace/29.pwrmgr_reset/latest

Test location /workspace/coverage/default/29.pwrmgr_reset_invalid.2952140633
Short name T533
Test name
Test status
Simulation time 511372513 ps
CPU time 0.8 seconds
Started Jul 30 06:41:35 PM PDT 24
Finished Jul 30 06:41:36 PM PDT 24
Peak memory 209540 kb
Host smart-35164cd8-5f93-4fe9-b2bf-8c7d1dd86772
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952140633 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset_invalid.2952140633
Directory /workspace/29.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/29.pwrmgr_sec_cm_rstmgr_intersig_mubi.1597117521
Short name T317
Test name
Test status
Simulation time 127512632 ps
CPU time 0.77 seconds
Started Jul 30 06:41:39 PM PDT 24
Finished Jul 30 06:41:40 PM PDT 24
Peak memory 198272 kb
Host smart-489f7712-28d0-4b44-af89-01cc799f2bbf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597117521 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1597117521
Directory /workspace/29.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/29.pwrmgr_smoke.1714075375
Short name T358
Test name
Test status
Simulation time 56080471 ps
CPU time 0.65 seconds
Started Jul 30 06:41:38 PM PDT 24
Finished Jul 30 06:41:39 PM PDT 24
Peak memory 199360 kb
Host smart-85c1819e-8ee0-42f5-99dc-2603291010a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714075375 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_smoke.1714075375
Directory /workspace/29.pwrmgr_smoke/latest

Test location /workspace/coverage/default/3.pwrmgr_aborted_low_power.182716583
Short name T374
Test name
Test status
Simulation time 78316709 ps
CPU time 0.78 seconds
Started Jul 30 06:40:27 PM PDT 24
Finished Jul 30 06:40:28 PM PDT 24
Peak memory 198824 kb
Host smart-2c801864-2d56-447a-8a49-16c33347a97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182716583 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_aborted_low_power.182716583
Directory /workspace/3.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/3.pwrmgr_esc_clk_rst_malfunc.3399168317
Short name T469
Test name
Test status
Simulation time 33672724 ps
CPU time 0.59 seconds
Started Jul 30 06:40:31 PM PDT 24
Finished Jul 30 06:40:32 PM PDT 24
Peak memory 198020 kb
Host smart-56aa4f90-8253-4a60-8699-525751537c71
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399168317 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_esc_clk_rst_
malfunc.3399168317
Directory /workspace/3.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/3.pwrmgr_escalation_timeout.3543580635
Short name T519
Test name
Test status
Simulation time 582867381 ps
CPU time 0.96 seconds
Started Jul 30 06:40:34 PM PDT 24
Finished Jul 30 06:40:35 PM PDT 24
Peak memory 197808 kb
Host smart-c3e5dc23-4e48-4482-8fe8-77fa290b3202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543580635 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_escalation_timeout.3543580635
Directory /workspace/3.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/3.pwrmgr_glitch.1581456730
Short name T273
Test name
Test status
Simulation time 54081151 ps
CPU time 0.62 seconds
Started Jul 30 06:40:31 PM PDT 24
Finished Jul 30 06:40:32 PM PDT 24
Peak memory 197512 kb
Host smart-ca8ac28d-487e-4eb0-b243-fe209ca7dacd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581456730 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_glitch.1581456730
Directory /workspace/3.pwrmgr_glitch/latest

Test location /workspace/coverage/default/3.pwrmgr_global_esc.1395745287
Short name T453
Test name
Test status
Simulation time 44836414 ps
CPU time 0.66 seconds
Started Jul 30 06:40:32 PM PDT 24
Finished Jul 30 06:40:33 PM PDT 24
Peak memory 198112 kb
Host smart-2b4a9935-0d7b-416e-929d-376caead148e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395745287 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_global_esc.1395745287
Directory /workspace/3.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/3.pwrmgr_reset.2832133883
Short name T224
Test name
Test status
Simulation time 19781708 ps
CPU time 0.63 seconds
Started Jul 30 06:40:26 PM PDT 24
Finished Jul 30 06:40:26 PM PDT 24
Peak memory 198168 kb
Host smart-31dea264-0ca5-4baa-bed5-deabc86bd7fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832133883 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset.2832133883
Directory /workspace/3.pwrmgr_reset/latest

Test location /workspace/coverage/default/3.pwrmgr_reset_invalid.2514223258
Short name T423
Test name
Test status
Simulation time 324264433 ps
CPU time 0.77 seconds
Started Jul 30 06:40:31 PM PDT 24
Finished Jul 30 06:40:32 PM PDT 24
Peak memory 209484 kb
Host smart-5c00eb79-73ec-4d6b-9f31-0c659dcf75b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514223258 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset_invalid.2514223258
Directory /workspace/3.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm.1357970379
Short name T31
Test name
Test status
Simulation time 590861208 ps
CPU time 1.97 seconds
Started Jul 30 06:40:30 PM PDT 24
Finished Jul 30 06:40:32 PM PDT 24
Peak memory 216936 kb
Host smart-46523cf5-5a17-42bf-8a9e-bc936bcf0256
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357970379 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm.1357970379
Directory /workspace/3.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm_rstmgr_intersig_mubi.2535986747
Short name T46
Test name
Test status
Simulation time 53541684 ps
CPU time 0.84 seconds
Started Jul 30 06:40:30 PM PDT 24
Finished Jul 30 06:40:31 PM PDT 24
Peak memory 199460 kb
Host smart-06dc8bcb-ae9e-4aab-a95a-42dec9d6386d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535986747 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2535986747
Directory /workspace/3.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/3.pwrmgr_smoke.2305418486
Short name T275
Test name
Test status
Simulation time 51361492 ps
CPU time 0.67 seconds
Started Jul 30 06:40:27 PM PDT 24
Finished Jul 30 06:40:28 PM PDT 24
Peak memory 199440 kb
Host smart-95540982-538b-4e08-ac20-b7deb9c56a40
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305418486 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_smoke.2305418486
Directory /workspace/3.pwrmgr_smoke/latest

Test location /workspace/coverage/default/30.pwrmgr_aborted_low_power.3377129231
Short name T375
Test name
Test status
Simulation time 39330144 ps
CPU time 0.91 seconds
Started Jul 30 06:41:41 PM PDT 24
Finished Jul 30 06:41:42 PM PDT 24
Peak memory 200212 kb
Host smart-3c96daf4-d0ae-4b2d-8fab-0099b1fe1471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377129231 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_aborted_low_power.3377129231
Directory /workspace/30.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/30.pwrmgr_disable_rom_integrity_check.724598137
Short name T138
Test name
Test status
Simulation time 65686469 ps
CPU time 0.66 seconds
Started Jul 30 06:41:45 PM PDT 24
Finished Jul 30 06:41:46 PM PDT 24
Peak memory 199164 kb
Host smart-6d053cd2-a58e-4232-83bf-dcb2306823dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724598137 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_disa
ble_rom_integrity_check.724598137
Directory /workspace/30.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/30.pwrmgr_esc_clk_rst_malfunc.3796894413
Short name T527
Test name
Test status
Simulation time 32455461 ps
CPU time 0.59 seconds
Started Jul 30 06:41:40 PM PDT 24
Finished Jul 30 06:41:41 PM PDT 24
Peak memory 198008 kb
Host smart-3e13544c-50a5-4b45-a321-d880ceb72a86
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796894413 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_esc_clk_rst
_malfunc.3796894413
Directory /workspace/30.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/30.pwrmgr_escalation_timeout.915588783
Short name T355
Test name
Test status
Simulation time 179151881 ps
CPU time 0.93 seconds
Started Jul 30 06:41:36 PM PDT 24
Finished Jul 30 06:41:37 PM PDT 24
Peak memory 198148 kb
Host smart-4f62fa59-85b2-492f-b580-712518434444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915588783 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_escalation_timeout.915588783
Directory /workspace/30.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/30.pwrmgr_glitch.4141459021
Short name T477
Test name
Test status
Simulation time 72419207 ps
CPU time 0.62 seconds
Started Jul 30 06:41:49 PM PDT 24
Finished Jul 30 06:41:50 PM PDT 24
Peak memory 197432 kb
Host smart-18c396a4-963a-4135-9292-baa72efc2daf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141459021 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_glitch.4141459021
Directory /workspace/30.pwrmgr_glitch/latest

Test location /workspace/coverage/default/30.pwrmgr_global_esc.617884134
Short name T50
Test name
Test status
Simulation time 87935474 ps
CPU time 0.59 seconds
Started Jul 30 06:41:46 PM PDT 24
Finished Jul 30 06:41:47 PM PDT 24
Peak memory 198096 kb
Host smart-efd08549-1bb3-4207-9b9d-dc65a77bd49f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617884134 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_global_esc.617884134
Directory /workspace/30.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/30.pwrmgr_lowpower_wakeup_race.2696489041
Short name T205
Test name
Test status
Simulation time 50633622 ps
CPU time 0.65 seconds
Started Jul 30 06:41:42 PM PDT 24
Finished Jul 30 06:41:43 PM PDT 24
Peak memory 198140 kb
Host smart-0a0d5bc7-76d4-4706-a367-477c690deb76
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696489041 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_lowpower_w
akeup_race.2696489041
Directory /workspace/30.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/30.pwrmgr_reset.2453111725
Short name T255
Test name
Test status
Simulation time 84501336 ps
CPU time 0.69 seconds
Started Jul 30 06:41:41 PM PDT 24
Finished Jul 30 06:41:42 PM PDT 24
Peak memory 198312 kb
Host smart-a721671e-a500-4c31-ae08-ab092dab1782
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453111725 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset.2453111725
Directory /workspace/30.pwrmgr_reset/latest

Test location /workspace/coverage/default/30.pwrmgr_reset_invalid.4121596578
Short name T282
Test name
Test status
Simulation time 109901434 ps
CPU time 1.17 seconds
Started Jul 30 06:41:46 PM PDT 24
Finished Jul 30 06:41:47 PM PDT 24
Peak memory 209488 kb
Host smart-36fd4bc4-e661-493a-9c01-dad1f1725d71
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121596578 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset_invalid.4121596578
Directory /workspace/30.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/30.pwrmgr_sec_cm_rstmgr_intersig_mubi.1270826316
Short name T429
Test name
Test status
Simulation time 324115288 ps
CPU time 0.72 seconds
Started Jul 30 06:41:46 PM PDT 24
Finished Jul 30 06:41:47 PM PDT 24
Peak memory 198296 kb
Host smart-aa9e0021-ccb4-4767-9c88-728d20d65acc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270826316 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1270826316
Directory /workspace/30.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/30.pwrmgr_smoke.2805760895
Short name T564
Test name
Test status
Simulation time 39191825 ps
CPU time 0.65 seconds
Started Jul 30 06:41:41 PM PDT 24
Finished Jul 30 06:41:42 PM PDT 24
Peak memory 198504 kb
Host smart-40d49dc3-4cae-4b93-af20-24230bd75b5b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805760895 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_smoke.2805760895
Directory /workspace/30.pwrmgr_smoke/latest

Test location /workspace/coverage/default/31.pwrmgr_aborted_low_power.3970597899
Short name T342
Test name
Test status
Simulation time 32585385 ps
CPU time 0.93 seconds
Started Jul 30 06:41:38 PM PDT 24
Finished Jul 30 06:41:39 PM PDT 24
Peak memory 200736 kb
Host smart-85c2f644-96a9-4711-82f4-8b10da230571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970597899 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_aborted_low_power.3970597899
Directory /workspace/31.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/31.pwrmgr_disable_rom_integrity_check.3284287290
Short name T547
Test name
Test status
Simulation time 65680728 ps
CPU time 0.72 seconds
Started Jul 30 06:41:46 PM PDT 24
Finished Jul 30 06:41:47 PM PDT 24
Peak memory 198488 kb
Host smart-72f36278-5d9c-434e-bea4-8382882d831a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284287290 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_dis
able_rom_integrity_check.3284287290
Directory /workspace/31.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/31.pwrmgr_esc_clk_rst_malfunc.234869587
Short name T269
Test name
Test status
Simulation time 32558258 ps
CPU time 0.6 seconds
Started Jul 30 06:41:44 PM PDT 24
Finished Jul 30 06:41:45 PM PDT 24
Peak memory 198080 kb
Host smart-34482e52-843e-4e5a-a5ce-a9a7f1ed9fd5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234869587 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_esc_clk_rst_
malfunc.234869587
Directory /workspace/31.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/31.pwrmgr_escalation_timeout.4082828631
Short name T579
Test name
Test status
Simulation time 661309959 ps
CPU time 0.95 seconds
Started Jul 30 06:41:37 PM PDT 24
Finished Jul 30 06:41:38 PM PDT 24
Peak memory 198128 kb
Host smart-15600339-9e73-4c17-904e-3ee3ab0b9f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082828631 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_escalation_timeout.4082828631
Directory /workspace/31.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/31.pwrmgr_glitch.1215146025
Short name T271
Test name
Test status
Simulation time 87546680 ps
CPU time 0.59 seconds
Started Jul 30 06:41:42 PM PDT 24
Finished Jul 30 06:41:43 PM PDT 24
Peak memory 198140 kb
Host smart-32439b0a-e3ac-4596-8837-02c571e2e40d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215146025 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_glitch.1215146025
Directory /workspace/31.pwrmgr_glitch/latest

Test location /workspace/coverage/default/31.pwrmgr_global_esc.3668826535
Short name T251
Test name
Test status
Simulation time 45035849 ps
CPU time 0.66 seconds
Started Jul 30 06:41:36 PM PDT 24
Finished Jul 30 06:41:37 PM PDT 24
Peak memory 198072 kb
Host smart-808f330e-d5ac-461b-b027-ba88eb5f31f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668826535 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_global_esc.3668826535
Directory /workspace/31.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/31.pwrmgr_reset.1940376593
Short name T241
Test name
Test status
Simulation time 60430504 ps
CPU time 0.8 seconds
Started Jul 30 06:41:47 PM PDT 24
Finished Jul 30 06:41:48 PM PDT 24
Peak memory 198388 kb
Host smart-61a7bc49-3334-4e14-a5c3-213246e7e63f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940376593 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset.1940376593
Directory /workspace/31.pwrmgr_reset/latest

Test location /workspace/coverage/default/31.pwrmgr_reset_invalid.3880002648
Short name T303
Test name
Test status
Simulation time 161100002 ps
CPU time 0.78 seconds
Started Jul 30 06:41:49 PM PDT 24
Finished Jul 30 06:41:50 PM PDT 24
Peak memory 209496 kb
Host smart-5fc16965-45e6-4405-b09e-98e8ebcb6cec
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880002648 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset_invalid.3880002648
Directory /workspace/31.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/31.pwrmgr_sec_cm_rstmgr_intersig_mubi.1084190822
Short name T389
Test name
Test status
Simulation time 107710862 ps
CPU time 0.69 seconds
Started Jul 30 06:41:44 PM PDT 24
Finished Jul 30 06:41:54 PM PDT 24
Peak memory 198116 kb
Host smart-b9562a03-05f5-4736-9a00-f747a7ccfcd8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084190822 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1084190822
Directory /workspace/31.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/31.pwrmgr_smoke.3765144346
Short name T301
Test name
Test status
Simulation time 32946195 ps
CPU time 0.65 seconds
Started Jul 30 06:41:42 PM PDT 24
Finished Jul 30 06:41:43 PM PDT 24
Peak memory 198508 kb
Host smart-7bb8eefa-036e-4deb-8d33-7391ba586872
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765144346 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_smoke.3765144346
Directory /workspace/31.pwrmgr_smoke/latest

Test location /workspace/coverage/default/32.pwrmgr_aborted_low_power.4012022623
Short name T486
Test name
Test status
Simulation time 31217679 ps
CPU time 0.73 seconds
Started Jul 30 06:41:46 PM PDT 24
Finished Jul 30 06:41:47 PM PDT 24
Peak memory 198836 kb
Host smart-a4724aac-e00e-48ab-9d5f-f2cbe2f0a3bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012022623 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_aborted_low_power.4012022623
Directory /workspace/32.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/32.pwrmgr_disable_rom_integrity_check.1043041848
Short name T153
Test name
Test status
Simulation time 50771936 ps
CPU time 0.73 seconds
Started Jul 30 06:41:52 PM PDT 24
Finished Jul 30 06:41:52 PM PDT 24
Peak memory 199172 kb
Host smart-32304f26-1c1b-462c-b15e-fba1e7ed0bef
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043041848 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_dis
able_rom_integrity_check.1043041848
Directory /workspace/32.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/32.pwrmgr_esc_clk_rst_malfunc.3061096781
Short name T394
Test name
Test status
Simulation time 62574739 ps
CPU time 0.59 seconds
Started Jul 30 06:41:58 PM PDT 24
Finished Jul 30 06:41:58 PM PDT 24
Peak memory 198084 kb
Host smart-d783d6c6-d81f-44e3-ad04-36bf71cbd0e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061096781 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_esc_clk_rst
_malfunc.3061096781
Directory /workspace/32.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/32.pwrmgr_escalation_timeout.633726985
Short name T458
Test name
Test status
Simulation time 160477749 ps
CPU time 0.97 seconds
Started Jul 30 06:41:36 PM PDT 24
Finished Jul 30 06:41:38 PM PDT 24
Peak memory 198128 kb
Host smart-f1dece95-2d00-4df1-8d42-5ad63ed96cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633726985 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_escalation_timeout.633726985
Directory /workspace/32.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/32.pwrmgr_glitch.226915816
Short name T410
Test name
Test status
Simulation time 57399208 ps
CPU time 0.6 seconds
Started Jul 30 06:41:38 PM PDT 24
Finished Jul 30 06:41:39 PM PDT 24
Peak memory 198060 kb
Host smart-35fde49b-d028-42b6-a1fb-c3e6f19cd68e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226915816 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_glitch.226915816
Directory /workspace/32.pwrmgr_glitch/latest

Test location /workspace/coverage/default/32.pwrmgr_global_esc.639779940
Short name T434
Test name
Test status
Simulation time 35001573 ps
CPU time 0.64 seconds
Started Jul 30 06:41:46 PM PDT 24
Finished Jul 30 06:41:47 PM PDT 24
Peak memory 198112 kb
Host smart-b15b48c9-afe6-42ef-9b1e-3427613baeea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639779940 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_global_esc.639779940
Directory /workspace/32.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/32.pwrmgr_lowpower_invalid.3246568797
Short name T382
Test name
Test status
Simulation time 43042083 ps
CPU time 0.7 seconds
Started Jul 30 06:41:58 PM PDT 24
Finished Jul 30 06:41:59 PM PDT 24
Peak memory 201204 kb
Host smart-8d64c891-de13-429b-a19c-b5b6cdb6e250
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246568797 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_lowpower_inval
id.3246568797
Directory /workspace/32.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/32.pwrmgr_reset.1980064178
Short name T474
Test name
Test status
Simulation time 45966574 ps
CPU time 0.74 seconds
Started Jul 30 06:41:51 PM PDT 24
Finished Jul 30 06:41:52 PM PDT 24
Peak memory 199200 kb
Host smart-13a473fb-a4f8-4d88-bbf2-33b40d3b70ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980064178 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset.1980064178
Directory /workspace/32.pwrmgr_reset/latest

Test location /workspace/coverage/default/32.pwrmgr_reset_invalid.103538649
Short name T247
Test name
Test status
Simulation time 115463063 ps
CPU time 0.83 seconds
Started Jul 30 06:41:38 PM PDT 24
Finished Jul 30 06:41:40 PM PDT 24
Peak memory 209456 kb
Host smart-85d25a26-064a-4e76-a6af-dd96cc532bbb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103538649 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset_invalid.103538649
Directory /workspace/32.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/32.pwrmgr_sec_cm_rstmgr_intersig_mubi.1357586028
Short name T421
Test name
Test status
Simulation time 50518994 ps
CPU time 0.84 seconds
Started Jul 30 06:41:38 PM PDT 24
Finished Jul 30 06:41:39 PM PDT 24
Peak memory 199200 kb
Host smart-7759fd96-817c-4eb1-ac94-2ec5ad7b3156
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357586028 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1357586028
Directory /workspace/32.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/32.pwrmgr_smoke.2553183843
Short name T125
Test name
Test status
Simulation time 34086362 ps
CPU time 0.66 seconds
Started Jul 30 06:41:46 PM PDT 24
Finished Jul 30 06:41:47 PM PDT 24
Peak memory 198468 kb
Host smart-b6f0fdc4-428b-4ef4-aff6-12aa5fc27fda
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553183843 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_smoke.2553183843
Directory /workspace/32.pwrmgr_smoke/latest

Test location /workspace/coverage/default/33.pwrmgr_aborted_low_power.1279067264
Short name T194
Test name
Test status
Simulation time 40743984 ps
CPU time 0.71 seconds
Started Jul 30 06:41:39 PM PDT 24
Finished Jul 30 06:41:39 PM PDT 24
Peak memory 198884 kb
Host smart-ac7f0b80-3d74-4187-9fb3-112c9657c704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279067264 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_aborted_low_power.1279067264
Directory /workspace/33.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/33.pwrmgr_esc_clk_rst_malfunc.233316386
Short name T412
Test name
Test status
Simulation time 28866433 ps
CPU time 0.68 seconds
Started Jul 30 06:41:50 PM PDT 24
Finished Jul 30 06:41:51 PM PDT 24
Peak memory 198048 kb
Host smart-e3868389-b629-4191-892f-9cabe7626b42
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233316386 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_esc_clk_rst_
malfunc.233316386
Directory /workspace/33.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/33.pwrmgr_escalation_timeout.3303547619
Short name T580
Test name
Test status
Simulation time 326413287 ps
CPU time 0.98 seconds
Started Jul 30 06:41:37 PM PDT 24
Finished Jul 30 06:41:38 PM PDT 24
Peak memory 198416 kb
Host smart-ed4cf93e-b07f-4527-b9c2-8e97ed1ac4b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303547619 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_escalation_timeout.3303547619
Directory /workspace/33.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/33.pwrmgr_glitch.2081484095
Short name T417
Test name
Test status
Simulation time 47690190 ps
CPU time 0.6 seconds
Started Jul 30 06:41:52 PM PDT 24
Finished Jul 30 06:41:53 PM PDT 24
Peak memory 197352 kb
Host smart-d3461c84-b713-4a25-87ba-fc54529df64c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081484095 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_glitch.2081484095
Directory /workspace/33.pwrmgr_glitch/latest

Test location /workspace/coverage/default/33.pwrmgr_global_esc.3903202021
Short name T392
Test name
Test status
Simulation time 64063352 ps
CPU time 0.61 seconds
Started Jul 30 06:41:49 PM PDT 24
Finished Jul 30 06:41:50 PM PDT 24
Peak memory 198100 kb
Host smart-ce4fbe32-865a-4500-97f7-d2c520d5cad5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903202021 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_global_esc.3903202021
Directory /workspace/33.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/33.pwrmgr_lowpower_invalid.1373549530
Short name T550
Test name
Test status
Simulation time 71134741 ps
CPU time 0.65 seconds
Started Jul 30 06:41:47 PM PDT 24
Finished Jul 30 06:41:48 PM PDT 24
Peak memory 201432 kb
Host smart-a03a0d9a-b0c0-4ef5-97a7-c0927aa6d35e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373549530 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_lowpower_inval
id.1373549530
Directory /workspace/33.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/33.pwrmgr_reset.1329948435
Short name T503
Test name
Test status
Simulation time 80054354 ps
CPU time 0.75 seconds
Started Jul 30 06:41:51 PM PDT 24
Finished Jul 30 06:41:52 PM PDT 24
Peak memory 198360 kb
Host smart-8afb02ba-5800-498f-a1ab-f936964c726c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329948435 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset.1329948435
Directory /workspace/33.pwrmgr_reset/latest

Test location /workspace/coverage/default/33.pwrmgr_reset_invalid.2200847860
Short name T597
Test name
Test status
Simulation time 123843035 ps
CPU time 0.82 seconds
Started Jul 30 06:41:42 PM PDT 24
Finished Jul 30 06:41:43 PM PDT 24
Peak memory 209448 kb
Host smart-2e3a7c78-faeb-4455-a5fd-c5fc1fd1de2e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200847860 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset_invalid.2200847860
Directory /workspace/33.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/33.pwrmgr_sec_cm_rstmgr_intersig_mubi.3627214557
Short name T285
Test name
Test status
Simulation time 51388187 ps
CPU time 0.87 seconds
Started Jul 30 06:41:58 PM PDT 24
Finished Jul 30 06:41:59 PM PDT 24
Peak memory 198012 kb
Host smart-fb5b2307-19cd-4c69-b139-98bb44632376
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627214557 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3627214557
Directory /workspace/33.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/33.pwrmgr_smoke.1828772394
Short name T462
Test name
Test status
Simulation time 48246430 ps
CPU time 0.65 seconds
Started Jul 30 06:41:49 PM PDT 24
Finished Jul 30 06:41:50 PM PDT 24
Peak memory 199404 kb
Host smart-a255891a-f8c7-40de-bf7c-7a06d1bdb2be
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828772394 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_smoke.1828772394
Directory /workspace/33.pwrmgr_smoke/latest

Test location /workspace/coverage/default/34.pwrmgr_aborted_low_power.3767203459
Short name T345
Test name
Test status
Simulation time 27982367 ps
CPU time 0.91 seconds
Started Jul 30 06:41:47 PM PDT 24
Finished Jul 30 06:41:48 PM PDT 24
Peak memory 200348 kb
Host smart-45c160a0-4e70-4983-ba85-ec19c6287aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767203459 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_aborted_low_power.3767203459
Directory /workspace/34.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/34.pwrmgr_disable_rom_integrity_check.2082311695
Short name T615
Test name
Test status
Simulation time 53609946 ps
CPU time 0.69 seconds
Started Jul 30 06:41:54 PM PDT 24
Finished Jul 30 06:41:55 PM PDT 24
Peak memory 198364 kb
Host smart-0c7d1374-063d-4739-8a03-dce24dd5d8ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082311695 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_dis
able_rom_integrity_check.2082311695
Directory /workspace/34.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/34.pwrmgr_esc_clk_rst_malfunc.1264811389
Short name T49
Test name
Test status
Simulation time 41559185 ps
CPU time 0.57 seconds
Started Jul 30 06:41:43 PM PDT 24
Finished Jul 30 06:41:44 PM PDT 24
Peak memory 198036 kb
Host smart-81cefabe-bcea-49bd-b3cf-854669249253
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264811389 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_esc_clk_rst
_malfunc.1264811389
Directory /workspace/34.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/34.pwrmgr_escalation_timeout.3991827016
Short name T131
Test name
Test status
Simulation time 157848122 ps
CPU time 0.97 seconds
Started Jul 30 06:41:47 PM PDT 24
Finished Jul 30 06:41:48 PM PDT 24
Peak memory 198372 kb
Host smart-955a097d-13d6-4ef8-8918-5a5ef8a7da48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991827016 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_escalation_timeout.3991827016
Directory /workspace/34.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/34.pwrmgr_glitch.205091142
Short name T318
Test name
Test status
Simulation time 40286084 ps
CPU time 0.63 seconds
Started Jul 30 06:41:45 PM PDT 24
Finished Jul 30 06:41:45 PM PDT 24
Peak memory 198144 kb
Host smart-1fbc60b1-34c4-4fb3-8437-353a8e11f4d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205091142 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_glitch.205091142
Directory /workspace/34.pwrmgr_glitch/latest

Test location /workspace/coverage/default/34.pwrmgr_global_esc.2185614142
Short name T236
Test name
Test status
Simulation time 46872831 ps
CPU time 0.66 seconds
Started Jul 30 06:41:52 PM PDT 24
Finished Jul 30 06:41:53 PM PDT 24
Peak memory 198104 kb
Host smart-fd31e54c-6615-4451-8b04-f19be9ff4231
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185614142 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_global_esc.2185614142
Directory /workspace/34.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/34.pwrmgr_lowpower_invalid.2614081304
Short name T188
Test name
Test status
Simulation time 42943203 ps
CPU time 0.74 seconds
Started Jul 30 06:41:46 PM PDT 24
Finished Jul 30 06:41:47 PM PDT 24
Peak memory 201416 kb
Host smart-116c7033-fd19-43f0-a90a-d460927819fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614081304 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_lowpower_inval
id.2614081304
Directory /workspace/34.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/34.pwrmgr_reset.1964994675
Short name T359
Test name
Test status
Simulation time 66075801 ps
CPU time 0.92 seconds
Started Jul 30 06:41:47 PM PDT 24
Finished Jul 30 06:41:48 PM PDT 24
Peak memory 199164 kb
Host smart-78cd5b49-e8df-4a74-b8be-5c8862b0e9e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964994675 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset.1964994675
Directory /workspace/34.pwrmgr_reset/latest

Test location /workspace/coverage/default/34.pwrmgr_reset_invalid.3769130262
Short name T592
Test name
Test status
Simulation time 91313257 ps
CPU time 1.1 seconds
Started Jul 30 06:41:45 PM PDT 24
Finished Jul 30 06:41:48 PM PDT 24
Peak memory 209512 kb
Host smart-ef97beed-8e85-49c1-987c-2e7a8f686947
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769130262 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset_invalid.3769130262
Directory /workspace/34.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/34.pwrmgr_sec_cm_rstmgr_intersig_mubi.1098544984
Short name T598
Test name
Test status
Simulation time 110209142 ps
CPU time 0.72 seconds
Started Jul 30 06:41:54 PM PDT 24
Finished Jul 30 06:41:55 PM PDT 24
Peak memory 198096 kb
Host smart-afca3197-536b-4421-83f9-a412d8ec095e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098544984 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1098544984
Directory /workspace/34.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/34.pwrmgr_smoke.2519054256
Short name T620
Test name
Test status
Simulation time 29138297 ps
CPU time 0.69 seconds
Started Jul 30 06:41:59 PM PDT 24
Finished Jul 30 06:42:00 PM PDT 24
Peak memory 198388 kb
Host smart-aefeecc3-d0d8-4c5d-8b3b-ac09ca0db411
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519054256 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_smoke.2519054256
Directory /workspace/34.pwrmgr_smoke/latest

Test location /workspace/coverage/default/35.pwrmgr_aborted_low_power.231037249
Short name T270
Test name
Test status
Simulation time 33502274 ps
CPU time 0.8 seconds
Started Jul 30 06:41:49 PM PDT 24
Finished Jul 30 06:41:50 PM PDT 24
Peak memory 198996 kb
Host smart-55545ad3-edcc-4e48-a4fa-6b36d40557da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231037249 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_aborted_low_power.231037249
Directory /workspace/35.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/35.pwrmgr_disable_rom_integrity_check.3460393012
Short name T488
Test name
Test status
Simulation time 101766963 ps
CPU time 0.63 seconds
Started Jul 30 06:41:46 PM PDT 24
Finished Jul 30 06:41:52 PM PDT 24
Peak memory 198548 kb
Host smart-e842d182-7cc9-42d0-a80c-887686d14598
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460393012 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_dis
able_rom_integrity_check.3460393012
Directory /workspace/35.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/35.pwrmgr_esc_clk_rst_malfunc.623417230
Short name T610
Test name
Test status
Simulation time 29813896 ps
CPU time 0.64 seconds
Started Jul 30 06:41:49 PM PDT 24
Finished Jul 30 06:41:50 PM PDT 24
Peak memory 198028 kb
Host smart-332c3729-3010-4d76-a958-a7a32ce62a49
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623417230 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_esc_clk_rst_
malfunc.623417230
Directory /workspace/35.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/35.pwrmgr_escalation_timeout.3414050673
Short name T584
Test name
Test status
Simulation time 631929961 ps
CPU time 0.95 seconds
Started Jul 30 06:41:54 PM PDT 24
Finished Jul 30 06:41:55 PM PDT 24
Peak memory 198400 kb
Host smart-badb6869-cd89-4226-8e63-9d523e847502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414050673 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_escalation_timeout.3414050673
Directory /workspace/35.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/35.pwrmgr_glitch.1710762483
Short name T17
Test name
Test status
Simulation time 67855105 ps
CPU time 0.6 seconds
Started Jul 30 06:41:49 PM PDT 24
Finished Jul 30 06:41:50 PM PDT 24
Peak memory 197420 kb
Host smart-8bda0184-bb17-48ad-9b82-0dff349b86ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710762483 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_glitch.1710762483
Directory /workspace/35.pwrmgr_glitch/latest

Test location /workspace/coverage/default/35.pwrmgr_global_esc.2795552520
Short name T337
Test name
Test status
Simulation time 23595760 ps
CPU time 0.63 seconds
Started Jul 30 06:41:56 PM PDT 24
Finished Jul 30 06:41:57 PM PDT 24
Peak memory 198116 kb
Host smart-49abb764-3e56-441c-8309-ad0db0087887
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795552520 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_global_esc.2795552520
Directory /workspace/35.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/35.pwrmgr_lowpower_invalid.4153120981
Short name T608
Test name
Test status
Simulation time 44979261 ps
CPU time 0.7 seconds
Started Jul 30 06:42:19 PM PDT 24
Finished Jul 30 06:42:20 PM PDT 24
Peak memory 201380 kb
Host smart-8c7813c7-12d3-4a95-9b4e-3d4633d716ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153120981 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_lowpower_inval
id.4153120981
Directory /workspace/35.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/35.pwrmgr_reset.2442758517
Short name T267
Test name
Test status
Simulation time 65132317 ps
CPU time 0.76 seconds
Started Jul 30 06:41:52 PM PDT 24
Finished Jul 30 06:41:53 PM PDT 24
Peak memory 199148 kb
Host smart-a5f67d71-31e5-43b1-a8ce-acade37383f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442758517 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset.2442758517
Directory /workspace/35.pwrmgr_reset/latest

Test location /workspace/coverage/default/35.pwrmgr_reset_invalid.3829892559
Short name T250
Test name
Test status
Simulation time 287940706 ps
CPU time 0.81 seconds
Started Jul 30 06:42:17 PM PDT 24
Finished Jul 30 06:42:18 PM PDT 24
Peak memory 209528 kb
Host smart-c30832ed-71b8-4843-b5b2-48ba817a4bd8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829892559 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset_invalid.3829892559
Directory /workspace/35.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/35.pwrmgr_sec_cm_rstmgr_intersig_mubi.268582185
Short name T601
Test name
Test status
Simulation time 63750104 ps
CPU time 0.86 seconds
Started Jul 30 06:41:45 PM PDT 24
Finished Jul 30 06:41:48 PM PDT 24
Peak memory 199416 kb
Host smart-2ffc4817-cd26-4e26-8f8e-94f430c7867c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268582185 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_rstmgr_intersig_
mubi.268582185
Directory /workspace/35.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/35.pwrmgr_smoke.3113277101
Short name T401
Test name
Test status
Simulation time 80217142 ps
CPU time 0.62 seconds
Started Jul 30 06:41:46 PM PDT 24
Finished Jul 30 06:41:47 PM PDT 24
Peak memory 199372 kb
Host smart-5ec628e9-1047-4b70-8f5b-82a617c5253b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113277101 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_smoke.3113277101
Directory /workspace/35.pwrmgr_smoke/latest

Test location /workspace/coverage/default/36.pwrmgr_aborted_low_power.3391284487
Short name T88
Test name
Test status
Simulation time 103009194 ps
CPU time 0.83 seconds
Started Jul 30 06:41:59 PM PDT 24
Finished Jul 30 06:42:00 PM PDT 24
Peak memory 200168 kb
Host smart-e8c26fd8-7aca-4e5e-8dfc-b213f71f8966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391284487 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_aborted_low_power.3391284487
Directory /workspace/36.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/36.pwrmgr_disable_rom_integrity_check.4230080784
Short name T501
Test name
Test status
Simulation time 72878837 ps
CPU time 0.68 seconds
Started Jul 30 06:41:56 PM PDT 24
Finished Jul 30 06:41:57 PM PDT 24
Peak memory 198560 kb
Host smart-0f720ceb-4410-4b2a-af2c-3cf8340654e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230080784 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_dis
able_rom_integrity_check.4230080784
Directory /workspace/36.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/36.pwrmgr_esc_clk_rst_malfunc.2424813825
Short name T471
Test name
Test status
Simulation time 32886012 ps
CPU time 0.62 seconds
Started Jul 30 06:41:50 PM PDT 24
Finished Jul 30 06:41:50 PM PDT 24
Peak memory 197376 kb
Host smart-213f53e3-0766-4a06-b27b-04974dccf0e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424813825 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_esc_clk_rst
_malfunc.2424813825
Directory /workspace/36.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/36.pwrmgr_escalation_timeout.1036176542
Short name T354
Test name
Test status
Simulation time 657542747 ps
CPU time 0.97 seconds
Started Jul 30 06:41:43 PM PDT 24
Finished Jul 30 06:41:44 PM PDT 24
Peak memory 198364 kb
Host smart-a363d4ce-1883-4b33-af0f-44a23298c766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036176542 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_escalation_timeout.1036176542
Directory /workspace/36.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/36.pwrmgr_glitch.1298136641
Short name T330
Test name
Test status
Simulation time 34934287 ps
CPU time 0.65 seconds
Started Jul 30 06:41:45 PM PDT 24
Finished Jul 30 06:41:46 PM PDT 24
Peak memory 198056 kb
Host smart-65d73a8e-adc6-441a-8867-0e6a55b7468c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298136641 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_glitch.1298136641
Directory /workspace/36.pwrmgr_glitch/latest

Test location /workspace/coverage/default/36.pwrmgr_global_esc.2375354878
Short name T621
Test name
Test status
Simulation time 33595758 ps
CPU time 0.57 seconds
Started Jul 30 06:41:52 PM PDT 24
Finished Jul 30 06:41:53 PM PDT 24
Peak memory 198068 kb
Host smart-80141340-25ff-4d44-a882-2090d3357d86
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375354878 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_global_esc.2375354878
Directory /workspace/36.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/36.pwrmgr_lowpower_invalid.2718738560
Short name T183
Test name
Test status
Simulation time 66780267 ps
CPU time 0.67 seconds
Started Jul 30 06:41:44 PM PDT 24
Finished Jul 30 06:41:44 PM PDT 24
Peak memory 201416 kb
Host smart-46be07a0-eb07-4b71-9f53-8f0b142b05ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718738560 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_lowpower_inval
id.2718738560
Directory /workspace/36.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/36.pwrmgr_reset.3549977512
Short name T557
Test name
Test status
Simulation time 89561581 ps
CPU time 0.73 seconds
Started Jul 30 06:41:55 PM PDT 24
Finished Jul 30 06:41:56 PM PDT 24
Peak memory 198436 kb
Host smart-c7863e37-02d8-4cd5-9562-e352cd19af8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549977512 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset.3549977512
Directory /workspace/36.pwrmgr_reset/latest

Test location /workspace/coverage/default/36.pwrmgr_reset_invalid.4085971940
Short name T572
Test name
Test status
Simulation time 118795174 ps
CPU time 0.93 seconds
Started Jul 30 06:41:47 PM PDT 24
Finished Jul 30 06:41:48 PM PDT 24
Peak memory 209448 kb
Host smart-51fc05f1-72da-4f07-9c10-d1d8ce0fcda9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085971940 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset_invalid.4085971940
Directory /workspace/36.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/36.pwrmgr_sec_cm_rstmgr_intersig_mubi.1690924022
Short name T244
Test name
Test status
Simulation time 68737194 ps
CPU time 0.8 seconds
Started Jul 30 06:41:45 PM PDT 24
Finished Jul 30 06:41:46 PM PDT 24
Peak memory 199208 kb
Host smart-b0053a56-36c1-46d8-9c29-57d838432aa0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690924022 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1690924022
Directory /workspace/36.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/36.pwrmgr_smoke.3622080733
Short name T397
Test name
Test status
Simulation time 73440041 ps
CPU time 0.61 seconds
Started Jul 30 06:41:46 PM PDT 24
Finished Jul 30 06:41:47 PM PDT 24
Peak memory 198476 kb
Host smart-f90ca171-9c96-43a8-aedf-a3d134b74d9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622080733 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_smoke.3622080733
Directory /workspace/36.pwrmgr_smoke/latest

Test location /workspace/coverage/default/37.pwrmgr_aborted_low_power.3487650294
Short name T415
Test name
Test status
Simulation time 21344298 ps
CPU time 0.7 seconds
Started Jul 30 06:42:22 PM PDT 24
Finished Jul 30 06:42:23 PM PDT 24
Peak memory 199124 kb
Host smart-a507bb20-5785-45d3-973f-df25d2aa4d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487650294 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_aborted_low_power.3487650294
Directory /workspace/37.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/37.pwrmgr_disable_rom_integrity_check.2369525598
Short name T139
Test name
Test status
Simulation time 73956038 ps
CPU time 0.67 seconds
Started Jul 30 06:41:46 PM PDT 24
Finished Jul 30 06:41:47 PM PDT 24
Peak memory 198380 kb
Host smart-29b6be62-b3d7-4be5-be5b-9e7e07072f2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369525598 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_dis
able_rom_integrity_check.2369525598
Directory /workspace/37.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/37.pwrmgr_esc_clk_rst_malfunc.162099685
Short name T268
Test name
Test status
Simulation time 38456542 ps
CPU time 0.64 seconds
Started Jul 30 06:41:47 PM PDT 24
Finished Jul 30 06:41:48 PM PDT 24
Peak memory 198072 kb
Host smart-c35df79c-3140-42ff-acba-5b3edc090343
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162099685 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_esc_clk_rst_
malfunc.162099685
Directory /workspace/37.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/37.pwrmgr_escalation_timeout.3642320757
Short name T531
Test name
Test status
Simulation time 631774202 ps
CPU time 1 seconds
Started Jul 30 06:41:49 PM PDT 24
Finished Jul 30 06:41:50 PM PDT 24
Peak memory 198080 kb
Host smart-fdcbb898-962a-4df8-beb1-45d5146a68f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642320757 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_escalation_timeout.3642320757
Directory /workspace/37.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/37.pwrmgr_glitch.1407828168
Short name T220
Test name
Test status
Simulation time 75080435 ps
CPU time 0.62 seconds
Started Jul 30 06:41:43 PM PDT 24
Finished Jul 30 06:41:44 PM PDT 24
Peak memory 198176 kb
Host smart-992b9702-91d2-44a1-8da1-c00ae2b27411
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407828168 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_glitch.1407828168
Directory /workspace/37.pwrmgr_glitch/latest

Test location /workspace/coverage/default/37.pwrmgr_global_esc.2461156693
Short name T39
Test name
Test status
Simulation time 46604474 ps
CPU time 0.63 seconds
Started Jul 30 06:42:06 PM PDT 24
Finished Jul 30 06:42:07 PM PDT 24
Peak memory 198028 kb
Host smart-4aa2a0ca-a621-4627-b908-20b6e7d7b64b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461156693 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_global_esc.2461156693
Directory /workspace/37.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/37.pwrmgr_lowpower_invalid.954577881
Short name T399
Test name
Test status
Simulation time 41149529 ps
CPU time 0.7 seconds
Started Jul 30 06:42:17 PM PDT 24
Finished Jul 30 06:42:18 PM PDT 24
Peak memory 201424 kb
Host smart-87d5e613-6e6a-4c82-bb74-bf0b1c53b872
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954577881 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_lowpower_invali
d.954577881
Directory /workspace/37.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/37.pwrmgr_reset.3782218215
Short name T546
Test name
Test status
Simulation time 108293146 ps
CPU time 0.75 seconds
Started Jul 30 06:42:01 PM PDT 24
Finished Jul 30 06:42:02 PM PDT 24
Peak memory 199052 kb
Host smart-87a5b083-9d84-48a3-bd42-77883fe81f87
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782218215 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset.3782218215
Directory /workspace/37.pwrmgr_reset/latest

Test location /workspace/coverage/default/37.pwrmgr_reset_invalid.1627604075
Short name T457
Test name
Test status
Simulation time 187086405 ps
CPU time 0.77 seconds
Started Jul 30 06:41:48 PM PDT 24
Finished Jul 30 06:41:49 PM PDT 24
Peak memory 209468 kb
Host smart-29f04352-e8e6-4a79-a700-d2feec58ec6a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627604075 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset_invalid.1627604075
Directory /workspace/37.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/37.pwrmgr_sec_cm_rstmgr_intersig_mubi.1226227956
Short name T484
Test name
Test status
Simulation time 90868008 ps
CPU time 0.88 seconds
Started Jul 30 06:42:19 PM PDT 24
Finished Jul 30 06:42:21 PM PDT 24
Peak memory 199128 kb
Host smart-66f6d217-bee3-418b-9f46-250cb72fa91a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226227956 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1226227956
Directory /workspace/37.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/37.pwrmgr_smoke.2747563757
Short name T12
Test name
Test status
Simulation time 28398490 ps
CPU time 0.68 seconds
Started Jul 30 06:41:50 PM PDT 24
Finished Jul 30 06:41:51 PM PDT 24
Peak memory 199352 kb
Host smart-d5c2e844-8a83-4df6-85f4-848b6176fc86
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747563757 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_smoke.2747563757
Directory /workspace/37.pwrmgr_smoke/latest

Test location /workspace/coverage/default/38.pwrmgr_aborted_low_power.4097780875
Short name T507
Test name
Test status
Simulation time 45565748 ps
CPU time 0.62 seconds
Started Jul 30 06:41:56 PM PDT 24
Finished Jul 30 06:41:57 PM PDT 24
Peak memory 198636 kb
Host smart-9e2fa47f-9feb-4938-b8f3-9aa5ea79c75f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097780875 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_aborted_low_power.4097780875
Directory /workspace/38.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/38.pwrmgr_esc_clk_rst_malfunc.351446849
Short name T9
Test name
Test status
Simulation time 39143960 ps
CPU time 0.61 seconds
Started Jul 30 06:41:56 PM PDT 24
Finished Jul 30 06:41:57 PM PDT 24
Peak memory 198048 kb
Host smart-ea017359-2b58-4438-9c32-5179deebef94
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351446849 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_esc_clk_rst_
malfunc.351446849
Directory /workspace/38.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/38.pwrmgr_escalation_timeout.3083423982
Short name T336
Test name
Test status
Simulation time 187500257 ps
CPU time 0.92 seconds
Started Jul 30 06:42:14 PM PDT 24
Finished Jul 30 06:42:15 PM PDT 24
Peak memory 198460 kb
Host smart-ac85f328-796c-436f-be12-f663541381f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083423982 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_escalation_timeout.3083423982
Directory /workspace/38.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/38.pwrmgr_glitch.1333056608
Short name T619
Test name
Test status
Simulation time 63329406 ps
CPU time 0.68 seconds
Started Jul 30 06:41:59 PM PDT 24
Finished Jul 30 06:41:59 PM PDT 24
Peak memory 197400 kb
Host smart-b37495b3-8b78-4064-a281-e20ed7522c27
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333056608 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_glitch.1333056608
Directory /workspace/38.pwrmgr_glitch/latest

Test location /workspace/coverage/default/38.pwrmgr_global_esc.1951792980
Short name T605
Test name
Test status
Simulation time 57319939 ps
CPU time 0.65 seconds
Started Jul 30 06:41:46 PM PDT 24
Finished Jul 30 06:41:47 PM PDT 24
Peak memory 198088 kb
Host smart-4cc0e362-fad3-4580-a4fb-f837b784d078
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951792980 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_global_esc.1951792980
Directory /workspace/38.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/38.pwrmgr_reset.748138677
Short name T230
Test name
Test status
Simulation time 67548010 ps
CPU time 0.64 seconds
Started Jul 30 06:41:43 PM PDT 24
Finished Jul 30 06:41:44 PM PDT 24
Peak memory 198240 kb
Host smart-d0246015-4cf0-4992-be38-ee05b7338eb0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748138677 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset.748138677
Directory /workspace/38.pwrmgr_reset/latest

Test location /workspace/coverage/default/38.pwrmgr_reset_invalid.3257857020
Short name T441
Test name
Test status
Simulation time 120054569 ps
CPU time 0.81 seconds
Started Jul 30 06:41:46 PM PDT 24
Finished Jul 30 06:41:47 PM PDT 24
Peak memory 209584 kb
Host smart-a1b5ac80-6351-4e48-a56b-86ccca2dc57c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257857020 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset_invalid.3257857020
Directory /workspace/38.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/38.pwrmgr_smoke.3997953859
Short name T36
Test name
Test status
Simulation time 31585081 ps
CPU time 0.67 seconds
Started Jul 30 06:41:58 PM PDT 24
Finished Jul 30 06:41:58 PM PDT 24
Peak memory 198532 kb
Host smart-c33f07fe-cd53-4579-92f5-e52e7fdc8cd1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997953859 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_smoke.3997953859
Directory /workspace/38.pwrmgr_smoke/latest

Test location /workspace/coverage/default/39.pwrmgr_aborted_low_power.3683361863
Short name T372
Test name
Test status
Simulation time 46505399 ps
CPU time 0.88 seconds
Started Jul 30 06:41:44 PM PDT 24
Finished Jul 30 06:41:45 PM PDT 24
Peak memory 200360 kb
Host smart-8aa3e2e2-8588-46b8-8c20-72947c4e4bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683361863 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_aborted_low_power.3683361863
Directory /workspace/39.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/39.pwrmgr_disable_rom_integrity_check.2074891227
Short name T16
Test name
Test status
Simulation time 75134779 ps
CPU time 0.68 seconds
Started Jul 30 06:42:05 PM PDT 24
Finished Jul 30 06:42:06 PM PDT 24
Peak memory 199248 kb
Host smart-743b9f66-d31a-43ce-9b59-8b044ff8277a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074891227 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_dis
able_rom_integrity_check.2074891227
Directory /workspace/39.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/39.pwrmgr_esc_clk_rst_malfunc.3755367288
Short name T132
Test name
Test status
Simulation time 42914241 ps
CPU time 0.57 seconds
Started Jul 30 06:41:47 PM PDT 24
Finished Jul 30 06:41:48 PM PDT 24
Peak memory 197316 kb
Host smart-12d8fe7c-8f66-4497-8ebf-c3b420b36497
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755367288 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_esc_clk_rst
_malfunc.3755367288
Directory /workspace/39.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/39.pwrmgr_escalation_timeout.3571521115
Short name T606
Test name
Test status
Simulation time 194600776 ps
CPU time 0.96 seconds
Started Jul 30 06:42:03 PM PDT 24
Finished Jul 30 06:42:04 PM PDT 24
Peak memory 198080 kb
Host smart-6d3a6f9f-699a-46b4-b07b-5096d104f0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571521115 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_escalation_timeout.3571521115
Directory /workspace/39.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/39.pwrmgr_glitch.3690196779
Short name T262
Test name
Test status
Simulation time 35511332 ps
CPU time 0.65 seconds
Started Jul 30 06:41:57 PM PDT 24
Finished Jul 30 06:41:58 PM PDT 24
Peak memory 197932 kb
Host smart-3a71cc35-23c5-4b30-8798-b19ab1634c5b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690196779 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_glitch.3690196779
Directory /workspace/39.pwrmgr_glitch/latest

Test location /workspace/coverage/default/39.pwrmgr_global_esc.1280740260
Short name T482
Test name
Test status
Simulation time 74011721 ps
CPU time 0.6 seconds
Started Jul 30 06:41:54 PM PDT 24
Finished Jul 30 06:41:55 PM PDT 24
Peak memory 198112 kb
Host smart-b2845b70-3b6e-4016-ab4f-ba7c5a801a6b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280740260 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_global_esc.1280740260
Directory /workspace/39.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/39.pwrmgr_lowpower_invalid.3081613527
Short name T168
Test name
Test status
Simulation time 79767591 ps
CPU time 0.65 seconds
Started Jul 30 06:41:57 PM PDT 24
Finished Jul 30 06:41:58 PM PDT 24
Peak memory 201404 kb
Host smart-ea5b52f2-ec1f-4747-9843-84040d8daefa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081613527 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_lowpower_inval
id.3081613527
Directory /workspace/39.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/39.pwrmgr_reset.874510005
Short name T447
Test name
Test status
Simulation time 51246505 ps
CPU time 0.71 seconds
Started Jul 30 06:42:05 PM PDT 24
Finished Jul 30 06:42:06 PM PDT 24
Peak memory 199132 kb
Host smart-36dc25ed-094a-450f-84b9-9c3a82e46bcf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874510005 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset.874510005
Directory /workspace/39.pwrmgr_reset/latest

Test location /workspace/coverage/default/39.pwrmgr_reset_invalid.2282320096
Short name T581
Test name
Test status
Simulation time 145273989 ps
CPU time 0.78 seconds
Started Jul 30 06:42:22 PM PDT 24
Finished Jul 30 06:42:23 PM PDT 24
Peak memory 209488 kb
Host smart-587d3d0a-b72e-4a60-a158-fa8ec8571169
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282320096 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset_invalid.2282320096
Directory /workspace/39.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/39.pwrmgr_sec_cm_rstmgr_intersig_mubi.340906855
Short name T341
Test name
Test status
Simulation time 51020613 ps
CPU time 0.87 seconds
Started Jul 30 06:42:06 PM PDT 24
Finished Jul 30 06:42:06 PM PDT 24
Peak memory 199280 kb
Host smart-23e3495f-36f6-43d5-89dc-48cb122aa6d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340906855 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_rstmgr_intersig_
mubi.340906855
Directory /workspace/39.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/39.pwrmgr_smoke.1357026255
Short name T604
Test name
Test status
Simulation time 30544872 ps
CPU time 0.69 seconds
Started Jul 30 06:41:52 PM PDT 24
Finished Jul 30 06:41:53 PM PDT 24
Peak memory 198588 kb
Host smart-d137975b-18c8-4ea1-a5f2-4103a42a845b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357026255 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_smoke.1357026255
Directory /workspace/39.pwrmgr_smoke/latest

Test location /workspace/coverage/default/4.pwrmgr_aborted_low_power.1008624172
Short name T529
Test name
Test status
Simulation time 31327543 ps
CPU time 0.86 seconds
Started Jul 30 06:40:29 PM PDT 24
Finished Jul 30 06:40:30 PM PDT 24
Peak memory 199228 kb
Host smart-d4059ef8-b177-400a-b1d3-923a4929a1a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008624172 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_aborted_low_power.1008624172
Directory /workspace/4.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/4.pwrmgr_disable_rom_integrity_check.1511911519
Short name T513
Test name
Test status
Simulation time 64686867 ps
CPU time 0.73 seconds
Started Jul 30 06:40:29 PM PDT 24
Finished Jul 30 06:40:30 PM PDT 24
Peak memory 199152 kb
Host smart-0c5ca543-4742-41f9-95ff-8bf8f309b418
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511911519 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_disa
ble_rom_integrity_check.1511911519
Directory /workspace/4.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/4.pwrmgr_esc_clk_rst_malfunc.1704119877
Short name T324
Test name
Test status
Simulation time 28914560 ps
CPU time 0.62 seconds
Started Jul 30 06:40:26 PM PDT 24
Finished Jul 30 06:40:27 PM PDT 24
Peak memory 198056 kb
Host smart-c67dd832-3668-46b0-a88e-a00c79a265b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704119877 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_esc_clk_rst_
malfunc.1704119877
Directory /workspace/4.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/4.pwrmgr_escalation_timeout.832119635
Short name T561
Test name
Test status
Simulation time 273500100 ps
CPU time 0.99 seconds
Started Jul 30 06:40:33 PM PDT 24
Finished Jul 30 06:40:34 PM PDT 24
Peak memory 198372 kb
Host smart-acc292a7-5f0d-428f-99d5-3db02c9ede13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832119635 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_escalation_timeout.832119635
Directory /workspace/4.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/4.pwrmgr_glitch.3242649336
Short name T222
Test name
Test status
Simulation time 43208843 ps
CPU time 0.63 seconds
Started Jul 30 06:40:32 PM PDT 24
Finished Jul 30 06:40:32 PM PDT 24
Peak memory 198140 kb
Host smart-e5524ad1-9290-44d1-8ac6-4b15d788c3bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242649336 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_glitch.3242649336
Directory /workspace/4.pwrmgr_glitch/latest

Test location /workspace/coverage/default/4.pwrmgr_global_esc.1038963814
Short name T492
Test name
Test status
Simulation time 30245769 ps
CPU time 0.61 seconds
Started Jul 30 06:40:27 PM PDT 24
Finished Jul 30 06:40:28 PM PDT 24
Peak memory 198100 kb
Host smart-eb9d3aba-f7b0-47da-98bb-8d299c19a0e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038963814 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_global_esc.1038963814
Directory /workspace/4.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/4.pwrmgr_lowpower_invalid.2990965805
Short name T201
Test name
Test status
Simulation time 44584113 ps
CPU time 0.75 seconds
Started Jul 30 06:40:30 PM PDT 24
Finished Jul 30 06:40:31 PM PDT 24
Peak memory 201496 kb
Host smart-4963d0c8-4ca5-4ec9-8f5f-45aed622492e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990965805 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_lowpower_invali
d.2990965805
Directory /workspace/4.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/4.pwrmgr_reset.1174805216
Short name T240
Test name
Test status
Simulation time 122655891 ps
CPU time 0.62 seconds
Started Jul 30 06:40:27 PM PDT 24
Finished Jul 30 06:40:28 PM PDT 24
Peak memory 198020 kb
Host smart-f4cb837d-d221-4e64-b207-8a69f798f887
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174805216 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset.1174805216
Directory /workspace/4.pwrmgr_reset/latest

Test location /workspace/coverage/default/4.pwrmgr_reset_invalid.2944210528
Short name T373
Test name
Test status
Simulation time 92232279 ps
CPU time 1.04 seconds
Started Jul 30 06:40:34 PM PDT 24
Finished Jul 30 06:40:35 PM PDT 24
Peak memory 209264 kb
Host smart-cb6ead9b-d456-4cc6-aba3-900c0069644b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944210528 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset_invalid.2944210528
Directory /workspace/4.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm.2838264852
Short name T20
Test name
Test status
Simulation time 401489696 ps
CPU time 1.24 seconds
Started Jul 30 06:40:33 PM PDT 24
Finished Jul 30 06:40:35 PM PDT 24
Peak memory 216928 kb
Host smart-80f71390-b40f-44a7-aecf-49bb1031cf4b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838264852 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm.2838264852
Directory /workspace/4.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm_rstmgr_intersig_mubi.1398824116
Short name T351
Test name
Test status
Simulation time 174910579 ps
CPU time 0.87 seconds
Started Jul 30 06:40:26 PM PDT 24
Finished Jul 30 06:40:27 PM PDT 24
Peak memory 199380 kb
Host smart-8473c302-6a35-412e-914f-846169990b13
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398824116 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_rstmgr_intersig_
mubi.1398824116
Directory /workspace/4.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/4.pwrmgr_smoke.331140454
Short name T504
Test name
Test status
Simulation time 28362241 ps
CPU time 0.66 seconds
Started Jul 30 06:40:34 PM PDT 24
Finished Jul 30 06:40:35 PM PDT 24
Peak memory 199388 kb
Host smart-de596084-62ca-408b-a4bb-4bb62021e5e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331140454 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_smoke.331140454
Directory /workspace/4.pwrmgr_smoke/latest

Test location /workspace/coverage/default/40.pwrmgr_aborted_low_power.4025187022
Short name T364
Test name
Test status
Simulation time 33026509 ps
CPU time 0.79 seconds
Started Jul 30 06:42:02 PM PDT 24
Finished Jul 30 06:42:03 PM PDT 24
Peak memory 200172 kb
Host smart-768235b1-8402-4126-b51d-20a22f1c8a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025187022 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_aborted_low_power.4025187022
Directory /workspace/40.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/40.pwrmgr_disable_rom_integrity_check.3597257855
Short name T148
Test name
Test status
Simulation time 73810767 ps
CPU time 0.68 seconds
Started Jul 30 06:42:14 PM PDT 24
Finished Jul 30 06:42:15 PM PDT 24
Peak memory 198548 kb
Host smart-7cbc4036-250e-4361-82da-84adf2d514fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597257855 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_dis
able_rom_integrity_check.3597257855
Directory /workspace/40.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/40.pwrmgr_esc_clk_rst_malfunc.4042471881
Short name T294
Test name
Test status
Simulation time 39440850 ps
CPU time 0.57 seconds
Started Jul 30 06:41:44 PM PDT 24
Finished Jul 30 06:41:44 PM PDT 24
Peak memory 198096 kb
Host smart-1466e61e-5066-4a9e-9a55-77c3bb70a195
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042471881 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_esc_clk_rst
_malfunc.4042471881
Directory /workspace/40.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/40.pwrmgr_escalation_timeout.2783998480
Short name T252
Test name
Test status
Simulation time 164052648 ps
CPU time 0.97 seconds
Started Jul 30 06:42:00 PM PDT 24
Finished Jul 30 06:42:01 PM PDT 24
Peak memory 197808 kb
Host smart-3d930152-3a6e-42ad-b5e0-9e39cf9cd3f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783998480 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_escalation_timeout.2783998480
Directory /workspace/40.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/40.pwrmgr_glitch.1044789425
Short name T407
Test name
Test status
Simulation time 59839289 ps
CPU time 0.64 seconds
Started Jul 30 06:42:15 PM PDT 24
Finished Jul 30 06:42:16 PM PDT 24
Peak memory 198108 kb
Host smart-27aa7b26-0458-4d2f-bfc6-09f38836ef24
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044789425 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_glitch.1044789425
Directory /workspace/40.pwrmgr_glitch/latest

Test location /workspace/coverage/default/40.pwrmgr_global_esc.3325650204
Short name T556
Test name
Test status
Simulation time 72736714 ps
CPU time 0.67 seconds
Started Jul 30 06:42:22 PM PDT 24
Finished Jul 30 06:42:23 PM PDT 24
Peak memory 198084 kb
Host smart-0f6193a9-b6c8-41cf-a2c1-80f0a827e0bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325650204 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_global_esc.3325650204
Directory /workspace/40.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/40.pwrmgr_lowpower_invalid.526236883
Short name T478
Test name
Test status
Simulation time 75925679 ps
CPU time 0.67 seconds
Started Jul 30 06:42:00 PM PDT 24
Finished Jul 30 06:42:01 PM PDT 24
Peak memory 201092 kb
Host smart-03ebe60f-e870-4ed2-8db4-d9fbc7fe276a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526236883 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_lowpower_invali
d.526236883
Directory /workspace/40.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/40.pwrmgr_reset.1277389761
Short name T212
Test name
Test status
Simulation time 88906372 ps
CPU time 0.98 seconds
Started Jul 30 06:42:02 PM PDT 24
Finished Jul 30 06:42:03 PM PDT 24
Peak memory 198532 kb
Host smart-78ba30f7-2a1b-4007-a7f9-a75cbcf3aace
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277389761 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset.1277389761
Directory /workspace/40.pwrmgr_reset/latest

Test location /workspace/coverage/default/40.pwrmgr_reset_invalid.1448607570
Short name T279
Test name
Test status
Simulation time 112430291 ps
CPU time 0.9 seconds
Started Jul 30 06:42:18 PM PDT 24
Finished Jul 30 06:42:19 PM PDT 24
Peak memory 209456 kb
Host smart-9dd27eba-6eb8-4f9b-8898-0b4202a0f164
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448607570 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset_invalid.1448607570
Directory /workspace/40.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/40.pwrmgr_sec_cm_rstmgr_intersig_mubi.484480314
Short name T306
Test name
Test status
Simulation time 50801416 ps
CPU time 0.89 seconds
Started Jul 30 06:41:45 PM PDT 24
Finished Jul 30 06:41:46 PM PDT 24
Peak memory 199420 kb
Host smart-7f64f1e0-b7d9-4b4a-8032-b3662e338ffa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484480314 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_rstmgr_intersig_
mubi.484480314
Directory /workspace/40.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/40.pwrmgr_smoke.1669858190
Short name T142
Test name
Test status
Simulation time 32812005 ps
CPU time 0.66 seconds
Started Jul 30 06:42:06 PM PDT 24
Finished Jul 30 06:42:06 PM PDT 24
Peak memory 199472 kb
Host smart-3952cffe-602e-41a5-ab9c-067c736053d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669858190 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_smoke.1669858190
Directory /workspace/40.pwrmgr_smoke/latest

Test location /workspace/coverage/default/41.pwrmgr_aborted_low_power.384275504
Short name T296
Test name
Test status
Simulation time 21640730 ps
CPU time 0.8 seconds
Started Jul 30 06:42:24 PM PDT 24
Finished Jul 30 06:42:25 PM PDT 24
Peak memory 200112 kb
Host smart-cbd3ef08-c403-428b-9865-34860cd97c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384275504 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_aborted_low_power.384275504
Directory /workspace/41.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/41.pwrmgr_disable_rom_integrity_check.2608801776
Short name T161
Test name
Test status
Simulation time 71594345 ps
CPU time 0.62 seconds
Started Jul 30 06:43:29 PM PDT 24
Finished Jul 30 06:43:29 PM PDT 24
Peak memory 198136 kb
Host smart-d54b08c4-8693-4eb3-a2c4-bde5e413c774
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608801776 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_dis
able_rom_integrity_check.2608801776
Directory /workspace/41.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/41.pwrmgr_esc_clk_rst_malfunc.1807034603
Short name T420
Test name
Test status
Simulation time 45470025 ps
CPU time 0.58 seconds
Started Jul 30 06:42:19 PM PDT 24
Finished Jul 30 06:42:20 PM PDT 24
Peak memory 198012 kb
Host smart-18dabbb9-c523-4929-b26e-0346752157d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807034603 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_esc_clk_rst
_malfunc.1807034603
Directory /workspace/41.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/41.pwrmgr_escalation_timeout.234019122
Short name T431
Test name
Test status
Simulation time 599495350 ps
CPU time 0.94 seconds
Started Jul 30 06:42:04 PM PDT 24
Finished Jul 30 06:42:05 PM PDT 24
Peak memory 198124 kb
Host smart-df9af4f9-0e4a-4bc7-acc9-117aded38a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234019122 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_escalation_timeout.234019122
Directory /workspace/41.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/41.pwrmgr_glitch.640984183
Short name T3
Test name
Test status
Simulation time 40386051 ps
CPU time 0.62 seconds
Started Jul 30 06:41:45 PM PDT 24
Finished Jul 30 06:41:46 PM PDT 24
Peak memory 197308 kb
Host smart-a3fb8bac-2689-47de-a5a3-3cde9051aa40
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640984183 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_glitch.640984183
Directory /workspace/41.pwrmgr_glitch/latest

Test location /workspace/coverage/default/41.pwrmgr_global_esc.2839353104
Short name T327
Test name
Test status
Simulation time 42888406 ps
CPU time 0.62 seconds
Started Jul 30 06:42:02 PM PDT 24
Finished Jul 30 06:42:03 PM PDT 24
Peak memory 197792 kb
Host smart-fea0b484-3c12-42f3-b272-77ce3ff2ece6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839353104 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_global_esc.2839353104
Directory /workspace/41.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/41.pwrmgr_lowpower_invalid.1651384297
Short name T169
Test name
Test status
Simulation time 39934433 ps
CPU time 0.69 seconds
Started Jul 30 06:41:45 PM PDT 24
Finished Jul 30 06:41:45 PM PDT 24
Peak memory 201464 kb
Host smart-3a44197a-c872-4a78-8782-f597fa9c2c96
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651384297 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_lowpower_inval
id.1651384297
Directory /workspace/41.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/41.pwrmgr_reset.2966607232
Short name T559
Test name
Test status
Simulation time 57411001 ps
CPU time 0.71 seconds
Started Jul 30 06:42:24 PM PDT 24
Finished Jul 30 06:42:25 PM PDT 24
Peak memory 199096 kb
Host smart-14e633ea-6b0a-4e6b-9e0c-6e3153bdc6a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966607232 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset.2966607232
Directory /workspace/41.pwrmgr_reset/latest

Test location /workspace/coverage/default/41.pwrmgr_reset_invalid.4110469441
Short name T356
Test name
Test status
Simulation time 114066792 ps
CPU time 1.17 seconds
Started Jul 30 06:42:49 PM PDT 24
Finished Jul 30 06:42:51 PM PDT 24
Peak memory 208440 kb
Host smart-3ac18f0b-2b0e-4bcb-bbeb-25c447fd2049
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110469441 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset_invalid.4110469441
Directory /workspace/41.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/41.pwrmgr_sec_cm_rstmgr_intersig_mubi.1085238464
Short name T311
Test name
Test status
Simulation time 53196781 ps
CPU time 0.85 seconds
Started Jul 30 06:41:53 PM PDT 24
Finished Jul 30 06:41:54 PM PDT 24
Peak memory 199240 kb
Host smart-5e4a5991-cf2e-405a-8779-cf81abdf7827
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085238464 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1085238464
Directory /workspace/41.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/42.pwrmgr_aborted_low_power.3296345183
Short name T514
Test name
Test status
Simulation time 107108709 ps
CPU time 0.76 seconds
Started Jul 30 06:42:07 PM PDT 24
Finished Jul 30 06:42:08 PM PDT 24
Peak memory 199984 kb
Host smart-b51ca5a3-d6a1-4da2-a945-6058f72057b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296345183 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_aborted_low_power.3296345183
Directory /workspace/42.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/42.pwrmgr_disable_rom_integrity_check.595622673
Short name T134
Test name
Test status
Simulation time 61190737 ps
CPU time 0.69 seconds
Started Jul 30 06:42:05 PM PDT 24
Finished Jul 30 06:42:06 PM PDT 24
Peak memory 199164 kb
Host smart-58273a51-736a-48bf-9450-51ade724dda6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595622673 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_disa
ble_rom_integrity_check.595622673
Directory /workspace/42.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/42.pwrmgr_esc_clk_rst_malfunc.4015491483
Short name T281
Test name
Test status
Simulation time 42293840 ps
CPU time 0.61 seconds
Started Jul 30 06:42:08 PM PDT 24
Finished Jul 30 06:42:08 PM PDT 24
Peak memory 198000 kb
Host smart-9c2dcf59-1e8a-4a20-b2a7-2995dba0d1ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015491483 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_esc_clk_rst
_malfunc.4015491483
Directory /workspace/42.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/42.pwrmgr_escalation_timeout.717648899
Short name T442
Test name
Test status
Simulation time 584410038 ps
CPU time 0.94 seconds
Started Jul 30 06:41:54 PM PDT 24
Finished Jul 30 06:41:55 PM PDT 24
Peak memory 198160 kb
Host smart-f212cf44-2cef-46e9-ba02-97e875e63831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717648899 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_escalation_timeout.717648899
Directory /workspace/42.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/42.pwrmgr_glitch.61613612
Short name T90
Test name
Test status
Simulation time 34935447 ps
CPU time 0.57 seconds
Started Jul 30 06:41:51 PM PDT 24
Finished Jul 30 06:41:52 PM PDT 24
Peak memory 197384 kb
Host smart-0f9898e3-837a-4705-92c7-ec60b85c623d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61613612 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_glitch.61613612
Directory /workspace/42.pwrmgr_glitch/latest

Test location /workspace/coverage/default/42.pwrmgr_global_esc.4263753979
Short name T406
Test name
Test status
Simulation time 51776137 ps
CPU time 0.62 seconds
Started Jul 30 06:42:00 PM PDT 24
Finished Jul 30 06:42:00 PM PDT 24
Peak memory 198132 kb
Host smart-b2d459b6-e52a-4fbe-960f-8a78d4224cf4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263753979 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_global_esc.4263753979
Directory /workspace/42.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/42.pwrmgr_reset.2708813789
Short name T502
Test name
Test status
Simulation time 48346577 ps
CPU time 0.77 seconds
Started Jul 30 06:42:16 PM PDT 24
Finished Jul 30 06:42:17 PM PDT 24
Peak memory 199220 kb
Host smart-7ff5040f-1ba5-44c6-9326-234884fa2b81
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708813789 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset.2708813789
Directory /workspace/42.pwrmgr_reset/latest

Test location /workspace/coverage/default/42.pwrmgr_reset_invalid.1076790994
Short name T613
Test name
Test status
Simulation time 178375839 ps
CPU time 0.79 seconds
Started Jul 30 06:41:57 PM PDT 24
Finished Jul 30 06:41:58 PM PDT 24
Peak memory 209564 kb
Host smart-8cb46e24-bfa6-4602-b4fe-0d73751e8968
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076790994 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset_invalid.1076790994
Directory /workspace/42.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/42.pwrmgr_sec_cm_rstmgr_intersig_mubi.412859779
Short name T350
Test name
Test status
Simulation time 54223356 ps
CPU time 0.72 seconds
Started Jul 30 06:41:48 PM PDT 24
Finished Jul 30 06:41:49 PM PDT 24
Peak memory 198156 kb
Host smart-7f6623f3-d059-4f20-b76e-b6553a5ec442
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412859779 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_rstmgr_intersig_
mubi.412859779
Directory /workspace/42.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/42.pwrmgr_smoke.185205328
Short name T67
Test name
Test status
Simulation time 63491097 ps
CPU time 0.62 seconds
Started Jul 30 06:42:01 PM PDT 24
Finished Jul 30 06:42:02 PM PDT 24
Peak memory 199372 kb
Host smart-535f7b75-d2d4-4def-8719-ecb5a9c9a55e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185205328 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_smoke.185205328
Directory /workspace/42.pwrmgr_smoke/latest

Test location /workspace/coverage/default/42.pwrmgr_stress_all.3287675002
Short name T368
Test name
Test status
Simulation time 112383407 ps
CPU time 0.7 seconds
Started Jul 30 06:41:57 PM PDT 24
Finished Jul 30 06:41:58 PM PDT 24
Peak memory 198860 kb
Host smart-c00268ab-70e5-4d27-8ca4-eba00a8cfcc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287675002 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_stress_all.3287675002
Directory /workspace/42.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/43.pwrmgr_aborted_low_power.1309323750
Short name T87
Test name
Test status
Simulation time 73142343 ps
CPU time 0.66 seconds
Started Jul 30 06:41:48 PM PDT 24
Finished Jul 30 06:41:49 PM PDT 24
Peak memory 199172 kb
Host smart-ef2ff520-126c-4fac-a7c9-9e24c579d03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309323750 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_aborted_low_power.1309323750
Directory /workspace/43.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/43.pwrmgr_disable_rom_integrity_check.3144916102
Short name T28
Test name
Test status
Simulation time 79585210 ps
CPU time 0.68 seconds
Started Jul 30 06:42:12 PM PDT 24
Finished Jul 30 06:42:13 PM PDT 24
Peak memory 198464 kb
Host smart-a6371681-3792-4f17-a8a8-9ce14a1f8754
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144916102 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_dis
able_rom_integrity_check.3144916102
Directory /workspace/43.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/43.pwrmgr_esc_clk_rst_malfunc.2614666004
Short name T390
Test name
Test status
Simulation time 38605899 ps
CPU time 0.64 seconds
Started Jul 30 06:41:55 PM PDT 24
Finished Jul 30 06:41:56 PM PDT 24
Peak memory 198052 kb
Host smart-5bf5ebda-1b40-46cc-bdc9-03762ca8e37d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614666004 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_esc_clk_rst
_malfunc.2614666004
Directory /workspace/43.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/43.pwrmgr_escalation_timeout.337811548
Short name T4
Test name
Test status
Simulation time 600932955 ps
CPU time 0.96 seconds
Started Jul 30 06:42:12 PM PDT 24
Finished Jul 30 06:42:13 PM PDT 24
Peak memory 198116 kb
Host smart-a0c80985-ee78-42bc-b617-5aeacf38ef68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337811548 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_escalation_timeout.337811548
Directory /workspace/43.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/43.pwrmgr_glitch.3170540368
Short name T534
Test name
Test status
Simulation time 82044848 ps
CPU time 0.6 seconds
Started Jul 30 06:42:05 PM PDT 24
Finished Jul 30 06:42:05 PM PDT 24
Peak memory 198068 kb
Host smart-939334c3-b700-46f5-99b0-d5c8bda61bbb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170540368 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_glitch.3170540368
Directory /workspace/43.pwrmgr_glitch/latest

Test location /workspace/coverage/default/43.pwrmgr_global_esc.759527665
Short name T396
Test name
Test status
Simulation time 64206258 ps
CPU time 0.61 seconds
Started Jul 30 06:42:03 PM PDT 24
Finished Jul 30 06:42:04 PM PDT 24
Peak memory 198092 kb
Host smart-317b4885-85ab-4026-a93d-1c88009f0b2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759527665 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_global_esc.759527665
Directory /workspace/43.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/43.pwrmgr_lowpower_invalid.3053863752
Short name T181
Test name
Test status
Simulation time 143655332 ps
CPU time 0.68 seconds
Started Jul 30 06:42:18 PM PDT 24
Finished Jul 30 06:42:19 PM PDT 24
Peak memory 201404 kb
Host smart-b28b81e4-42b6-4b4e-a2f7-aca9738edaba
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053863752 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_lowpower_inval
id.3053863752
Directory /workspace/43.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/43.pwrmgr_reset.2956141266
Short name T210
Test name
Test status
Simulation time 144163803 ps
CPU time 0.71 seconds
Started Jul 30 06:41:56 PM PDT 24
Finished Jul 30 06:41:57 PM PDT 24
Peak memory 198416 kb
Host smart-483bd491-e21c-4e54-b8bb-e4705074130c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956141266 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset.2956141266
Directory /workspace/43.pwrmgr_reset/latest

Test location /workspace/coverage/default/43.pwrmgr_reset_invalid.1420151511
Short name T42
Test name
Test status
Simulation time 115797893 ps
CPU time 0.9 seconds
Started Jul 30 06:42:09 PM PDT 24
Finished Jul 30 06:42:15 PM PDT 24
Peak memory 209484 kb
Host smart-61c71fdb-134f-41a1-b58d-c934b3353a34
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420151511 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset_invalid.1420151511
Directory /workspace/43.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/43.pwrmgr_sec_cm_rstmgr_intersig_mubi.2164296528
Short name T440
Test name
Test status
Simulation time 52782206 ps
CPU time 0.75 seconds
Started Jul 30 06:42:13 PM PDT 24
Finished Jul 30 06:42:14 PM PDT 24
Peak memory 198152 kb
Host smart-4557e08a-eda1-4347-b560-509e25a8f4c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164296528 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2164296528
Directory /workspace/43.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/43.pwrmgr_smoke.4122898146
Short name T541
Test name
Test status
Simulation time 75269675 ps
CPU time 0.61 seconds
Started Jul 30 06:41:50 PM PDT 24
Finished Jul 30 06:41:51 PM PDT 24
Peak memory 198528 kb
Host smart-46ea11c7-249a-4e55-b25d-19a1869b53e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122898146 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_smoke.4122898146
Directory /workspace/43.pwrmgr_smoke/latest

Test location /workspace/coverage/default/44.pwrmgr_aborted_low_power.1454463244
Short name T353
Test name
Test status
Simulation time 150857175 ps
CPU time 0.74 seconds
Started Jul 30 06:42:04 PM PDT 24
Finished Jul 30 06:42:05 PM PDT 24
Peak memory 198848 kb
Host smart-cabec5c4-a5e0-4141-82b5-4d08e628998b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454463244 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_aborted_low_power.1454463244
Directory /workspace/44.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/44.pwrmgr_disable_rom_integrity_check.2540035481
Short name T578
Test name
Test status
Simulation time 66413996 ps
CPU time 0.65 seconds
Started Jul 30 06:42:16 PM PDT 24
Finished Jul 30 06:42:17 PM PDT 24
Peak memory 199140 kb
Host smart-eeccd940-a2e0-4e2b-8554-6dc0c223874b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540035481 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_dis
able_rom_integrity_check.2540035481
Directory /workspace/44.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/44.pwrmgr_esc_clk_rst_malfunc.2081074632
Short name T590
Test name
Test status
Simulation time 38680552 ps
CPU time 0.65 seconds
Started Jul 30 06:42:07 PM PDT 24
Finished Jul 30 06:42:08 PM PDT 24
Peak memory 197364 kb
Host smart-efe36c5b-1f33-489a-af55-a02eb01dfa85
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081074632 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_esc_clk_rst
_malfunc.2081074632
Directory /workspace/44.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/44.pwrmgr_escalation_timeout.1715586822
Short name T627
Test name
Test status
Simulation time 633940996 ps
CPU time 0.97 seconds
Started Jul 30 06:42:03 PM PDT 24
Finished Jul 30 06:42:04 PM PDT 24
Peak memory 198416 kb
Host smart-a8660ab6-d98f-4dcd-a2fe-af533f77712d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715586822 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_escalation_timeout.1715586822
Directory /workspace/44.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/44.pwrmgr_glitch.142021441
Short name T214
Test name
Test status
Simulation time 55693251 ps
CPU time 0.71 seconds
Started Jul 30 06:42:11 PM PDT 24
Finished Jul 30 06:42:12 PM PDT 24
Peak memory 198112 kb
Host smart-0e2b1854-444a-4ca3-90df-cb8c44798dd3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142021441 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_glitch.142021441
Directory /workspace/44.pwrmgr_glitch/latest

Test location /workspace/coverage/default/44.pwrmgr_global_esc.3488092998
Short name T567
Test name
Test status
Simulation time 35220188 ps
CPU time 0.61 seconds
Started Jul 30 06:42:31 PM PDT 24
Finished Jul 30 06:42:32 PM PDT 24
Peak memory 198084 kb
Host smart-1097feb5-01f9-4653-836f-2b516d548962
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488092998 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_global_esc.3488092998
Directory /workspace/44.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/44.pwrmgr_lowpower_invalid.2121518585
Short name T570
Test name
Test status
Simulation time 51604614 ps
CPU time 0.67 seconds
Started Jul 30 06:42:02 PM PDT 24
Finished Jul 30 06:42:03 PM PDT 24
Peak memory 201400 kb
Host smart-b0104826-0272-483d-b8d4-02ffdd1b9245
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121518585 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_lowpower_inval
id.2121518585
Directory /workspace/44.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/44.pwrmgr_reset.305886322
Short name T467
Test name
Test status
Simulation time 243072826 ps
CPU time 0.76 seconds
Started Jul 30 06:42:17 PM PDT 24
Finished Jul 30 06:42:18 PM PDT 24
Peak memory 199140 kb
Host smart-799d271e-68a1-4f83-9edd-bd2fa575c0a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305886322 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset.305886322
Directory /workspace/44.pwrmgr_reset/latest

Test location /workspace/coverage/default/44.pwrmgr_reset_invalid.1224581573
Short name T404
Test name
Test status
Simulation time 106623806 ps
CPU time 0.92 seconds
Started Jul 30 06:42:24 PM PDT 24
Finished Jul 30 06:42:25 PM PDT 24
Peak memory 209640 kb
Host smart-f3667e62-b325-49cc-b6a0-b208224efbf9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224581573 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset_invalid.1224581573
Directory /workspace/44.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/44.pwrmgr_sec_cm_ctrl_config_regwen.1008647094
Short name T187
Test name
Test status
Simulation time 47674017 ps
CPU time 0.62 seconds
Started Jul 30 06:42:09 PM PDT 24
Finished Jul 30 06:42:10 PM PDT 24
Peak memory 198532 kb
Host smart-4b00c80d-0942-4387-8151-c855cf4d8a5b
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008647094 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_
cm_ctrl_config_regwen.1008647094
Directory /workspace/44.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/44.pwrmgr_sec_cm_rstmgr_intersig_mubi.1670540494
Short name T536
Test name
Test status
Simulation time 52793415 ps
CPU time 0.85 seconds
Started Jul 30 06:42:15 PM PDT 24
Finished Jul 30 06:42:16 PM PDT 24
Peak memory 198088 kb
Host smart-50a00448-a91e-4200-a3fd-0a74d71bb216
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670540494 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1670540494
Directory /workspace/44.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/44.pwrmgr_smoke.2522837450
Short name T612
Test name
Test status
Simulation time 38118356 ps
CPU time 0.65 seconds
Started Jul 30 06:42:17 PM PDT 24
Finished Jul 30 06:42:18 PM PDT 24
Peak memory 199384 kb
Host smart-1bb246ae-534d-4eef-8d81-c6164da51bbf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522837450 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_smoke.2522837450
Directory /workspace/44.pwrmgr_smoke/latest

Test location /workspace/coverage/default/45.pwrmgr_aborted_low_power.265325602
Short name T35
Test name
Test status
Simulation time 28965518 ps
CPU time 0.95 seconds
Started Jul 30 06:42:03 PM PDT 24
Finished Jul 30 06:42:04 PM PDT 24
Peak memory 200260 kb
Host smart-73a8fb37-19a3-46b5-9138-c60aac794a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265325602 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_aborted_low_power.265325602
Directory /workspace/45.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/45.pwrmgr_disable_rom_integrity_check.1405514366
Short name T305
Test name
Test status
Simulation time 54082083 ps
CPU time 0.8 seconds
Started Jul 30 06:42:29 PM PDT 24
Finished Jul 30 06:42:30 PM PDT 24
Peak memory 198608 kb
Host smart-a95cd176-97d0-43a7-9fee-1facdfb6ee21
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405514366 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_dis
able_rom_integrity_check.1405514366
Directory /workspace/45.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/45.pwrmgr_esc_clk_rst_malfunc.4061195091
Short name T312
Test name
Test status
Simulation time 29047923 ps
CPU time 0.61 seconds
Started Jul 30 06:42:29 PM PDT 24
Finished Jul 30 06:42:30 PM PDT 24
Peak memory 198004 kb
Host smart-f7dbe010-149f-4ec8-af31-1e36e128f377
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061195091 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_esc_clk_rst
_malfunc.4061195091
Directory /workspace/45.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/45.pwrmgr_escalation_timeout.3100134665
Short name T443
Test name
Test status
Simulation time 252345991 ps
CPU time 0.92 seconds
Started Jul 30 06:42:33 PM PDT 24
Finished Jul 30 06:42:34 PM PDT 24
Peak memory 198416 kb
Host smart-ea036d86-5afe-45ef-bd51-948def581055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100134665 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_escalation_timeout.3100134665
Directory /workspace/45.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/45.pwrmgr_glitch.1557001627
Short name T363
Test name
Test status
Simulation time 44718817 ps
CPU time 0.59 seconds
Started Jul 30 06:42:30 PM PDT 24
Finished Jul 30 06:42:31 PM PDT 24
Peak memory 198064 kb
Host smart-62640d2d-963b-493e-be48-85280abd0609
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557001627 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_glitch.1557001627
Directory /workspace/45.pwrmgr_glitch/latest

Test location /workspace/coverage/default/45.pwrmgr_global_esc.2452227539
Short name T383
Test name
Test status
Simulation time 227612134 ps
CPU time 0.66 seconds
Started Jul 30 06:42:24 PM PDT 24
Finished Jul 30 06:42:24 PM PDT 24
Peak memory 198488 kb
Host smart-d08f5905-42ad-4bfb-b4f6-d4bfbb5016cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452227539 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_global_esc.2452227539
Directory /workspace/45.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/45.pwrmgr_lowpower_invalid.2105749050
Short name T167
Test name
Test status
Simulation time 42543475 ps
CPU time 0.68 seconds
Started Jul 30 06:42:24 PM PDT 24
Finished Jul 30 06:42:25 PM PDT 24
Peak memory 201444 kb
Host smart-b8788e62-1204-452a-9274-6c3331928916
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105749050 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_lowpower_inval
id.2105749050
Directory /workspace/45.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/45.pwrmgr_reset.1087317536
Short name T325
Test name
Test status
Simulation time 66912898 ps
CPU time 0.73 seconds
Started Jul 30 06:42:21 PM PDT 24
Finished Jul 30 06:42:21 PM PDT 24
Peak memory 198384 kb
Host smart-ca375c34-c5bb-4211-bd30-18b679618ba2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087317536 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset.1087317536
Directory /workspace/45.pwrmgr_reset/latest

Test location /workspace/coverage/default/45.pwrmgr_reset_invalid.2108426477
Short name T320
Test name
Test status
Simulation time 146085625 ps
CPU time 0.8 seconds
Started Jul 30 06:42:37 PM PDT 24
Finished Jul 30 06:42:38 PM PDT 24
Peak memory 209468 kb
Host smart-9f02e2a9-3cd8-4ab2-a897-8b0dce3f72d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108426477 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset_invalid.2108426477
Directory /workspace/45.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/45.pwrmgr_sec_cm_rstmgr_intersig_mubi.2140602146
Short name T32
Test name
Test status
Simulation time 111229534 ps
CPU time 0.77 seconds
Started Jul 30 06:42:28 PM PDT 24
Finished Jul 30 06:42:29 PM PDT 24
Peak memory 198088 kb
Host smart-69ebcd65-f092-4702-856b-c37b58220027
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140602146 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2140602146
Directory /workspace/45.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/45.pwrmgr_smoke.4015000744
Short name T272
Test name
Test status
Simulation time 56191542 ps
CPU time 0.64 seconds
Started Jul 30 06:42:25 PM PDT 24
Finished Jul 30 06:42:25 PM PDT 24
Peak memory 199364 kb
Host smart-35b1e275-0c10-45aa-b36c-61d900f58ac6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015000744 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_smoke.4015000744
Directory /workspace/45.pwrmgr_smoke/latest

Test location /workspace/coverage/default/46.pwrmgr_disable_rom_integrity_check.4245186986
Short name T603
Test name
Test status
Simulation time 55151376 ps
CPU time 0.77 seconds
Started Jul 30 06:42:28 PM PDT 24
Finished Jul 30 06:42:29 PM PDT 24
Peak memory 198548 kb
Host smart-9ffe5eec-45e6-4a38-a377-316bd590c527
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245186986 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_dis
able_rom_integrity_check.4245186986
Directory /workspace/46.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/46.pwrmgr_esc_clk_rst_malfunc.837981076
Short name T385
Test name
Test status
Simulation time 36696068 ps
CPU time 0.6 seconds
Started Jul 30 06:42:34 PM PDT 24
Finished Jul 30 06:42:35 PM PDT 24
Peak memory 198016 kb
Host smart-8fafcd77-7fef-4785-af5f-7041d58dc1e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837981076 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_esc_clk_rst_
malfunc.837981076
Directory /workspace/46.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/46.pwrmgr_escalation_timeout.172457861
Short name T387
Test name
Test status
Simulation time 169690040 ps
CPU time 0.98 seconds
Started Jul 30 06:42:25 PM PDT 24
Finished Jul 30 06:42:26 PM PDT 24
Peak memory 198136 kb
Host smart-b8bf1e9b-b67f-48ea-8eb0-e928f6285a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172457861 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_escalation_timeout.172457861
Directory /workspace/46.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/46.pwrmgr_glitch.2183242407
Short name T522
Test name
Test status
Simulation time 41339854 ps
CPU time 0.7 seconds
Started Jul 30 06:42:27 PM PDT 24
Finished Jul 30 06:42:27 PM PDT 24
Peak memory 198128 kb
Host smart-51ee10a3-8dd1-4710-a981-f28eea6305bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183242407 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_glitch.2183242407
Directory /workspace/46.pwrmgr_glitch/latest

Test location /workspace/coverage/default/46.pwrmgr_global_esc.3851468233
Short name T505
Test name
Test status
Simulation time 29803264 ps
CPU time 0.66 seconds
Started Jul 30 06:42:31 PM PDT 24
Finished Jul 30 06:42:32 PM PDT 24
Peak memory 198492 kb
Host smart-ae90ace7-eb62-4396-803e-ddcfabcabd75
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851468233 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_global_esc.3851468233
Directory /workspace/46.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/46.pwrmgr_lowpower_invalid.1697229088
Short name T198
Test name
Test status
Simulation time 51728767 ps
CPU time 0.68 seconds
Started Jul 30 06:42:25 PM PDT 24
Finished Jul 30 06:42:26 PM PDT 24
Peak memory 201292 kb
Host smart-fada5173-e9ac-4627-a7a9-8a83899a03e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697229088 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_lowpower_inval
id.1697229088
Directory /workspace/46.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/46.pwrmgr_reset.3456051886
Short name T538
Test name
Test status
Simulation time 33429788 ps
CPU time 0.69 seconds
Started Jul 30 06:42:28 PM PDT 24
Finished Jul 30 06:42:29 PM PDT 24
Peak memory 199192 kb
Host smart-169ad948-a936-4746-baf0-93e329a6351b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456051886 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset.3456051886
Directory /workspace/46.pwrmgr_reset/latest

Test location /workspace/coverage/default/46.pwrmgr_reset_invalid.653169570
Short name T213
Test name
Test status
Simulation time 474348169 ps
CPU time 0.81 seconds
Started Jul 30 06:42:29 PM PDT 24
Finished Jul 30 06:42:30 PM PDT 24
Peak memory 209480 kb
Host smart-1ff3f24a-f433-4289-b624-faeda4202b56
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653169570 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset_invalid.653169570
Directory /workspace/46.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/46.pwrmgr_sec_cm_rstmgr_intersig_mubi.193770725
Short name T249
Test name
Test status
Simulation time 155883519 ps
CPU time 0.77 seconds
Started Jul 30 06:42:24 PM PDT 24
Finished Jul 30 06:42:24 PM PDT 24
Peak memory 198220 kb
Host smart-16312efd-00ed-4f75-b884-2ffa71a384e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193770725 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm_rstmgr_intersig_
mubi.193770725
Directory /workspace/46.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/46.pwrmgr_smoke.2651432899
Short name T66
Test name
Test status
Simulation time 33631558 ps
CPU time 0.66 seconds
Started Jul 30 06:42:21 PM PDT 24
Finished Jul 30 06:42:22 PM PDT 24
Peak memory 199356 kb
Host smart-cec7bd09-cd44-4bc2-9ecd-f5f16aca66b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651432899 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_smoke.2651432899
Directory /workspace/46.pwrmgr_smoke/latest

Test location /workspace/coverage/default/47.pwrmgr_aborted_low_power.41366386
Short name T433
Test name
Test status
Simulation time 115241280 ps
CPU time 0.83 seconds
Started Jul 30 06:42:19 PM PDT 24
Finished Jul 30 06:42:20 PM PDT 24
Peak memory 200100 kb
Host smart-78c95dd1-e50e-425d-b0be-581cca5f21f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41366386 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_aborted_low_power.41366386
Directory /workspace/47.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/47.pwrmgr_disable_rom_integrity_check.1945847834
Short name T340
Test name
Test status
Simulation time 70371330 ps
CPU time 0.68 seconds
Started Jul 30 06:42:31 PM PDT 24
Finished Jul 30 06:42:32 PM PDT 24
Peak memory 198472 kb
Host smart-bab3149b-c122-433f-b656-fcd0bb13cb8e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945847834 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_dis
able_rom_integrity_check.1945847834
Directory /workspace/47.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/47.pwrmgr_esc_clk_rst_malfunc.2648853685
Short name T465
Test name
Test status
Simulation time 39164074 ps
CPU time 0.61 seconds
Started Jul 30 06:42:30 PM PDT 24
Finished Jul 30 06:42:31 PM PDT 24
Peak memory 198080 kb
Host smart-60fbac75-0bd6-40e4-9dff-916604204c9e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648853685 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_esc_clk_rst
_malfunc.2648853685
Directory /workspace/47.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/47.pwrmgr_escalation_timeout.4234989415
Short name T335
Test name
Test status
Simulation time 165810599 ps
CPU time 0.99 seconds
Started Jul 30 06:42:36 PM PDT 24
Finished Jul 30 06:42:37 PM PDT 24
Peak memory 198140 kb
Host smart-7b58c5bd-13db-42ea-a260-d3fe615c6b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234989415 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_escalation_timeout.4234989415
Directory /workspace/47.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/47.pwrmgr_glitch.1211276688
Short name T609
Test name
Test status
Simulation time 50893193 ps
CPU time 0.58 seconds
Started Jul 30 06:42:28 PM PDT 24
Finished Jul 30 06:42:28 PM PDT 24
Peak memory 198120 kb
Host smart-094c8190-b2ab-498f-9ef5-2bfaeb1ee0d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211276688 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_glitch.1211276688
Directory /workspace/47.pwrmgr_glitch/latest

Test location /workspace/coverage/default/47.pwrmgr_global_esc.2341511779
Short name T436
Test name
Test status
Simulation time 40449519 ps
CPU time 0.57 seconds
Started Jul 30 06:42:37 PM PDT 24
Finished Jul 30 06:42:38 PM PDT 24
Peak memory 198412 kb
Host smart-7df5e2ff-9cc3-48c7-ab38-5d34c3642b06
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341511779 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_global_esc.2341511779
Directory /workspace/47.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/47.pwrmgr_lowpower_invalid.558206113
Short name T182
Test name
Test status
Simulation time 78882246 ps
CPU time 0.67 seconds
Started Jul 30 06:42:29 PM PDT 24
Finished Jul 30 06:42:29 PM PDT 24
Peak memory 201024 kb
Host smart-b53ed369-c932-40bd-a4a1-e5172dee4078
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558206113 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_lowpower_invali
d.558206113
Directory /workspace/47.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/47.pwrmgr_reset.1412088831
Short name T515
Test name
Test status
Simulation time 107130895 ps
CPU time 0.83 seconds
Started Jul 30 06:42:22 PM PDT 24
Finished Jul 30 06:42:23 PM PDT 24
Peak memory 198452 kb
Host smart-e53036d6-2294-41e3-9448-b376d2b6f2b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412088831 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset.1412088831
Directory /workspace/47.pwrmgr_reset/latest

Test location /workspace/coverage/default/47.pwrmgr_reset_invalid.3097536862
Short name T352
Test name
Test status
Simulation time 167425883 ps
CPU time 0.83 seconds
Started Jul 30 06:42:31 PM PDT 24
Finished Jul 30 06:42:32 PM PDT 24
Peak memory 209508 kb
Host smart-b450559a-1749-46ee-9113-3c4ca73c56f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097536862 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset_invalid.3097536862
Directory /workspace/47.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/47.pwrmgr_sec_cm_rstmgr_intersig_mubi.536907940
Short name T424
Test name
Test status
Simulation time 59153266 ps
CPU time 0.73 seconds
Started Jul 30 06:42:31 PM PDT 24
Finished Jul 30 06:42:32 PM PDT 24
Peak memory 198168 kb
Host smart-e4a5fc81-c2da-4f7d-88fd-42a2b5e19d19
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536907940 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm_rstmgr_intersig_
mubi.536907940
Directory /workspace/47.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/47.pwrmgr_smoke.108559109
Short name T452
Test name
Test status
Simulation time 31134581 ps
CPU time 0.68 seconds
Started Jul 30 06:42:30 PM PDT 24
Finished Jul 30 06:42:31 PM PDT 24
Peak memory 198588 kb
Host smart-dec66133-e386-4ae8-87da-1d0131a96839
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108559109 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_smoke.108559109
Directory /workspace/47.pwrmgr_smoke/latest

Test location /workspace/coverage/default/47.pwrmgr_stress_all.3293052547
Short name T588
Test name
Test status
Simulation time 240420165 ps
CPU time 1.02 seconds
Started Jul 30 06:42:28 PM PDT 24
Finished Jul 30 06:42:30 PM PDT 24
Peak memory 200828 kb
Host smart-71a0ffd2-373a-4aad-ab93-8ab1b26bf714
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293052547 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_stress_all.3293052547
Directory /workspace/47.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/48.pwrmgr_aborted_low_power.3268475731
Short name T585
Test name
Test status
Simulation time 26816070 ps
CPU time 0.91 seconds
Started Jul 30 06:42:29 PM PDT 24
Finished Jul 30 06:42:30 PM PDT 24
Peak memory 200720 kb
Host smart-0f314b06-5a09-4fb9-8132-963c1ac8916e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268475731 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_aborted_low_power.3268475731
Directory /workspace/48.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/48.pwrmgr_disable_rom_integrity_check.3430265878
Short name T499
Test name
Test status
Simulation time 53689750 ps
CPU time 0.79 seconds
Started Jul 30 06:42:23 PM PDT 24
Finished Jul 30 06:42:24 PM PDT 24
Peak memory 199224 kb
Host smart-94711379-7708-4528-99fe-93084a1daac2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430265878 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_dis
able_rom_integrity_check.3430265878
Directory /workspace/48.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/48.pwrmgr_esc_clk_rst_malfunc.28425445
Short name T413
Test name
Test status
Simulation time 29606079 ps
CPU time 0.66 seconds
Started Jul 30 06:42:24 PM PDT 24
Finished Jul 30 06:42:25 PM PDT 24
Peak memory 198088 kb
Host smart-c31a920d-15dd-4734-b02e-4196f9c4a395
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28425445 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_mal
func_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_esc_clk_rst_m
alfunc.28425445
Directory /workspace/48.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/48.pwrmgr_escalation_timeout.3440673175
Short name T295
Test name
Test status
Simulation time 160099700 ps
CPU time 0.93 seconds
Started Jul 30 06:42:24 PM PDT 24
Finished Jul 30 06:42:25 PM PDT 24
Peak memory 198096 kb
Host smart-d353f601-4d50-4b03-a3be-4631082c82a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440673175 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_escalation_timeout.3440673175
Directory /workspace/48.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/48.pwrmgr_glitch.3526116572
Short name T308
Test name
Test status
Simulation time 54452706 ps
CPU time 0.68 seconds
Started Jul 30 06:42:42 PM PDT 24
Finished Jul 30 06:42:43 PM PDT 24
Peak memory 197372 kb
Host smart-871503d4-2d20-4afd-a0bb-396a82cfd251
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526116572 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_glitch.3526116572
Directory /workspace/48.pwrmgr_glitch/latest

Test location /workspace/coverage/default/48.pwrmgr_global_esc.4210822665
Short name T625
Test name
Test status
Simulation time 42454330 ps
CPU time 0.67 seconds
Started Jul 30 06:42:28 PM PDT 24
Finished Jul 30 06:42:29 PM PDT 24
Peak memory 198164 kb
Host smart-dfd1a9f0-b000-4001-959b-7e4cd19aea71
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210822665 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_global_esc.4210822665
Directory /workspace/48.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/48.pwrmgr_lowpower_invalid.1744809385
Short name T171
Test name
Test status
Simulation time 47223782 ps
CPU time 0.71 seconds
Started Jul 30 06:42:28 PM PDT 24
Finished Jul 30 06:42:29 PM PDT 24
Peak memory 201432 kb
Host smart-2f8d01a3-f3c0-492d-8a4e-804381078cf1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744809385 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_lowpower_inval
id.1744809385
Directory /workspace/48.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/48.pwrmgr_lowpower_wakeup_race.2307931814
Short name T53
Test name
Test status
Simulation time 39527430 ps
CPU time 0.67 seconds
Started Jul 30 06:42:29 PM PDT 24
Finished Jul 30 06:42:30 PM PDT 24
Peak memory 198272 kb
Host smart-37e8ad55-ab2b-4ce4-831c-abc282699604
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307931814 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_lowpower_w
akeup_race.2307931814
Directory /workspace/48.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/48.pwrmgr_reset.3711798131
Short name T209
Test name
Test status
Simulation time 84018390 ps
CPU time 0.72 seconds
Started Jul 30 06:42:22 PM PDT 24
Finished Jul 30 06:42:23 PM PDT 24
Peak memory 198376 kb
Host smart-600bb2c2-d392-4376-ac85-91633bcd9323
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711798131 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset.3711798131
Directory /workspace/48.pwrmgr_reset/latest

Test location /workspace/coverage/default/48.pwrmgr_reset_invalid.438485908
Short name T537
Test name
Test status
Simulation time 167945758 ps
CPU time 0.79 seconds
Started Jul 30 06:42:32 PM PDT 24
Finished Jul 30 06:42:33 PM PDT 24
Peak memory 209612 kb
Host smart-9d212076-dbfd-494d-bda4-8e848aae48a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438485908 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset_invalid.438485908
Directory /workspace/48.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/48.pwrmgr_sec_cm_rstmgr_intersig_mubi.1696583264
Short name T298
Test name
Test status
Simulation time 65043527 ps
CPU time 0.86 seconds
Started Jul 30 06:42:35 PM PDT 24
Finished Jul 30 06:42:36 PM PDT 24
Peak memory 198416 kb
Host smart-b78de259-161c-4342-9a51-169af22e132f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696583264 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1696583264
Directory /workspace/48.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/48.pwrmgr_smoke.3488552874
Short name T380
Test name
Test status
Simulation time 68168583 ps
CPU time 0.62 seconds
Started Jul 30 06:42:26 PM PDT 24
Finished Jul 30 06:42:27 PM PDT 24
Peak memory 198540 kb
Host smart-4774dfe4-8704-454f-af0d-5fdbb64a115e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488552874 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_smoke.3488552874
Directory /workspace/48.pwrmgr_smoke/latest

Test location /workspace/coverage/default/49.pwrmgr_aborted_low_power.631911591
Short name T528
Test name
Test status
Simulation time 39761600 ps
CPU time 0.64 seconds
Started Jul 30 06:42:35 PM PDT 24
Finished Jul 30 06:42:36 PM PDT 24
Peak memory 198676 kb
Host smart-b13eed24-034a-4015-8f66-cf1fc805b4ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631911591 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_aborted_low_power.631911591
Directory /workspace/49.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/49.pwrmgr_disable_rom_integrity_check.1776093688
Short name T151
Test name
Test status
Simulation time 61449978 ps
CPU time 0.79 seconds
Started Jul 30 06:42:35 PM PDT 24
Finished Jul 30 06:42:36 PM PDT 24
Peak memory 199172 kb
Host smart-407b8061-a00b-4f33-9b27-b6d3cac77fc7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776093688 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_dis
able_rom_integrity_check.1776093688
Directory /workspace/49.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/49.pwrmgr_esc_clk_rst_malfunc.1369922794
Short name T265
Test name
Test status
Simulation time 31440605 ps
CPU time 0.6 seconds
Started Jul 30 06:42:33 PM PDT 24
Finished Jul 30 06:42:34 PM PDT 24
Peak memory 198016 kb
Host smart-4aa16331-aff2-487d-81a3-0b6cc1ba6d73
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369922794 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_esc_clk_rst
_malfunc.1369922794
Directory /workspace/49.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/49.pwrmgr_escalation_timeout.3262525186
Short name T91
Test name
Test status
Simulation time 167975802 ps
CPU time 0.97 seconds
Started Jul 30 06:42:38 PM PDT 24
Finished Jul 30 06:42:39 PM PDT 24
Peak memory 198120 kb
Host smart-85ca2120-2e81-4c88-bbab-b4b1d9f99bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262525186 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_escalation_timeout.3262525186
Directory /workspace/49.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/49.pwrmgr_glitch.3136565805
Short name T300
Test name
Test status
Simulation time 58290944 ps
CPU time 0.65 seconds
Started Jul 30 06:42:36 PM PDT 24
Finished Jul 30 06:42:37 PM PDT 24
Peak memory 197416 kb
Host smart-46673947-1ea5-48ab-bf3f-3ce0d2eadd79
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136565805 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_glitch.3136565805
Directory /workspace/49.pwrmgr_glitch/latest

Test location /workspace/coverage/default/49.pwrmgr_global_esc.713634742
Short name T432
Test name
Test status
Simulation time 37025089 ps
CPU time 0.67 seconds
Started Jul 30 06:42:29 PM PDT 24
Finished Jul 30 06:42:30 PM PDT 24
Peak memory 198428 kb
Host smart-1b20a553-25ce-45cb-9c6a-7ff2267d28cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713634742 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_global_esc.713634742
Directory /workspace/49.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/49.pwrmgr_lowpower_invalid.834210348
Short name T173
Test name
Test status
Simulation time 80178081 ps
CPU time 0.67 seconds
Started Jul 30 06:42:35 PM PDT 24
Finished Jul 30 06:42:36 PM PDT 24
Peak memory 201400 kb
Host smart-1fb379ea-dd52-4da9-9912-4692c36876a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834210348 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_lowpower_invali
d.834210348
Directory /workspace/49.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/49.pwrmgr_reset.2649166874
Short name T288
Test name
Test status
Simulation time 67113606 ps
CPU time 0.66 seconds
Started Jul 30 06:42:30 PM PDT 24
Finished Jul 30 06:42:30 PM PDT 24
Peak memory 198332 kb
Host smart-81b15e2d-e644-48e0-911d-ac642de1dd62
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649166874 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset.2649166874
Directory /workspace/49.pwrmgr_reset/latest

Test location /workspace/coverage/default/49.pwrmgr_reset_invalid.4201855551
Short name T38
Test name
Test status
Simulation time 108840144 ps
CPU time 0.98 seconds
Started Jul 30 06:42:29 PM PDT 24
Finished Jul 30 06:42:30 PM PDT 24
Peak memory 209612 kb
Host smart-664a3eb5-53d6-4e80-917a-93063361242e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201855551 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset_invalid.4201855551
Directory /workspace/49.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/49.pwrmgr_sec_cm_rstmgr_intersig_mubi.1671921772
Short name T480
Test name
Test status
Simulation time 93527753 ps
CPU time 0.72 seconds
Started Jul 30 06:42:32 PM PDT 24
Finished Jul 30 06:42:33 PM PDT 24
Peak memory 199596 kb
Host smart-59468140-177a-426a-9642-fdc646a4c1cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671921772 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1671921772
Directory /workspace/49.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/49.pwrmgr_smoke.2876682586
Short name T278
Test name
Test status
Simulation time 27687767 ps
CPU time 0.73 seconds
Started Jul 30 06:42:28 PM PDT 24
Finished Jul 30 06:42:29 PM PDT 24
Peak memory 199436 kb
Host smart-e949388e-d0a2-4cff-b8ae-c9d576ddd5cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876682586 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_smoke.2876682586
Directory /workspace/49.pwrmgr_smoke/latest

Test location /workspace/coverage/default/5.pwrmgr_aborted_low_power.1304124891
Short name T348
Test name
Test status
Simulation time 42333679 ps
CPU time 0.83 seconds
Started Jul 30 06:40:34 PM PDT 24
Finished Jul 30 06:40:35 PM PDT 24
Peak memory 198828 kb
Host smart-dd316ec3-e99a-4c8f-b657-d187c5a7d524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304124891 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_aborted_low_power.1304124891
Directory /workspace/5.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/5.pwrmgr_disable_rom_integrity_check.787433599
Short name T154
Test name
Test status
Simulation time 59232474 ps
CPU time 0.84 seconds
Started Jul 30 06:40:41 PM PDT 24
Finished Jul 30 06:40:42 PM PDT 24
Peak memory 198520 kb
Host smart-72fe89f8-3695-47af-abc1-ad03936c5a1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787433599 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_disab
le_rom_integrity_check.787433599
Directory /workspace/5.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/5.pwrmgr_esc_clk_rst_malfunc.1417761236
Short name T445
Test name
Test status
Simulation time 32519366 ps
CPU time 0.61 seconds
Started Jul 30 06:40:31 PM PDT 24
Finished Jul 30 06:40:32 PM PDT 24
Peak memory 197352 kb
Host smart-21cc6cc0-70ab-4465-a7ec-2b6261e4fe34
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417761236 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_esc_clk_rst_
malfunc.1417761236
Directory /workspace/5.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/5.pwrmgr_escalation_timeout.188579157
Short name T414
Test name
Test status
Simulation time 160985372 ps
CPU time 0.99 seconds
Started Jul 30 06:40:40 PM PDT 24
Finished Jul 30 06:40:41 PM PDT 24
Peak memory 198400 kb
Host smart-6d089076-2eed-4bf1-89c8-91879cce5c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188579157 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_escalation_timeout.188579157
Directory /workspace/5.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/5.pwrmgr_glitch.4265262131
Short name T454
Test name
Test status
Simulation time 58138729 ps
CPU time 0.64 seconds
Started Jul 30 06:40:33 PM PDT 24
Finished Jul 30 06:40:33 PM PDT 24
Peak memory 198108 kb
Host smart-adabcd24-ba60-49c4-bfca-fe94024e19d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265262131 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_glitch.4265262131
Directory /workspace/5.pwrmgr_glitch/latest

Test location /workspace/coverage/default/5.pwrmgr_global_esc.1739629526
Short name T217
Test name
Test status
Simulation time 51173358 ps
CPU time 0.58 seconds
Started Jul 30 06:40:34 PM PDT 24
Finished Jul 30 06:40:34 PM PDT 24
Peak memory 198108 kb
Host smart-cda75c3f-0fff-4174-8ffe-d803bd1315aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739629526 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_global_esc.1739629526
Directory /workspace/5.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/5.pwrmgr_lowpower_invalid.1384250036
Short name T409
Test name
Test status
Simulation time 82137855 ps
CPU time 0.71 seconds
Started Jul 30 06:40:41 PM PDT 24
Finished Jul 30 06:40:42 PM PDT 24
Peak memory 201192 kb
Host smart-1d748ac9-d6da-49c7-93d5-2e773a86f40c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384250036 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_lowpower_invali
d.1384250036
Directory /workspace/5.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/5.pwrmgr_reset.3019235038
Short name T476
Test name
Test status
Simulation time 114938315 ps
CPU time 0.69 seconds
Started Jul 30 06:40:40 PM PDT 24
Finished Jul 30 06:40:41 PM PDT 24
Peak memory 198316 kb
Host smart-73a9d5fb-d60d-4e24-9930-aa1d73996e76
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019235038 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset.3019235038
Directory /workspace/5.pwrmgr_reset/latest

Test location /workspace/coverage/default/5.pwrmgr_reset_invalid.860716463
Short name T234
Test name
Test status
Simulation time 175190559 ps
CPU time 0.79 seconds
Started Jul 30 06:40:31 PM PDT 24
Finished Jul 30 06:40:32 PM PDT 24
Peak memory 209524 kb
Host smart-2887888e-8bf1-4a13-82d4-a859beefacb4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860716463 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset_invalid.860716463
Directory /workspace/5.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/5.pwrmgr_sec_cm_rstmgr_intersig_mubi.917657545
Short name T254
Test name
Test status
Simulation time 57984327 ps
CPU time 0.78 seconds
Started Jul 30 06:40:31 PM PDT 24
Finished Jul 30 06:40:32 PM PDT 24
Peak memory 198072 kb
Host smart-b67ec6b3-cb50-4181-a139-59770440c9c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917657545 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.917657545
Directory /workspace/5.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/5.pwrmgr_smoke.125680482
Short name T416
Test name
Test status
Simulation time 42114620 ps
CPU time 0.63 seconds
Started Jul 30 06:40:31 PM PDT 24
Finished Jul 30 06:40:32 PM PDT 24
Peak memory 198520 kb
Host smart-01229c50-8aaf-4052-9b29-df42b8008037
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125680482 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_smoke.125680482
Directory /workspace/5.pwrmgr_smoke/latest

Test location /workspace/coverage/default/6.pwrmgr_aborted_low_power.3822401505
Short name T593
Test name
Test status
Simulation time 41694800 ps
CPU time 0.92 seconds
Started Jul 30 06:40:32 PM PDT 24
Finished Jul 30 06:40:33 PM PDT 24
Peak memory 200188 kb
Host smart-b5387c1c-4ea2-46f4-822c-a6c44628867d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822401505 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_aborted_low_power.3822401505
Directory /workspace/6.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/6.pwrmgr_disable_rom_integrity_check.1988817527
Short name T165
Test name
Test status
Simulation time 63747568 ps
CPU time 0.63 seconds
Started Jul 30 06:40:36 PM PDT 24
Finished Jul 30 06:40:36 PM PDT 24
Peak memory 198252 kb
Host smart-8144a23f-e8ed-4e6d-8490-1895a75eef78
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988817527 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_disa
ble_rom_integrity_check.1988817527
Directory /workspace/6.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/6.pwrmgr_esc_clk_rst_malfunc.1641339021
Short name T548
Test name
Test status
Simulation time 28415933 ps
CPU time 0.66 seconds
Started Jul 30 06:40:37 PM PDT 24
Finished Jul 30 06:40:38 PM PDT 24
Peak memory 198004 kb
Host smart-7c029637-2e61-49ea-b330-ef19714b6396
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641339021 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_esc_clk_rst_
malfunc.1641339021
Directory /workspace/6.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/6.pwrmgr_escalation_timeout.404888295
Short name T565
Test name
Test status
Simulation time 157896073 ps
CPU time 0.95 seconds
Started Jul 30 06:40:39 PM PDT 24
Finished Jul 30 06:40:40 PM PDT 24
Peak memory 198132 kb
Host smart-65afa8e9-3e34-4bf5-a232-5f6a5dd06e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404888295 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_escalation_timeout.404888295
Directory /workspace/6.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/6.pwrmgr_glitch.2451191902
Short name T582
Test name
Test status
Simulation time 38820484 ps
CPU time 0.61 seconds
Started Jul 30 06:40:39 PM PDT 24
Finished Jul 30 06:40:40 PM PDT 24
Peak memory 197980 kb
Host smart-99a8b1c0-47af-4c61-a5b7-d3b2ad28ba85
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451191902 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_glitch.2451191902
Directory /workspace/6.pwrmgr_glitch/latest

Test location /workspace/coverage/default/6.pwrmgr_global_esc.2187071884
Short name T332
Test name
Test status
Simulation time 97491752 ps
CPU time 0.65 seconds
Started Jul 30 06:40:39 PM PDT 24
Finished Jul 30 06:40:39 PM PDT 24
Peak memory 198416 kb
Host smart-30c507b1-2209-4e6c-b50a-addfd13cbf13
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187071884 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_global_esc.2187071884
Directory /workspace/6.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/6.pwrmgr_lowpower_invalid.2584006410
Short name T10
Test name
Test status
Simulation time 57019505 ps
CPU time 0.75 seconds
Started Jul 30 06:40:40 PM PDT 24
Finished Jul 30 06:40:41 PM PDT 24
Peak memory 201408 kb
Host smart-6c73d57d-29bb-445f-a5e4-e99858482152
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584006410 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_lowpower_invali
d.2584006410
Directory /workspace/6.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/6.pwrmgr_lowpower_wakeup_race.3385232500
Short name T141
Test name
Test status
Simulation time 31830571 ps
CPU time 0.66 seconds
Started Jul 30 06:40:33 PM PDT 24
Finished Jul 30 06:40:34 PM PDT 24
Peak memory 198244 kb
Host smart-fa453de3-73ce-461e-b79a-270b18b54d35
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385232500 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_lowpower_wa
keup_race.3385232500
Directory /workspace/6.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/6.pwrmgr_reset.588657266
Short name T542
Test name
Test status
Simulation time 57935597 ps
CPU time 0.62 seconds
Started Jul 30 06:40:32 PM PDT 24
Finished Jul 30 06:40:33 PM PDT 24
Peak memory 198376 kb
Host smart-c6240d23-0f91-4987-b0a1-920aa9c0a823
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588657266 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset.588657266
Directory /workspace/6.pwrmgr_reset/latest

Test location /workspace/coverage/default/6.pwrmgr_reset_invalid.1621423567
Short name T261
Test name
Test status
Simulation time 113807332 ps
CPU time 0.89 seconds
Started Jul 30 06:40:38 PM PDT 24
Finished Jul 30 06:40:39 PM PDT 24
Peak memory 209556 kb
Host smart-77a6bb1a-9c3b-4290-9e17-6f759a3eaa23
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621423567 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset_invalid.1621423567
Directory /workspace/6.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/6.pwrmgr_sec_cm_rstmgr_intersig_mubi.4075761542
Short name T449
Test name
Test status
Simulation time 50111275 ps
CPU time 0.86 seconds
Started Jul 30 06:40:37 PM PDT 24
Finished Jul 30 06:40:38 PM PDT 24
Peak memory 199636 kb
Host smart-119dae14-03c7-48f4-89a5-392c890b7ab3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075761542 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_rstmgr_intersig_
mubi.4075761542
Directory /workspace/6.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/6.pwrmgr_smoke.1778225078
Short name T607
Test name
Test status
Simulation time 139609789 ps
CPU time 0.61 seconds
Started Jul 30 06:40:38 PM PDT 24
Finished Jul 30 06:40:39 PM PDT 24
Peak memory 198528 kb
Host smart-be7623b9-b499-4083-a0be-348e612a1fc8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778225078 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_smoke.1778225078
Directory /workspace/6.pwrmgr_smoke/latest

Test location /workspace/coverage/default/7.pwrmgr_aborted_low_power.3907201322
Short name T97
Test name
Test status
Simulation time 79042943 ps
CPU time 0.86 seconds
Started Jul 30 06:40:42 PM PDT 24
Finished Jul 30 06:40:43 PM PDT 24
Peak memory 200188 kb
Host smart-f42cda6b-d9da-44d4-93b4-d68e7bf86e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907201322 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_aborted_low_power.3907201322
Directory /workspace/7.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/7.pwrmgr_disable_rom_integrity_check.818944477
Short name T293
Test name
Test status
Simulation time 45241102 ps
CPU time 0.77 seconds
Started Jul 30 06:40:41 PM PDT 24
Finished Jul 30 06:40:42 PM PDT 24
Peak memory 198572 kb
Host smart-31603c56-9eea-4a01-befc-6371ea43651c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818944477 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_disab
le_rom_integrity_check.818944477
Directory /workspace/7.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.4144152029
Short name T339
Test name
Test status
Simulation time 30862282 ps
CPU time 0.66 seconds
Started Jul 30 06:40:43 PM PDT 24
Finished Jul 30 06:40:43 PM PDT 24
Peak memory 198120 kb
Host smart-086a2a9c-2969-46cd-bc4f-8cabcb51c336
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144152029 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_esc_clk_rst_
malfunc.4144152029
Directory /workspace/7.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/7.pwrmgr_escalation_timeout.357164680
Short name T304
Test name
Test status
Simulation time 661338846 ps
CPU time 0.98 seconds
Started Jul 30 06:40:41 PM PDT 24
Finished Jul 30 06:40:42 PM PDT 24
Peak memory 198060 kb
Host smart-30627aea-cef5-4387-901e-a6afc8c040e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357164680 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_escalation_timeout.357164680
Directory /workspace/7.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/7.pwrmgr_glitch.3753752708
Short name T479
Test name
Test status
Simulation time 58898612 ps
CPU time 0.73 seconds
Started Jul 30 06:40:41 PM PDT 24
Finished Jul 30 06:40:42 PM PDT 24
Peak memory 198112 kb
Host smart-e03769b6-81b6-4f5e-a124-06801ad3aab7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753752708 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_glitch.3753752708
Directory /workspace/7.pwrmgr_glitch/latest

Test location /workspace/coverage/default/7.pwrmgr_global_esc.1163829785
Short name T384
Test name
Test status
Simulation time 94422172 ps
CPU time 0.62 seconds
Started Jul 30 06:40:41 PM PDT 24
Finished Jul 30 06:40:42 PM PDT 24
Peak memory 198460 kb
Host smart-1e3b27b5-1857-42d8-9340-16352d5273b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163829785 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_global_esc.1163829785
Directory /workspace/7.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/7.pwrmgr_lowpower_invalid.3312170877
Short name T6
Test name
Test status
Simulation time 48974185 ps
CPU time 0.68 seconds
Started Jul 30 06:40:42 PM PDT 24
Finished Jul 30 06:40:43 PM PDT 24
Peak memory 201360 kb
Host smart-429ac73a-76c1-4cbf-8c14-cbdf788937c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312170877 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_lowpower_invali
d.3312170877
Directory /workspace/7.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/7.pwrmgr_reset.684856404
Short name T215
Test name
Test status
Simulation time 127626093 ps
CPU time 0.65 seconds
Started Jul 30 06:40:39 PM PDT 24
Finished Jul 30 06:40:39 PM PDT 24
Peak memory 199220 kb
Host smart-aed5925f-e268-4f19-bac3-d9ddab60458a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684856404 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset.684856404
Directory /workspace/7.pwrmgr_reset/latest

Test location /workspace/coverage/default/7.pwrmgr_reset_invalid.124321088
Short name T558
Test name
Test status
Simulation time 146768926 ps
CPU time 0.84 seconds
Started Jul 30 06:40:42 PM PDT 24
Finished Jul 30 06:40:43 PM PDT 24
Peak memory 209512 kb
Host smart-404a8cca-c7f2-4065-b895-937af4c4670c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124321088 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset_invalid.124321088
Directory /workspace/7.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.3280573195
Short name T81
Test name
Test status
Simulation time 60802781 ps
CPU time 0.8 seconds
Started Jul 30 06:40:43 PM PDT 24
Finished Jul 30 06:40:44 PM PDT 24
Peak memory 198256 kb
Host smart-81c0bc99-84ce-4368-8c32-0f9e8db88f04
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280573195 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_rstmgr_intersig_
mubi.3280573195
Directory /workspace/7.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/7.pwrmgr_smoke.3594528517
Short name T264
Test name
Test status
Simulation time 54860463 ps
CPU time 0.68 seconds
Started Jul 30 06:40:36 PM PDT 24
Finished Jul 30 06:40:37 PM PDT 24
Peak memory 198556 kb
Host smart-3763f120-2e16-4d2e-98b2-97e327508bff
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594528517 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_smoke.3594528517
Directory /workspace/7.pwrmgr_smoke/latest

Test location /workspace/coverage/default/8.pwrmgr_aborted_low_power.3328279252
Short name T456
Test name
Test status
Simulation time 32198350 ps
CPU time 0.63 seconds
Started Jul 30 06:40:45 PM PDT 24
Finished Jul 30 06:40:45 PM PDT 24
Peak memory 198592 kb
Host smart-a8d13f73-7809-4603-b651-f550cc039e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328279252 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_aborted_low_power.3328279252
Directory /workspace/8.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/8.pwrmgr_disable_rom_integrity_check.3456940994
Short name T309
Test name
Test status
Simulation time 71365231 ps
CPU time 0.66 seconds
Started Jul 30 06:40:46 PM PDT 24
Finished Jul 30 06:40:47 PM PDT 24
Peak memory 198304 kb
Host smart-b3a4a75f-2e78-445a-a637-6e4f9b6524ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456940994 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_disa
ble_rom_integrity_check.3456940994
Directory /workspace/8.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.2328710422
Short name T628
Test name
Test status
Simulation time 33139458 ps
CPU time 0.66 seconds
Started Jul 30 06:40:47 PM PDT 24
Finished Jul 30 06:40:48 PM PDT 24
Peak memory 197376 kb
Host smart-9632b72a-92c5-44ef-a39b-54e54ebc89ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328710422 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_esc_clk_rst_
malfunc.2328710422
Directory /workspace/8.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/8.pwrmgr_escalation_timeout.2575471071
Short name T8
Test name
Test status
Simulation time 163623649 ps
CPU time 0.99 seconds
Started Jul 30 06:40:43 PM PDT 24
Finished Jul 30 06:40:44 PM PDT 24
Peak memory 198148 kb
Host smart-f0e6cec4-7e00-47ec-8bbf-bb01204c8fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575471071 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_escalation_timeout.2575471071
Directory /workspace/8.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/8.pwrmgr_glitch.2975588507
Short name T223
Test name
Test status
Simulation time 49754493 ps
CPU time 0.71 seconds
Started Jul 30 06:40:44 PM PDT 24
Finished Jul 30 06:40:45 PM PDT 24
Peak memory 197448 kb
Host smart-b3939328-813a-445b-993d-7be05ac7e8e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975588507 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_glitch.2975588507
Directory /workspace/8.pwrmgr_glitch/latest

Test location /workspace/coverage/default/8.pwrmgr_global_esc.4082286008
Short name T243
Test name
Test status
Simulation time 56425472 ps
CPU time 0.63 seconds
Started Jul 30 06:40:42 PM PDT 24
Finished Jul 30 06:40:43 PM PDT 24
Peak memory 198088 kb
Host smart-e9384984-cf10-44ca-a11f-059e070bbbee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082286008 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_global_esc.4082286008
Directory /workspace/8.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/8.pwrmgr_reset.399210391
Short name T535
Test name
Test status
Simulation time 151808874 ps
CPU time 0.73 seconds
Started Jul 30 06:40:42 PM PDT 24
Finished Jul 30 06:40:43 PM PDT 24
Peak memory 198312 kb
Host smart-8b28e4ac-8e8c-455c-be41-37b39083da57
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399210391 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset.399210391
Directory /workspace/8.pwrmgr_reset/latest

Test location /workspace/coverage/default/8.pwrmgr_reset_invalid.2056084083
Short name T526
Test name
Test status
Simulation time 115719184 ps
CPU time 0.83 seconds
Started Jul 30 06:40:43 PM PDT 24
Finished Jul 30 06:40:44 PM PDT 24
Peak memory 209508 kb
Host smart-f1295f21-f490-486f-bfd3-04feb538406e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056084083 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset_invalid.2056084083
Directory /workspace/8.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.1200786141
Short name T292
Test name
Test status
Simulation time 120324793 ps
CPU time 0.76 seconds
Started Jul 30 06:40:46 PM PDT 24
Finished Jul 30 06:40:46 PM PDT 24
Peak memory 198140 kb
Host smart-b3b3f617-6134-43dc-bb98-71b67fcf1cbf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200786141 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_rstmgr_intersig_
mubi.1200786141
Directory /workspace/8.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/8.pwrmgr_smoke.4040738297
Short name T596
Test name
Test status
Simulation time 46321708 ps
CPU time 0.75 seconds
Started Jul 30 06:40:47 PM PDT 24
Finished Jul 30 06:40:48 PM PDT 24
Peak memory 199424 kb
Host smart-8fca0626-42f8-49c2-844d-fe5964bed3cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040738297 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_smoke.4040738297
Directory /workspace/8.pwrmgr_smoke/latest

Test location /workspace/coverage/default/9.pwrmgr_aborted_low_power.2739476803
Short name T552
Test name
Test status
Simulation time 27608289 ps
CPU time 0.76 seconds
Started Jul 30 06:40:49 PM PDT 24
Finished Jul 30 06:40:50 PM PDT 24
Peak memory 200064 kb
Host smart-5e9e56b1-442e-44e4-ac8b-8ddfa156372e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739476803 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_aborted_low_power.2739476803
Directory /workspace/9.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/9.pwrmgr_disable_rom_integrity_check.3369925827
Short name T408
Test name
Test status
Simulation time 74631099 ps
CPU time 0.63 seconds
Started Jul 30 06:40:53 PM PDT 24
Finished Jul 30 06:40:53 PM PDT 24
Peak memory 198216 kb
Host smart-8a0ea834-f65a-41dc-8554-96fd161305f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369925827 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_disa
ble_rom_integrity_check.3369925827
Directory /workspace/9.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.2543987610
Short name T381
Test name
Test status
Simulation time 31313234 ps
CPU time 0.61 seconds
Started Jul 30 06:40:49 PM PDT 24
Finished Jul 30 06:40:50 PM PDT 24
Peak memory 197304 kb
Host smart-ae5f3b4a-7110-4ad7-9318-b3f4c125fb06
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543987610 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_esc_clk_rst_
malfunc.2543987610
Directory /workspace/9.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/9.pwrmgr_escalation_timeout.3176369133
Short name T566
Test name
Test status
Simulation time 164740851 ps
CPU time 1 seconds
Started Jul 30 06:40:53 PM PDT 24
Finished Jul 30 06:40:54 PM PDT 24
Peak memory 198420 kb
Host smart-505caf94-5a6e-4730-9db3-50a804516079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176369133 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_escalation_timeout.3176369133
Directory /workspace/9.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/9.pwrmgr_glitch.1477145690
Short name T562
Test name
Test status
Simulation time 39746862 ps
CPU time 0.67 seconds
Started Jul 30 06:40:59 PM PDT 24
Finished Jul 30 06:41:00 PM PDT 24
Peak memory 198060 kb
Host smart-51b5d740-b825-4ad7-a941-c3eaf367256b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477145690 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_glitch.1477145690
Directory /workspace/9.pwrmgr_glitch/latest

Test location /workspace/coverage/default/9.pwrmgr_global_esc.3096834129
Short name T425
Test name
Test status
Simulation time 23672712 ps
CPU time 0.65 seconds
Started Jul 30 06:40:49 PM PDT 24
Finished Jul 30 06:40:50 PM PDT 24
Peak memory 198160 kb
Host smart-cbbccff0-060f-4553-adb8-c5d9e1722560
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096834129 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_global_esc.3096834129
Directory /workspace/9.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/9.pwrmgr_lowpower_invalid.873481154
Short name T575
Test name
Test status
Simulation time 42220927 ps
CPU time 0.72 seconds
Started Jul 30 06:40:51 PM PDT 24
Finished Jul 30 06:40:52 PM PDT 24
Peak memory 201468 kb
Host smart-f7deefff-cffc-49db-bf52-4b1f7003fd8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873481154 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_lowpower_invalid
.873481154
Directory /workspace/9.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/9.pwrmgr_reset.2479702162
Short name T451
Test name
Test status
Simulation time 71105528 ps
CPU time 0.75 seconds
Started Jul 30 06:40:47 PM PDT 24
Finished Jul 30 06:40:48 PM PDT 24
Peak memory 198332 kb
Host smart-3358b144-159a-4047-b49a-13f7d37238c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479702162 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset.2479702162
Directory /workspace/9.pwrmgr_reset/latest

Test location /workspace/coverage/default/9.pwrmgr_reset_invalid.3171075805
Short name T258
Test name
Test status
Simulation time 95745308 ps
CPU time 1.07 seconds
Started Jul 30 06:40:51 PM PDT 24
Finished Jul 30 06:40:52 PM PDT 24
Peak memory 209480 kb
Host smart-391f524f-8d59-423d-b2f5-12a4ae730364
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171075805 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset_invalid.3171075805
Directory /workspace/9.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.192777132
Short name T494
Test name
Test status
Simulation time 101470934 ps
CPU time 0.74 seconds
Started Jul 30 06:40:51 PM PDT 24
Finished Jul 30 06:40:52 PM PDT 24
Peak memory 198148 kb
Host smart-52d97e05-99fc-453f-bc2e-b03406b0b85f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192777132 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.192777132
Directory /workspace/9.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/9.pwrmgr_smoke.870288287
Short name T496
Test name
Test status
Simulation time 29996584 ps
CPU time 0.67 seconds
Started Jul 30 06:40:44 PM PDT 24
Finished Jul 30 06:40:45 PM PDT 24
Peak memory 198540 kb
Host smart-07647f58-9a04-49b6-a3bc-13ce0c304daf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870288287 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_smoke.870288287
Directory /workspace/9.pwrmgr_smoke/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%