Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	38725	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

29196

1

T1

1

T2

12

T3

78

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	34756	1			T1	1		T2	5		T3	137
values[0x0]	16321	1			T2	14		T3	17		T4	6
values[0x1]	16844	1			T2	8		T3	16		T4	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	31186	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

36735

1

T1

1

T2

13

T3

95

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	239	1			T3	2		T77	4		T210	1
valid_sources[0x01]	259	1			T63	3		T13	3		T211	1
valid_sources[0x02]	268	1			T3	2		T77	2		T63	4
valid_sources[0x03]	202	1			T2	1		T3	3		T77	2
valid_sources[0x04]	251	1			T3	2		T77	1		T212	2
valid_sources[0x05]	217	1			T3	1		T76	3		T210	1
valid_sources[0x06]	223	1			T26	3		T77	1		T13	1
valid_sources[0x07]	203	1			T11	2		T77	1		T80	2
valid_sources[0x08]	284	1			T26	2		T13	3		T98	1
valid_sources[0x09]	179	1			T3	1		T11	2		T63	2
valid_sources[0x0a]	174	1			T3	2		T77	1		T37	1
valid_sources[0x0b]	269	1			T3	2		T77	1		T213	3
valid_sources[0x0c]	236	1			T4	1		T11	5		T27	1
valid_sources[0x0d]	275	1			T11	7		T37	1		T13	2
valid_sources[0x0e]	271	1			T37	1		T214	1		T215	1
valid_sources[0x0f]	355	1			T11	1		T77	1		T13	4
valid_sources[0x10]	242	1			T16	1		T77	2		T37	1
valid_sources[0x11]	234	1			T37	2		T13	1		T216	13
valid_sources[0x12]	341	1			T11	2		T54	2		T77	1
valid_sources[0x13]	346	1			T3	1		T14	1		T77	3
valid_sources[0x14]	246	1			T2	1		T77	1		T63	1
valid_sources[0x15]	192	1			T3	1		T34	30		T63	2
valid_sources[0x16]	321	1			T11	3		T77	1		T37	1
valid_sources[0x17]	339	1			T27	1		T37	1		T210	4
valid_sources[0x18]	161	1			T3	1		T76	1		T32	1
valid_sources[0x19]	291	1			T3	1		T77	1		T37	1
valid_sources[0x1a]	195	1			T3	1		T76	1		T77	2
valid_sources[0x1b]	215	1			T3	2		T11	4		T77	4
valid_sources[0x1c]	194	1			T4	3		T11	4		T210	1
valid_sources[0x1d]	264	1			T2	1		T3	2		T11	2
valid_sources[0x1e]	193	1			T3	1		T13	1		T144	2
valid_sources[0x1f]	463	1			T11	1		T77	3		T63	2
valid_sources[0x20]	251	1			T3	1		T26	1		T37	1
valid_sources[0x21]	267	1			T3	1		T10	1		T77	1
valid_sources[0x22]	311	1			T3	2		T77	2		T37	2
valid_sources[0x23]	358	1			T3	3		T11	5		T13	1
valid_sources[0x24]	192	1			T4	5		T37	1		T52	1
valid_sources[0x25]	352	1			T3	3		T26	5		T77	2
valid_sources[0x26]	375	1			T23	31		T77	1		T37	2
valid_sources[0x27]	273	1			T11	3		T77	1		T13	3
valid_sources[0x28]	256	1			T3	1		T11	1		T76	4
valid_sources[0x29]	294	1			T77	2		T211	1		T214	1
valid_sources[0x2a]	238	1			T77	1		T13	5		T210	1
valid_sources[0x2b]	243	1			T3	1		T77	2		T37	2
valid_sources[0x2c]	233	1			T3	1		T11	1		T12	14
valid_sources[0x2d]	195	1			T54	2		T63	2		T211	1
valid_sources[0x2e]	229	1			T77	1		T37	1		T13	6
valid_sources[0x2f]	233	1			T3	1		T63	2		T211	1
valid_sources[0x30]	291	1			T3	1		T63	4		T13	2
valid_sources[0x31]	292	1			T77	1		T63	2		T211	1
valid_sources[0x32]	193	1			T77	2		T37	1		T63	2
valid_sources[0x33]	313	1			T3	1		T77	1		T63	2
valid_sources[0x34]	469	1			T3	1		T76	1		T63	1
valid_sources[0x35]	268	1			T3	3		T4	2		T27	1
valid_sources[0x36]	260	1			T77	1		T37	2		T63	2
valid_sources[0x37]	268	1			T3	1		T210	3		T128	2
valid_sources[0x38]	232	1			T11	2		T27	1		T13	2
valid_sources[0x39]	325	1			T3	1		T11	5		T211	2
valid_sources[0x3a]	265	1			T16	1		T77	1		T211	2
valid_sources[0x3b]	309	1			T77	2		T37	1		T211	1
valid_sources[0x3c]	276	1			T3	1		T77	3		T210	1
valid_sources[0x3d]	277	1			T3	1		T163	1		T86	5
valid_sources[0x3e]	401	1			T3	1		T27	1		T63	1
valid_sources[0x3f]	349	1			T26	2		T139	1		T13	1
valid_sources[0x40]	351	1			T3	3		T77	1		T211	2
valid_sources[0x41]	217	1			T3	1		T77	3		T37	1
valid_sources[0x42]	481	1			T30	1		T77	3		T37	1
valid_sources[0x43]	194	1			T11	5		T77	3		T215	1
valid_sources[0x44]	180	1			T37	3		T38	1		T41	1
valid_sources[0x45]	273	1			T11	2		T37	1		T63	1
valid_sources[0x46]	256	1			T76	1		T54	1		T63	6
valid_sources[0x47]	381	1			T3	2		T76	3		T12	14
valid_sources[0x48]	281	1			T3	1		T76	3		T35	7
valid_sources[0x49]	224	1			T3	4		T210	2		T211	2
valid_sources[0x4a]	193	1			T4	10		T76	2		T26	6
valid_sources[0x4b]	185	1			T3	2		T77	2		T63	6
valid_sources[0x4c]	335	1			T16	2		T13	2		T210	1
valid_sources[0x4d]	383	1			T76	1		T211	1		T98	1
valid_sources[0x4e]	246	1			T77	1		T217	13		T214	1
valid_sources[0x4f]	227	1			T3	1		T54	1		T77	1
valid_sources[0x50]	264	1			T3	2		T27	1		T77	1
valid_sources[0x51]	214	1			T77	1		T13	1		T53	3
valid_sources[0x52]	185	1			T3	2		T77	1		T13	4
valid_sources[0x53]	313	1			T76	1		T211	1		T52	2
valid_sources[0x54]	242	1			T3	3		T76	13		T77	1
valid_sources[0x55]	241	1			T213	6		T215	1		T52	1
valid_sources[0x56]	368	1			T37	1		T13	3		T128	16
valid_sources[0x57]	201	1			T63	3		T13	1		T165	1
valid_sources[0x58]	385	1			T216	9		T93	3		T98	2
valid_sources[0x59]	268	1			T77	1		T63	1		T211	1
valid_sources[0x5a]	308	1			T77	1		T210	2		T211	2
valid_sources[0x5b]	273	1			T26	3		T27	1		T77	5
valid_sources[0x5c]	250	1			T3	2		T12	14		T13	3
valid_sources[0x5d]	220	1			T3	2		T37	1		T41	2
valid_sources[0x5e]	379	1			T3	1		T77	1		T52	4
valid_sources[0x5f]	177	1			T37	2		T38	3		T50	2
valid_sources[0x60]	195	1			T27	1		T77	3		T37	1
valid_sources[0x61]	253	1			T2	1		T3	1		T77	2
valid_sources[0x62]	205	1			T11	5		T210	1		T93	3
valid_sources[0x63]	211	1			T3	1		T37	1		T13	1
valid_sources[0x64]	207	1			T77	1		T13	2		T41	3
valid_sources[0x65]	329	1			T3	2		T37	1		T13	4
valid_sources[0x66]	232	1			T77	3		T13	5		T50	4
valid_sources[0x67]	215	1			T3	2		T11	1		T63	1
valid_sources[0x68]	267	1			T11	2		T76	3		T77	2
valid_sources[0x69]	218	1			T3	1		T4	2		T76	6
valid_sources[0x6a]	232	1			T76	11		T41	2		T210	1
valid_sources[0x6b]	527	1			T24	47		T34	1		T37	2
valid_sources[0x6c]	269	1			T2	3		T3	1		T4	7
valid_sources[0x6d]	216	1			T77	1		T211	1		T52	1
valid_sources[0x6e]	238	1			T77	1		T13	1		T86	5
valid_sources[0x6f]	410	1			T3	1		T37	2		T63	2
valid_sources[0x70]	204	1			T26	1		T77	2		T37	1
valid_sources[0x71]	368	1			T77	1		T142	1		T13	1
valid_sources[0x72]	298	1			T3	2		T47	1		T50	5
valid_sources[0x73]	286	1			T77	2		T13	2		T218	5
valid_sources[0x74]	417	1			T3	2		T91	3		T53	1
valid_sources[0x75]	204	1			T2	2		T11	2		T13	4
valid_sources[0x76]	235	1			T2	1		T3	2		T12	13
valid_sources[0x77]	218	1			T211	1		T216	5		T51	5
valid_sources[0x78]	246	1			T77	1		T63	3		T13	1
valid_sources[0x79]	215	1			T3	1		T37	1		T98	1
valid_sources[0x7a]	318	1			T16	1		T77	2		T13	1
valid_sources[0x7b]	236	1			T3	1		T54	1		T77	1
valid_sources[0x7c]	358	1			T76	1		T77	1		T53	1
valid_sources[0x7d]	276	1			T16	1		T77	1		T211	3
valid_sources[0x7e]	242	1			T3	2		T16	3		T13	2
valid_sources[0x7f]	203	1			T76	2		T77	1		T13	1
valid_sources[0x80]	258	1			T3	1		T211	3		T53	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

14800

1

T1

1

T2

4

T3

73

values[0x0]

all_enables

biggest_size

8201

1

T2

7

T3

4

T4

3

values[0x1]

all_enables

biggest_size

6195

1

T2

1

T3

1

T4

1