SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 4 | 1 | T196 | 1 | T200 | 1 | T201 | 1 | ||||
others[1] | 12 | 1 | T94 | 1 | T199 | 1 | T195 | 2 | ||||
others[2] | 11 | 1 | T93 | 1 | T202 | 1 | T197 | 1 | ||||
others[3] | 12 | 1 | T2 | 2 | T94 | 1 | T203 | 1 | ||||
false | 128 | 1 | T2 | 3 | T9 | 2 | T23 | 2 | ||||
true | 2656 | 1 | T1 | 5 | T2 | 3 | T3 | 13 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 11 | 1 | T2 | 1 | T199 | 1 | T194 | 1 | ||||
others[1] | 10 | 1 | T23 | 1 | T199 | 1 | T202 | 1 | ||||
others[2] | 16 | 1 | T24 | 1 | T38 | 1 | T93 | 1 | ||||
others[3] | 13 | 1 | T24 | 1 | T38 | 1 | T145 | 2 | ||||
false | 150 | 1 | T2 | 3 | T9 | 4 | T23 | 3 | ||||
true | 2757 | 1 | T1 | 5 | T2 | 6 | T3 | 13 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 351 | 1 | T2 | 2 | T9 | 1 | T23 | 1 | ||||
others[1] | 302 | 1 | T9 | 1 | T76 | 5 | T77 | 4 | ||||
others[2] | 333 | 1 | T76 | 4 | T31 | 1 | T34 | 1 | ||||
others[3] | 567 | 1 | T76 | 9 | T31 | 1 | T77 | 11 | ||||
false | 3722 | 1 | T1 | 5 | T2 | 7 | T3 | 19 | ||||
true | 763 | 1 | T2 | 3 | T3 | 6 | T9 | 2 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |