Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2770936	12622	0	0
intr_enable_rd_A	2770936	2027	0	0
reset_en_rd_A	2770936	724	0	0
reset_en_regwen_rd_A	2770936	816	0	0
wake_info_capture_dis_rd_A	2770936	727	0	0
wakeup_en_rd_A	2770936	1324	0	0
wakeup_en_regwen_rd_A	2770936	741	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2770936	12622	0	0
T19	1922	187	0	0
T20	1780	14	0	0
T21	6624	2	0	0
T55	1244	12	0	0
T56	9202	623	0	0
T57	4901	5	0	0
T59	2568	240	0	0
T60	6249	5	0	0
T61	1768	129	0	0
T90	2644	153	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2770936	2027	0	0
T11	2127	59	0	0
T12	2806	42	0	0
T16	17269	0	0	0
T24	4744	0	0	0
T25	2882	0	0	0
T27	0	7	0	0
T30	822	0	0	0
T31	2606	0	0	0
T32	2016	0	0	0
T76	3743	0	0	0
T82	0	3	0	0
T126	1886	0	0	0
T128	0	24	0	0
T129	0	26	0	0
T130	0	24	0	0
T131	0	7	0	0
T132	0	6	0	0
T133	0	110	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2770936	724	0	0
T55	1244	6	0	0
T60	6249	67	0	0
T70	11185	89	0	0
T105	1703	9	0	0
T107	1877	3	0	0
T109	1974	2	0	0
T125	2106	12	0	0
T134	1761	3	0	0
T135	1272	7	0	0
T136	5113	36	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2770936	816	0	0
T55	1244	4	0	0
T60	6249	48	0	0
T70	11185	70	0	0
T105	1703	8	0	0
T107	1877	11	0	0
T125	2106	55	0	0
T134	1761	7	0	0
T135	1272	5	0	0
T137	5922	15	0	0
T138	5065	7	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2770936	727	0	0
T55	1244	3	0	0
T60	6249	21	0	0
T70	11185	68	0	0
T105	1703	14	0	0
T107	1877	5	0	0
T125	2106	44	0	0
T134	1761	10	0	0
T136	5113	22	0	0
T137	5922	17	0	0
T138	5065	6	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2770936	1324	0	0
T55	1244	2	0	0
T60	6249	129	0	0
T70	11185	270	0	0
T105	1703	11	0	0
T107	1877	26	0	0
T109	1974	7	0	0
T125	2106	14	0	0
T135	1272	1	0	0
T136	5113	70	0	0
T138	5065	7	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2770936	741	0	0
T55	1244	7	0	0
T60	6249	44	0	0
T70	11185	59	0	0
T105	1703	5	0	0
T107	1877	13	0	0
T109	1974	7	0	0
T125	2106	10	0	0
T135	1272	3	0	0
T137	5922	7	0	0
T138	5065	19	0	0