Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	6781251	9560	0	0
StatusRise_A	6781251	12999	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6781251	9560	0	0
T2	4692	15	0	0
T3	12876	54	0	0
T4	4557	6	0	0
T5	45258	3	0	0
T6	45057	3	0	0
T7	5970	3	0	0
T8	46728	3	0	0
T9	12294	21	0	0
T10	2640	0	0	0
T23	0	15	0	0
T39	46536	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6781251	12999	0	0
T1	2061	15	0	0
T2	4692	21	0	0
T3	12876	60	0	0
T4	4557	9	0	0
T5	45258	6	0	0
T6	45057	6	0	0
T7	5970	9	0	0
T8	46728	6	0	0
T9	12294	24	0	0
T10	2640	6	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	2260417	3214	0	0
StatusRise_A	2260417	4371	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2260417	3214	0	0
T2	1564	5	0	0
T3	4292	18	0	0
T4	1519	2	0	0
T5	15086	1	0	0
T6	15019	1	0	0
T7	1990	1	0	0
T8	15576	1	0	0
T9	4098	7	0	0
T10	880	0	0	0
T23	0	5	0	0
T39	15512	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2260417	4371	0	0
T1	687	5	0	0
T2	1564	7	0	0
T3	4292	20	0	0
T4	1519	3	0	0
T5	15086	2	0	0
T6	15019	2	0	0
T7	1990	3	0	0
T8	15576	2	0	0
T9	4098	8	0	0
T10	880	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	2260417	3214	0	0
StatusRise_A	2260417	4371	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2260417	3214	0	0
T2	1564	5	0	0
T3	4292	18	0	0
T4	1519	2	0	0
T5	15086	1	0	0
T6	15019	1	0	0
T7	1990	1	0	0
T8	15576	1	0	0
T9	4098	7	0	0
T10	880	0	0	0
T23	0	5	0	0
T39	15512	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2260417	4371	0	0
T1	687	5	0	0
T2	1564	7	0	0
T3	4292	20	0	0
T4	1519	3	0	0
T5	15086	2	0	0
T6	15019	2	0	0
T7	1990	3	0	0
T8	15576	2	0	0
T9	4098	8	0	0
T10	880	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	2260417	3132	0	0
StatusRise_A	2260417	4257	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2260417	3132	0	0
T2	1564	5	0	0
T3	4292	18	0	0
T4	1519	2	0	0
T5	15086	1	0	0
T6	15019	1	0	0
T7	1990	1	0	0
T8	15576	1	0	0
T9	4098	7	0	0
T10	880	0	0	0
T23	0	5	0	0
T39	15512	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2260417	4257	0	0
T1	687	5	0	0
T2	1564	7	0	0
T3	4292	20	0	0
T4	1519	3	0	0
T5	15086	2	0	0
T6	15019	2	0	0
T7	1990	3	0	0
T8	15576	2	0	0
T9	4098	8	0	0
T10	880	2	0	0