Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	2260779	5594	0	0
EscTimeoutStoppedByClReset_A	2260417	77686	0	0
EscTimeoutTriggersReset_A	300232	319	0	0
RomAllowActiveState_A	2260417	3971	0	0
RomAllowCheckGoodState_A	2260417	4021	0	0
RomBlockActiveState_A	2260417	31711	0	0
RomBlockCheckGoodState_A	2260417	20722	0	0
RomIntgChkDisFalse_A	2260417	2072742	0	0
RomIntgChkDisTrue_A	2260417	33312	0	0
RstreqChkEsctimeout_A	2260417	1000	0	0
RstreqChkFsmterm_A	2260417	160	0	0
RstreqChkGlbesc_A	2260417	1000	0	0
RstreqChkMainpd_A	2260417	55947	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2260779	5594	0	0
T5	15087	58	0	0
T6	15020	29	0	0
T7	1991	22	0	0
T8	15577	116	0	0
T9	4099	0	0	0
T10	880	0	0	0
T14	1842	0	0	0
T15	2873	0	0	0
T23	3852	0	0	0
T30	0	11	0	0
T33	0	216	0	0
T39	15512	167	0	0
T139	0	157	0	0
T140	0	18	0	0
T141	0	15	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2260417	77686	0	0
T1	687	25	0	0
T2	1564	117	0	0
T3	4292	411	0	0
T4	1519	37	0	0
T5	15086	12	0	0
T6	15019	11	0	0
T7	1990	12	0	0
T8	15576	11	0	0
T9	4098	350	0	0
T10	880	22	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300232	319	0	0
T5	369	2	0	0
T6	1073	3	0	0
T7	198	2	0	0
T8	237	2	0	0
T9	377	0	0	0
T10	720	0	0	0
T14	290	0	0	0
T15	278	0	0	0
T23	379	0	0	0
T30	0	4	0	0
T33	0	3	0	0
T39	201	2	0	0
T139	0	2	0	0
T142	0	2	0	0
T143	0	5	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2260417	3971	0	0
T1	687	5	0	0
T2	1564	7	0	0
T3	4292	13	0	0
T4	1519	3	0	0
T5	15086	2	0	0
T6	15019	2	0	0
T7	1990	3	0	0
T8	15576	2	0	0
T9	4098	8	0	0
T10	880	2	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2260417	4021	0	0
T1	687	5	0	0
T2	1564	7	0	0
T3	4292	14	0	0
T4	1519	3	0	0
T5	15086	2	0	0
T6	15019	2	0	0
T7	1990	3	0	0
T8	15576	2	0	0
T9	4098	8	0	0
T10	880	2	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2260417	31711	0	0
T2	1564	232	0	0
T3	4292	0	0	0
T4	1519	0	0	0
T5	15086	0	0	0
T6	15019	0	0	0
T7	1990	0	0	0
T8	15576	0	0	0
T9	4098	666	0	0
T10	880	0	0	0
T23	0	484	0	0
T24	0	934	0	0
T35	0	1072	0	0
T38	0	85	0	0
T39	15512	0	0	0
T93	0	934	0	0
T94	0	1337	0	0
T144	0	324	0	0
T145	0	220	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2260417	20722	0	0
T2	1564	73	0	0
T3	4292	0	0	0
T4	1519	0	0	0
T5	15086	0	0	0
T6	15019	0	0	0
T7	1990	0	0	0
T8	15576	0	0	0
T9	4098	562	0	0
T10	880	0	0	0
T23	0	596	0	0
T24	0	1037	0	0
T35	0	439	0	0
T38	0	23	0	0
T39	15512	0	0	0
T93	0	667	0	0
T94	0	617	0	0
T144	0	131	0	0
T145	0	84	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2260417	2072742	0	0
T1	687	306	0	0
T2	1564	912	0	0
T3	4292	3367	0	0
T4	1519	1455	0	0
T5	15086	14988	0	0
T6	15019	14923	0	0
T7	1990	1849	0	0
T8	15576	15492	0	0
T9	4098	3938	0	0
T10	880	766	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2260417	33312	0	0
T2	1564	491	0	0
T3	4292	0	0	0
T4	1519	0	0	0
T5	15086	0	0	0
T6	15019	0	0	0
T7	1990	0	0	0
T8	15576	0	0	0
T9	4098	87	0	0
T10	880	0	0	0
T23	0	83	0	0
T24	0	1414	0	0
T35	0	567	0	0
T38	0	33	0	0
T39	15512	0	0	0
T93	0	2977	0	0
T94	0	258	0	0
T144	0	900	0	0
T145	0	74	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2260417	1000	0	0
T2	1564	4	0	0
T3	4292	10	0	0
T4	1519	0	0	0
T5	15086	1	0	0
T6	15019	1	0	0
T7	1990	1	0	0
T8	15576	1	0	0
T9	4098	1	0	0
T10	880	0	0	0
T23	0	1	0	0
T24	0	4	0	0
T39	15512	1	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2260417	160	0	0
T16	17269	40	0	0
T17	0	20	0	0
T18	0	40	0	0
T25	2882	0	0	0
T26	3072	0	0	0
T27	1417	0	0	0
T28	0	20	0	0
T29	0	40	0	0
T30	822	0	0	0
T31	2606	0	0	0
T32	2016	0	0	0
T33	15906	0	0	0
T34	2916	0	0	0
T35	4784	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2260417	1000	0	0
T2	1564	4	0	0
T3	4292	10	0	0
T4	1519	0	0	0
T5	15086	1	0	0
T6	15019	1	0	0
T7	1990	1	0	0
T8	15576	1	0	0
T9	4098	1	0	0
T10	880	0	0	0
T23	0	1	0	0
T24	0	4	0	0
T39	15512	1	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2260417	55947	0	0
T1	687	18	0	0
T2	1564	48	0	0
T3	4292	158	0	0
T4	1519	0	0	0
T5	15086	0	0	0
T6	15019	0	0	0
T7	1990	0	0	0
T8	15576	0	0	0
T9	4098	961	0	0
T10	880	6	0	0
T14	0	15	0	0
T15	0	10	0	0
T23	0	78	0	0
T40	0	16	0	0
T146	0	17	0	0