Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	41450	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

31762

1

T1

122

T4

77

T5

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36934	1			T1	219		T2	1		T3	1
values[0x0]	18122	1			T1	22		T4	76		T7	5
values[0x1]	18156	1			T1	11		T4	84		T5	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	33269	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

39943

1

T1

146

T2

1

T4

114

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	182	1			T4	4		T76	1		T198	1
valid_sources[0x01]	157	1			T1	2		T10	2		T76	1
valid_sources[0x02]	226	1			T8	1		T76	2		T52	1
valid_sources[0x03]	224	1			T52	1		T40	3		T199	1
valid_sources[0x04]	685	1			T4	2		T87	1		T40	3
valid_sources[0x05]	227	1			T10	1		T76	1		T29	1
valid_sources[0x06]	540	1			T1	1		T4	3		T76	1
valid_sources[0x07]	276	1			T1	1		T4	4		T10	2
valid_sources[0x08]	358	1			T1	1		T13	1		T52	1
valid_sources[0x09]	182	1			T1	1		T8	1		T76	1
valid_sources[0x0a]	255	1			T1	1		T76	1		T52	1
valid_sources[0x0b]	197	1			T38	1		T39	2		T40	1
valid_sources[0x0c]	379	1			T1	1		T4	5		T7	29
valid_sources[0x0d]	368	1			T4	3		T10	1		T76	1
valid_sources[0x0e]	299	1			T1	1		T40	1		T116	1
valid_sources[0x0f]	253	1			T1	2		T76	1		T29	1
valid_sources[0x10]	227	1			T1	2		T8	1		T10	1
valid_sources[0x11]	527	1			T1	5		T4	1		T8	1
valid_sources[0x12]	327	1			T1	1		T76	1		T36	3
valid_sources[0x13]	257	1			T1	1		T4	10		T36	2
valid_sources[0x14]	207	1			T1	1		T10	1		T76	1
valid_sources[0x15]	394	1			T1	1		T4	4		T76	1
valid_sources[0x16]	450	1			T1	2		T10	1		T15	1
valid_sources[0x17]	334	1			T15	4		T50	2		T51	2
valid_sources[0x18]	298	1			T4	4		T37	13		T200	1
valid_sources[0x19]	244	1			T4	2		T76	1		T52	1
valid_sources[0x1a]	188	1			T13	3		T76	1		T15	3
valid_sources[0x1b]	238	1			T1	1		T44	1		T200	1
valid_sources[0x1c]	234	1			T4	7		T76	1		T25	1
valid_sources[0x1d]	240	1			T1	1		T36	1		T52	1
valid_sources[0x1e]	224	1			T1	1		T8	1		T87	3
valid_sources[0x1f]	321	1			T76	1		T30	1		T24	4
valid_sources[0x20]	341	1			T4	2		T8	1		T29	2
valid_sources[0x21]	254	1			T1	2		T76	1		T29	1
valid_sources[0x22]	332	1			T1	1		T76	1		T39	3
valid_sources[0x23]	402	1			T48	1		T199	2		T79	1
valid_sources[0x24]	378	1			T8	2		T10	1		T76	1
valid_sources[0x25]	390	1			T1	2		T13	2		T76	1
valid_sources[0x26]	259	1			T1	2		T10	1		T37	4
valid_sources[0x27]	186	1			T1	1		T4	1		T8	3
valid_sources[0x28]	253	1			T29	1		T52	1		T24	12
valid_sources[0x29]	313	1			T1	1		T4	4		T10	1
valid_sources[0x2a]	512	1			T8	2		T10	1		T76	1
valid_sources[0x2b]	317	1			T1	1		T76	1		T15	13
valid_sources[0x2c]	212	1			T1	2		T4	14		T76	1
valid_sources[0x2d]	614	1			T76	1		T39	6		T201	1
valid_sources[0x2e]	328	1			T1	2		T8	1		T10	1
valid_sources[0x2f]	198	1			T1	4		T52	1		T77	7
valid_sources[0x30]	318	1			T29	2		T15	2		T34	1
valid_sources[0x31]	206	1			T10	5		T76	1		T52	4
valid_sources[0x32]	172	1			T4	4		T8	5		T76	2
valid_sources[0x33]	295	1			T13	2		T76	1		T15	1
valid_sources[0x34]	236	1			T1	2		T52	1		T41	1
valid_sources[0x35]	211	1			T1	1		T8	1		T10	2
valid_sources[0x36]	219	1			T42	1		T39	2		T41	1
valid_sources[0x37]	263	1			T10	2		T76	1		T15	3
valid_sources[0x38]	235	1			T1	3		T8	1		T52	2
valid_sources[0x39]	269	1			T1	3		T4	5		T10	5
valid_sources[0x3a]	230	1			T1	1		T36	3		T24	2
valid_sources[0x3b]	400	1			T76	2		T116	1		T50	1
valid_sources[0x3c]	283	1			T1	1		T8	3		T34	1
valid_sources[0x3d]	274	1			T4	4		T78	1		T79	1
valid_sources[0x3e]	185	1			T1	3		T8	1		T39	1
valid_sources[0x3f]	438	1			T1	1		T8	1		T76	1
valid_sources[0x40]	325	1			T2	1		T9	1		T24	1
valid_sources[0x41]	242	1			T76	1		T29	1		T37	5
valid_sources[0x42]	303	1			T1	1		T10	1		T34	1
valid_sources[0x43]	226	1			T10	3		T76	1		T41	1
valid_sources[0x44]	288	1			T52	1		T40	1		T199	2
valid_sources[0x45]	147	1			T1	2		T10	2		T52	1
valid_sources[0x46]	189	1			T1	1		T13	1		T76	1
valid_sources[0x47]	421	1			T24	1		T201	3		T50	6
valid_sources[0x48]	263	1			T1	1		T76	1		T24	2
valid_sources[0x49]	297	1			T4	3		T34	1		T52	1
valid_sources[0x4a]	300	1			T1	2		T76	1		T34	1
valid_sources[0x4b]	206	1			T8	1		T16	1		T15	3
valid_sources[0x4c]	415	1			T4	6		T29	1		T52	1
valid_sources[0x4d]	228	1			T1	1		T10	1		T76	1
valid_sources[0x4e]	462	1			T1	4		T10	1		T87	1
valid_sources[0x4f]	239	1			T1	1		T4	12		T10	2
valid_sources[0x50]	230	1			T1	2		T4	6		T76	1
valid_sources[0x51]	216	1			T1	2		T8	1		T38	1
valid_sources[0x52]	243	1			T34	1		T39	1		T40	1
valid_sources[0x53]	257	1			T1	2		T36	1		T87	1
valid_sources[0x54]	194	1			T52	1		T87	3		T39	2
valid_sources[0x55]	196	1			T1	1		T8	1		T76	1
valid_sources[0x56]	255	1			T8	3		T29	1		T52	2
valid_sources[0x57]	347	1			T1	2		T76	2		T44	4
valid_sources[0x58]	231	1			T10	2		T76	1		T39	4
valid_sources[0x59]	338	1			T37	2		T87	1		T116	1
valid_sources[0x5a]	409	1			T78	1		T41	1		T79	1
valid_sources[0x5b]	256	1			T1	1		T10	2		T29	1
valid_sources[0x5c]	206	1			T76	1		T38	1		T40	1
valid_sources[0x5d]	241	1			T1	2		T4	11		T76	1
valid_sources[0x5e]	335	1			T1	2		T34	1		T36	1
valid_sources[0x5f]	272	1			T29	1		T14	14		T34	1
valid_sources[0x60]	298	1			T4	12		T76	2		T24	2
valid_sources[0x61]	247	1			T1	1		T34	1		T40	1
valid_sources[0x62]	212	1			T1	1		T25	1		T36	1
valid_sources[0x63]	208	1			T8	1		T10	2		T34	1
valid_sources[0x64]	240	1			T8	1		T76	1		T36	1
valid_sources[0x65]	202	1			T1	1		T8	1		T10	3
valid_sources[0x66]	324	1			T4	2		T8	1		T52	2
valid_sources[0x67]	198	1			T1	1		T52	3		T24	1
valid_sources[0x68]	226	1			T34	2		T36	2		T52	1
valid_sources[0x69]	370	1			T1	2		T8	2		T10	3
valid_sources[0x6a]	169	1			T4	5		T76	1		T37	1
valid_sources[0x6b]	231	1			T76	2		T12	1		T52	1
valid_sources[0x6c]	170	1			T8	3		T10	3		T76	1
valid_sources[0x6d]	202	1			T1	1		T36	3		T52	2
valid_sources[0x6e]	268	1			T8	1		T76	1		T15	1
valid_sources[0x6f]	176	1			T1	3		T29	2		T38	1
valid_sources[0x70]	315	1			T16	2		T15	5		T40	2
valid_sources[0x71]	510	1			T1	1		T8	1		T36	1
valid_sources[0x72]	273	1			T1	1		T25	1		T38	2
valid_sources[0x73]	264	1			T1	1		T4	11		T24	2
valid_sources[0x74]	448	1			T1	3		T4	5		T36	2
valid_sources[0x75]	193	1			T1	1		T4	4		T8	2
valid_sources[0x76]	192	1			T1	2		T76	1		T15	6
valid_sources[0x77]	271	1			T1	1		T10	2		T76	2
valid_sources[0x78]	206	1			T1	1		T8	1		T76	1
valid_sources[0x79]	220	1			T1	2		T76	1		T40	1
valid_sources[0x7a]	262	1			T87	1		T199	1		T202	4
valid_sources[0x7b]	383	1			T1	1		T4	11		T8	1
valid_sources[0x7c]	362	1			T34	2		T28	1		T84	12
valid_sources[0x7d]	224	1			T1	2		T76	1		T87	4
valid_sources[0x7e]	354	1			T8	2		T76	2		T29	2
valid_sources[0x7f]	200	1			T8	6		T29	2		T24	2
valid_sources[0x80]	286	1			T10	1		T36	1		T39	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

15864

1

T1

113

T4

49

T7

8

values[0x0]

all_enables

biggest_size

9293

1

T1

8

T4

21

T7

2

values[0x1]

all_enables

biggest_size

6605

1

T1

1

T4

7

T5

1