Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2898150	12225	0	0
intr_enable_rd_A	2898150	2791	0	0
reset_en_rd_A	2898150	1615	0	0
reset_en_regwen_rd_A	2898150	1334	0	0
wake_info_capture_dis_rd_A	2898150	1365	0	0
wakeup_en_rd_A	2898150	2160	0	0
wakeup_en_regwen_rd_A	2898150	1426	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2898150	12225	0	0
T19	2970	16	0	0
T20	3867	733	0	0
T21	8336	10	0	0
T53	5402	309	0	0
T55	7197	377	0	0
T56	6725	4	0	0
T63	3652	262	0	0
T72	1993	33	0	0
T73	1587	211	0	0
T86	4159	42	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2898150	2791	0	0
T10	5659	29	0	0
T11	15477	0	0	0
T13	2415	4	0	0
T14	1556	0	0	0
T15	1631	0	0	0
T16	15216	0	0	0
T25	2902	0	0	0
T29	2718	0	0	0
T30	1806	0	0	0
T33	0	75	0	0
T36	0	3	0	0
T49	0	6	0	0
T50	0	56	0	0
T76	4735	0	0	0
T83	0	22	0	0
T84	0	59	0	0
T115	0	36	0	0
T116	0	16	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2898150	1615	0	0
T53	5402	8	0	0
T55	7197	19	0	0
T61	1394	7	0	0
T69	1095	7	0	0
T72	1993	17	0	0
T86	4159	22	0	0
T111	3393	36	0	0
T117	26680	214	0	0
T118	7231	10	0	0
T119	14706	130	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2898150	1334	0	0
T53	5402	17	0	0
T55	7197	3	0	0
T61	1394	9	0	0
T65	10374	22	0	0
T69	1095	5	0	0
T72	1993	16	0	0
T86	4159	11	0	0
T111	3393	11	0	0
T117	26680	236	0	0
T120	1436	2	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2898150	1365	0	0
T53	5402	7	0	0
T55	7197	12	0	0
T61	1394	3	0	0
T65	10374	6	0	0
T69	1095	2	0	0
T72	1993	3	0	0
T86	4159	16	0	0
T111	3393	26	0	0
T117	26680	239	0	0
T120	1436	5	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2898150	2160	0	0
T53	5402	9	0	0
T55	7197	4	0	0
T65	10374	8	0	0
T69	1095	6	0	0
T72	1993	27	0	0
T86	4159	20	0	0
T111	3393	33	0	0
T117	26680	225	0	0
T119	14706	244	0	0
T120	1436	1	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2898150	1426	0	0
T53	5402	3	0	0
T55	7197	21	0	0
T61	1394	9	0	0
T65	10374	6	0	0
T72	1993	9	0	0
T86	4159	20	0	0
T111	3393	56	0	0
T117	26680	289	0	0
T118	7231	6	0	0
T119	14706	82	0	0