Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	6861573	9982	0	0
StatusRise_A	6861573	13478	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6861573	9982	0	0
T1	21195	54	0	0
T2	5271	0	0	0
T3	5055	0	0	0
T4	13332	57	0	0
T5	45168	3	0	0
T6	3903	0	0	0
T7	5859	6	0	0
T8	23586	96	0	0
T9	4653	0	0	0
T10	16977	3	0	0
T13	0	6	0	0
T14	0	4	0	0
T29	0	12	0	0
T76	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6861573	13478	0	0
T1	21195	57	0	0
T2	5271	18	0	0
T3	5055	9	0	0
T4	13332	60	0	0
T5	45168	6	0	0
T6	3903	9	0	0
T7	5859	9	0	0
T8	23586	102	0	0
T9	4653	15	0	0
T10	16977	6	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	2287191	3369	0	0
StatusRise_A	2287191	4547	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2287191	3369	0	0
T1	7065	18	0	0
T2	1757	0	0	0
T3	1685	0	0	0
T4	4444	20	0	0
T5	15056	1	0	0
T6	1301	0	0	0
T7	1953	2	0	0
T8	7862	32	0	0
T9	1551	0	0	0
T10	5659	1	0	0
T13	0	2	0	0
T14	0	1	0	0
T29	0	4	0	0
T76	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2287191	4547	0	0
T1	7065	19	0	0
T2	1757	6	0	0
T3	1685	3	0	0
T4	4444	21	0	0
T5	15056	2	0	0
T6	1301	3	0	0
T7	1953	3	0	0
T8	7862	34	0	0
T9	1551	5	0	0
T10	5659	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	2287191	3369	0	0
StatusRise_A	2287191	4547	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2287191	3369	0	0
T1	7065	18	0	0
T2	1757	0	0	0
T3	1685	0	0	0
T4	4444	20	0	0
T5	15056	1	0	0
T6	1301	0	0	0
T7	1953	2	0	0
T8	7862	32	0	0
T9	1551	0	0	0
T10	5659	1	0	0
T13	0	2	0	0
T14	0	1	0	0
T29	0	4	0	0
T76	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2287191	4547	0	0
T1	7065	19	0	0
T2	1757	6	0	0
T3	1685	3	0	0
T4	4444	21	0	0
T5	15056	2	0	0
T6	1301	3	0	0
T7	1953	3	0	0
T8	7862	34	0	0
T9	1551	5	0	0
T10	5659	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	2287191	3244	0	0
StatusRise_A	2287191	4384	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2287191	3244	0	0
T1	7065	18	0	0
T2	1757	0	0	0
T3	1685	0	0	0
T4	4444	17	0	0
T5	15056	1	0	0
T6	1301	0	0	0
T7	1953	2	0	0
T8	7862	32	0	0
T9	1551	0	0	0
T10	5659	1	0	0
T13	0	2	0	0
T14	0	2	0	0
T29	0	4	0	0
T76	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2287191	4384	0	0
T1	7065	19	0	0
T2	1757	6	0	0
T3	1685	3	0	0
T4	4444	18	0	0
T5	15056	2	0	0
T6	1301	3	0	0
T7	1953	3	0	0
T8	7862	34	0	0
T9	1551	5	0	0
T10	5659	2	0	0