Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	2287559	5366	0	0
EscTimeoutStoppedByClReset_A	2287191	91217	0	0
EscTimeoutTriggersReset_A	334101	302	0	0
RomAllowActiveState_A	2287191	4177	0	0
RomAllowCheckGoodState_A	2287191	4227	0	0
RomBlockActiveState_A	2287191	32466	0	0
RomBlockCheckGoodState_A	2287191	19642	0	0
RomIntgChkDisFalse_A	2287191	2094321	0	0
RomIntgChkDisTrue_A	2287191	35205	0	0
RstreqChkEsctimeout_A	2287191	1065	0	0
RstreqChkFsmterm_A	2287191	180	0	0
RstreqChkGlbesc_A	2287191	1065	0	0
RstreqChkMainpd_A	2287191	56460	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2287559	5366	0	0
T5	15057	31	0	0
T6	1301	0	0	0
T7	1954	0	0	0
T8	7862	0	0	0
T9	1552	0	0	0
T10	5660	0	0	0
T11	0	185	0	0
T12	0	18	0	0
T13	2415	0	0	0
T14	1557	0	0	0
T29	2719	0	0	0
T42	0	129	0	0
T76	4735	0	0	0
T88	0	4	0	0
T121	0	40	0	0
T122	0	96	0	0
T123	0	72	0	0
T124	0	72	0	0
T125	0	9	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2287191	91217	0	0
T1	7065	293	0	0
T2	1757	30	0	0
T3	1685	29	0	0
T4	4444	4	0	0
T5	15056	9	0	0
T6	1301	5	0	0
T7	1953	10	0	0
T8	7862	1373	0	0
T9	1551	58	0	0
T10	5659	12	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334101	302	0	0
T5	655	2	0	0
T6	236	0	0	0
T7	228	0	0	0
T8	590	0	0	0
T9	536	0	0	0
T10	437	0	0	0
T11	0	2	0	0
T12	0	2	0	0
T13	212	0	0	0
T14	133	0	0	0
T29	324	0	0	0
T35	0	4	0	0
T42	0	2	0	0
T76	362	0	0	0
T88	0	4	0	0
T121	0	3	0	0
T122	0	2	0	0
T126	0	4	0	0
T127	0	3	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2287191	4177	0	0
T1	7065	12	0	0
T2	1757	6	0	0
T3	1685	3	0	0
T4	4444	21	0	0
T5	15056	2	0	0
T6	1301	3	0	0
T7	1953	3	0	0
T8	7862	34	0	0
T9	1551	5	0	0
T10	5659	2	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2287191	4227	0	0
T1	7065	13	0	0
T2	1757	6	0	0
T3	1685	3	0	0
T4	4444	21	0	0
T5	15056	2	0	0
T6	1301	3	0	0
T7	1953	3	0	0
T8	7862	34	0	0
T9	1551	5	0	0
T10	5659	2	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2287191	32466	0	0
T12	15053	0	0	0
T25	2902	458	0	0
T26	1357	168	0	0
T27	0	1342	0	0
T28	0	451	0	0
T33	4678	0	0	0
T34	3014	0	0	0
T35	863	0	0	0
T36	5133	0	0	0
T37	4407	0	0	0
T42	15554	0	0	0
T52	1352	0	0	0
T128	0	11	0	0
T129	0	409	0	0
T130	0	986	0	0
T131	0	1148	0	0
T132	0	461	0	0
T133	0	1539	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2287191	19642	0	0
T12	15053	0	0	0
T25	2902	411	0	0
T26	1357	74	0	0
T27	0	639	0	0
T28	0	294	0	0
T33	4678	0	0	0
T34	3014	0	0	0
T35	863	0	0	0
T36	5133	0	0	0
T37	4407	0	0	0
T42	15554	0	0	0
T52	1352	0	0	0
T129	0	140	0	0
T130	0	369	0	0
T131	0	908	0	0
T132	0	267	0	0
T133	0	1080	0	0
T134	0	1037	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2287191	2094321	0	0
T1	7065	6132	0	0
T2	1757	1309	0	0
T3	1685	1464	0	0
T4	4444	4387	0	0
T5	15056	14985	0	0
T6	1301	1062	0	0
T7	1953	1866	0	0
T8	7862	7739	0	0
T9	1551	1235	0	0
T10	5659	5563	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2287191	35205	0	0
T12	15053	0	0	0
T25	2902	1035	0	0
T26	1357	74	0	0
T27	0	1634	0	0
T28	0	910	0	0
T33	4678	0	0	0
T34	3014	0	0	0
T35	863	0	0	0
T36	5133	0	0	0
T37	4407	0	0	0
T42	15554	0	0	0
T52	1352	0	0	0
T128	0	310	0	0
T129	0	95	0	0
T130	0	2165	0	0
T132	0	95	0	0
T133	0	267	0	0
T134	0	1393	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2287191	1065	0	0
T1	7065	4	0	0
T2	1757	0	0	0
T3	1685	0	0	0
T4	4444	0	0	0
T5	15056	1	0	0
T6	1301	0	0	0
T7	1953	0	0	0
T8	7862	11	0	0
T9	1551	0	0	0
T10	5659	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T16	0	10	0	0
T25	0	1	0	0
T30	0	4	0	0
T34	0	2	0	0
T35	0	1	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2287191	180	0	0
T11	15477	0	0	0
T12	15053	0	0	0
T15	1631	0	0	0
T16	15216	20	0	0
T17	0	40	0	0
T18	0	40	0	0
T25	2902	0	0	0
T30	1806	0	0	0
T31	0	40	0	0
T32	0	40	0	0
T33	4678	0	0	0
T34	3014	0	0	0
T35	863	0	0	0
T36	5133	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2287191	1065	0	0
T1	7065	4	0	0
T2	1757	0	0	0
T3	1685	0	0	0
T4	4444	0	0	0
T5	15056	1	0	0
T6	1301	0	0	0
T7	1953	0	0	0
T8	7862	11	0	0
T9	1551	0	0	0
T10	5659	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T16	0	10	0	0
T25	0	1	0	0
T30	0	4	0	0
T34	0	2	0	0
T35	0	1	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2287191	56460	0	0
T1	7065	124	0	0
T2	1757	28	0	0
T3	1685	10	0	0
T4	4444	0	0	0
T5	15056	0	0	0
T6	1301	6	0	0
T7	1953	0	0	0
T8	7862	1427	0	0
T9	1551	22	0	0
T10	5659	0	0	0
T25	0	42	0	0
T26	0	65	0	0
T34	0	194	0	0
T37	0	439	0	0