Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	40516	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

29081

1

T1

84

T2

4

T4

135

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	35622	1			T1	136		T2	15		T4	242
values[0x0]	16819	1			T1	69		T2	3		T4	22
values[0x1]	17156	1			T1	59		T2	5		T3	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	32560	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

37037

1

T1

124

T2

9

T4

157

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	204	1			T1	2		T4	1		T18	2
valid_sources[0x01]	229	1			T1	3		T4	1		T7	4
valid_sources[0x02]	218	1			T1	6		T4	3		T7	2
valid_sources[0x03]	234	1			T87	1		T207	1		T95	1
valid_sources[0x04]	310	1			T1	2		T4	1		T7	1
valid_sources[0x05]	211	1			T1	2		T4	1		T7	3
valid_sources[0x06]	181	1			T1	3		T9	2		T93	1
valid_sources[0x07]	220	1			T35	2		T32	2		T12	2
valid_sources[0x08]	252	1			T1	4		T2	1		T4	2
valid_sources[0x09]	293	1			T35	1		T124	1		T41	21
valid_sources[0x0a]	267	1			T1	1		T4	1		T35	1
valid_sources[0x0b]	487	1			T4	2		T6	2		T9	6
valid_sources[0x0c]	227	1			T4	1		T7	1		T10	1
valid_sources[0x0d]	276	1			T1	2		T4	1		T9	1
valid_sources[0x0e]	318	1			T1	6		T14	3		T208	1
valid_sources[0x0f]	281	1			T1	1		T4	1		T7	4
valid_sources[0x10]	286	1			T1	1		T4	2		T126	1
valid_sources[0x11]	209	1			T4	1		T7	1		T8	1
valid_sources[0x12]	245	1			T1	2		T2	1		T4	1
valid_sources[0x13]	244	1			T1	1		T7	3		T18	2
valid_sources[0x14]	224	1			T1	1		T4	3		T7	2
valid_sources[0x15]	255	1			T4	1		T18	1		T87	1
valid_sources[0x16]	355	1			T4	2		T9	11		T126	1
valid_sources[0x17]	236	1			T1	1		T7	2		T60	1
valid_sources[0x18]	296	1			T1	1		T48	59		T50	1
valid_sources[0x19]	329	1			T32	2		T89	3		T72	1
valid_sources[0x1a]	203	1			T1	2		T4	2		T8	1
valid_sources[0x1b]	186	1			T1	4		T4	1		T9	1
valid_sources[0x1c]	287	1			T4	2		T8	1		T30	21
valid_sources[0x1d]	507	1			T7	1		T35	1		T12	2
valid_sources[0x1e]	227	1			T7	1		T18	1		T14	9
valid_sources[0x1f]	332	1			T2	1		T9	1		T29	67
valid_sources[0x20]	241	1			T4	2		T18	1		T87	1
valid_sources[0x21]	204	1			T4	2		T7	1		T126	1
valid_sources[0x22]	210	1			T4	2		T50	1		T93	1
valid_sources[0x23]	214	1			T1	1		T4	1		T7	3
valid_sources[0x24]	308	1			T4	2		T7	2		T126	1
valid_sources[0x25]	251	1			T1	4		T4	2		T90	1
valid_sources[0x26]	410	1			T4	4		T35	3		T126	1
valid_sources[0x27]	514	1			T1	2		T35	1		T29	5
valid_sources[0x28]	297	1			T18	2		T126	3		T50	1
valid_sources[0x29]	244	1			T4	1		T7	2		T87	1
valid_sources[0x2a]	218	1			T1	1		T4	1		T7	4
valid_sources[0x2b]	260	1			T4	3		T7	4		T90	1
valid_sources[0x2c]	313	1			T1	2		T4	2		T7	1
valid_sources[0x2d]	289	1			T7	3		T9	1		T33	1
valid_sources[0x2e]	262	1			T9	1		T126	3		T50	1
valid_sources[0x2f]	197	1			T1	3		T2	1		T4	3
valid_sources[0x30]	232	1			T4	1		T9	2		T56	1
valid_sources[0x31]	228	1			T4	1		T35	4		T126	1
valid_sources[0x32]	292	1			T7	1		T30	16		T126	2
valid_sources[0x33]	287	1			T7	2		T126	2		T93	1
valid_sources[0x34]	338	1			T60	1		T31	2		T90	1
valid_sources[0x35]	293	1			T1	1		T35	1		T126	1
valid_sources[0x36]	253	1			T4	2		T7	1		T10	1
valid_sources[0x37]	416	1			T4	1		T7	2		T51	1
valid_sources[0x38]	275	1			T1	1		T7	2		T35	3
valid_sources[0x39]	379	1			T1	2		T32	1		T72	5
valid_sources[0x3a]	349	1			T8	2		T18	5		T32	3
valid_sources[0x3b]	243	1			T7	1		T32	1		T126	1
valid_sources[0x3c]	258	1			T4	3		T87	2		T90	1
valid_sources[0x3d]	248	1			T4	1		T10	3		T33	1
valid_sources[0x3e]	249	1			T4	1		T7	1		T90	1
valid_sources[0x3f]	244	1			T4	2		T7	2		T36	1
valid_sources[0x40]	253	1			T4	2		T126	1		T91	2
valid_sources[0x41]	198	1			T1	2		T4	3		T18	2
valid_sources[0x42]	324	1			T4	2		T60	1		T126	2
valid_sources[0x43]	215	1			T1	2		T2	1		T10	1
valid_sources[0x44]	243	1			T4	3		T7	1		T29	5
valid_sources[0x45]	261	1			T2	1		T87	1		T33	1
valid_sources[0x46]	220	1			T1	1		T4	1		T7	1
valid_sources[0x47]	221	1			T1	1		T2	1		T7	1
valid_sources[0x48]	583	1			T1	2		T4	1		T60	1
valid_sources[0x49]	230	1			T7	2		T34	1		T208	3
valid_sources[0x4a]	500	1			T2	1		T4	6		T7	1
valid_sources[0x4b]	214	1			T1	2		T4	1		T7	4
valid_sources[0x4c]	476	1			T1	1		T4	1		T59	11
valid_sources[0x4d]	234	1			T4	2		T35	4		T88	4
valid_sources[0x4e]	291	1			T1	1		T4	1		T9	1
valid_sources[0x4f]	493	1			T4	1		T29	20		T126	1
valid_sources[0x50]	218	1			T1	1		T7	1		T134	1
valid_sources[0x51]	243	1			T1	1		T4	1		T7	1
valid_sources[0x52]	338	1			T1	2		T12	1		T207	2
valid_sources[0x53]	230	1			T1	1		T90	1		T207	1
valid_sources[0x54]	238	1			T1	4		T7	1		T35	1
valid_sources[0x55]	219	1			T1	3		T7	4		T60	1
valid_sources[0x56]	265	1			T2	4		T3	1		T4	1
valid_sources[0x57]	224	1			T4	2		T6	2		T7	3
valid_sources[0x58]	251	1			T1	2		T4	1		T18	2
valid_sources[0x59]	188	1			T4	1		T7	1		T95	2
valid_sources[0x5a]	365	1			T1	1		T7	5		T18	1
valid_sources[0x5b]	226	1			T1	1		T126	2		T90	1
valid_sources[0x5c]	235	1			T1	2		T4	1		T8	1
valid_sources[0x5d]	251	1			T4	1		T126	1		T72	1
valid_sources[0x5e]	273	1			T1	4		T7	1		T59	12
valid_sources[0x5f]	248	1			T1	1		T4	5		T60	1
valid_sources[0x60]	381	1			T18	2		T126	1		T95	4
valid_sources[0x61]	395	1			T1	2		T7	1		T12	8
valid_sources[0x62]	233	1			T4	1		T8	1		T126	1
valid_sources[0x63]	315	1			T4	1		T6	2		T10	1
valid_sources[0x64]	165	1			T4	2		T126	1		T90	1
valid_sources[0x65]	299	1			T4	1		T7	4		T60	1
valid_sources[0x66]	193	1			T1	1		T4	1		T7	1
valid_sources[0x67]	225	1			T4	1		T50	1		T207	1
valid_sources[0x68]	208	1			T1	4		T4	1		T7	1
valid_sources[0x69]	220	1			T1	3		T4	4		T6	1
valid_sources[0x6a]	222	1			T1	2		T4	3		T90	1
valid_sources[0x6b]	322	1			T7	2		T18	3		T26	1
valid_sources[0x6c]	258	1			T4	1		T6	4		T9	4
valid_sources[0x6d]	257	1			T7	1		T60	1		T29	5
valid_sources[0x6e]	229	1			T1	3		T10	1		T50	2
valid_sources[0x6f]	272	1			T1	2		T4	1		T7	1
valid_sources[0x70]	211	1			T1	2		T4	2		T7	1
valid_sources[0x71]	296	1			T4	1		T7	2		T60	1
valid_sources[0x72]	230	1			T1	1		T4	1		T10	1
valid_sources[0x73]	192	1			T4	2		T126	1		T33	3
valid_sources[0x74]	266	1			T4	2		T9	1		T33	1
valid_sources[0x75]	297	1			T1	1		T7	1		T34	6
valid_sources[0x76]	348	1			T4	2		T8	1		T33	2
valid_sources[0x77]	181	1			T1	2		T93	1		T95	1
valid_sources[0x78]	227	1			T4	5		T6	1		T126	1
valid_sources[0x79]	221	1			T90	1		T50	2		T27	2
valid_sources[0x7a]	255	1			T1	1		T4	3		T91	1
valid_sources[0x7b]	237	1			T1	1		T7	1		T72	1
valid_sources[0x7c]	274	1			T4	1		T7	4		T9	5
valid_sources[0x7d]	231	1			T1	10		T4	1		T7	1
valid_sources[0x7e]	228	1			T1	3		T4	2		T26	1
valid_sources[0x7f]	307	1			T4	2		T7	3		T126	1
valid_sources[0x80]	207	1			T1	1		T18	1		T72	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

14661

1

T1

49

T2

4

T4

127

values[0x0]

all_enables

biggest_size

8327

1

T1

25

T4

6

T5

1

values[0x1]

all_enables

biggest_size

6093

1

T1

10

T4

2

T6

1