Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2813176	11956	0	0
intr_enable_rd_A	2813176	2432	0	0
reset_en_rd_A	2813176	963	0	0
reset_en_regwen_rd_A	2813176	878	0	0
wake_info_capture_dis_rd_A	2813176	864	0	0
wakeup_en_rd_A	2813176	1525	0	0
wakeup_en_regwen_rd_A	2813176	891	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2813176	11956	0	0
T22	10138	873	0	0
T23	1246	60	0	0
T24	2422	58	0	0
T61	8742	13	0	0
T62	9242	7	0	0
T63	4692	944	0	0
T65	14871	8	0	0
T66	3951	261	0	0
T73	6171	425	0	0
T99	2373	89	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2813176	2432	0	0
T29	2378	0	0	0
T30	2177	0	0	0
T34	1317	0	0	0
T40	0	2	0	0
T46	0	16	0	0
T48	3474	0	0	0
T49	8135	0	0	0
T53	15844	0	0	0
T71	3755	86	0	0
T87	2753	0	0	0
T88	908	0	0	0
T95	0	44	0	0
T96	0	12	0	0
T121	0	27	0	0
T122	0	73	0	0
T123	0	6	0	0
T124	0	13	0	0
T125	0	34	0	0
T126	1824	0	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2813176	963	0	0
T61	8742	58	0	0
T62	9242	47	0	0
T65	14871	117	0	0
T66	3951	2	0	0
T81	2684	14	0	0
T82	4449	2	0	0
T105	1868	6	0	0
T116	2194	19	0	0
T117	1489	10	0	0
T118	2262	9	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2813176	878	0	0
T61	8742	53	0	0
T62	9242	27	0	0
T65	14871	59	0	0
T66	3951	5	0	0
T73	6171	7	0	0
T81	2684	3	0	0
T82	4449	12	0	0
T105	1868	1	0	0
T116	2194	14	0	0
T117	1489	5	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2813176	864	0	0
T61	8742	38	0	0
T62	9242	33	0	0
T65	14871	61	0	0
T66	3951	4	0	0
T73	6171	9	0	0
T81	2684	10	0	0
T105	1868	3	0	0
T116	2194	10	0	0
T117	1489	6	0	0
T118	2262	18	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2813176	1525	0	0
T61	8742	189	0	0
T62	9242	129	0	0
T65	14871	275	0	0
T73	6171	9	0	0
T81	2684	12	0	0
T82	4449	17	0	0
T113	27080	247	0	0
T116	2194	26	0	0
T117	1489	24	0	0
T118	2262	25	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2813176	891	0	0
T61	8742	52	0	0
T62	9242	47	0	0
T65	14871	83	0	0
T66	3951	5	0	0
T81	2684	3	0	0
T82	4449	23	0	0
T105	1868	2	0	0
T113	27080	211	0	0
T116	2194	9	0	0
T117	1489	4	0	0