Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	6730194	9523	0	0
StatusRise_A	6730194	12990	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6730194	9523	0	0
T1	4014	47	0	0
T2	8106	3	0	0
T3	44745	3	0	0
T4	19914	54	0	0
T5	44823	3	0	0
T6	7326	6	0	0
T7	14142	0	0	0
T8	8856	12	0	0
T9	7776	18	0	0
T10	4821	18	0	0
T11	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6730194	12990	0	0
T1	4014	49	0	0
T2	8106	6	0	0
T3	44745	6	0	0
T4	19914	60	0	0
T5	44823	6	0	0
T6	7326	9	0	0
T7	14142	3	0	0
T8	8856	15	0	0
T9	7776	20	0	0
T10	4821	21	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	2243398	3212	0	0
StatusRise_A	2243398	4378	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2243398	3212	0	0
T1	1338	16	0	0
T2	2702	1	0	0
T3	14915	1	0	0
T4	6638	18	0	0
T5	14941	1	0	0
T6	2442	2	0	0
T7	4714	0	0	0
T8	2952	4	0	0
T9	2592	6	0	0
T10	1607	6	0	0
T11	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2243398	4378	0	0
T1	1338	17	0	0
T2	2702	2	0	0
T3	14915	2	0	0
T4	6638	20	0	0
T5	14941	2	0	0
T6	2442	3	0	0
T7	4714	1	0	0
T8	2952	5	0	0
T9	2592	7	0	0
T10	1607	7	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	2243398	3212	0	0
StatusRise_A	2243398	4378	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2243398	3212	0	0
T1	1338	16	0	0
T2	2702	1	0	0
T3	14915	1	0	0
T4	6638	18	0	0
T5	14941	1	0	0
T6	2442	2	0	0
T7	4714	0	0	0
T8	2952	4	0	0
T9	2592	6	0	0
T10	1607	6	0	0
T11	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2243398	4378	0	0
T1	1338	17	0	0
T2	2702	2	0	0
T3	14915	2	0	0
T4	6638	20	0	0
T5	14941	2	0	0
T6	2442	3	0	0
T7	4714	1	0	0
T8	2952	5	0	0
T9	2592	7	0	0
T10	1607	7	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	2243398	3099	0	0
StatusRise_A	2243398	4234	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2243398	3099	0	0
T1	1338	15	0	0
T2	2702	1	0	0
T3	14915	1	0	0
T4	6638	18	0	0
T5	14941	1	0	0
T6	2442	2	0	0
T7	4714	0	0	0
T8	2952	4	0	0
T9	2592	6	0	0
T10	1607	6	0	0
T11	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2243398	4234	0	0
T1	1338	15	0	0
T2	2702	2	0	0
T3	14915	2	0	0
T4	6638	20	0	0
T5	14941	2	0	0
T6	2442	3	0	0
T7	4714	1	0	0
T8	2952	5	0	0
T9	2592	6	0	0
T10	1607	7	0	0