Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	2243740	5643	0	0
EscTimeoutStoppedByClReset_A	2243398	71887	0	0
EscTimeoutTriggersReset_A	335057	320	0	0
RomAllowActiveState_A	2243398	3999	0	0
RomAllowCheckGoodState_A	2243398	4049	0	0
RomBlockActiveState_A	2243398	33310	0	0
RomBlockCheckGoodState_A	2243398	22924	0	0
RomIntgChkDisFalse_A	2243398	2059445	0	0
RomIntgChkDisTrue_A	2243398	28405	0	0
RstreqChkEsctimeout_A	2243398	1052	0	0
RstreqChkFsmterm_A	2243398	140	0	0
RstreqChkGlbesc_A	2243398	1052	0	0
RstreqChkMainpd_A	2243398	58423	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2243740	5643	0	0
T3	14916	9	0	0
T4	6639	0	0	0
T5	14942	56	0	0
T6	2442	0	0	0
T7	4715	0	0	0
T8	2953	0	0	0
T9	2593	0	0	0
T10	1608	0	0	0
T11	15198	94	0	0
T13	1709	0	0	0
T52	0	56	0	0
T53	0	271	0	0
T127	0	1	0	0
T128	0	41	0	0
T129	0	19	0	0
T130	0	13	0	0
T131	0	175	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2243398	71887	0	0
T2	2702	13	0	0
T3	14915	13	0	0
T4	6638	397	0	0
T5	14941	12	0	0
T6	2442	11	0	0
T7	4714	25	0	0
T8	2952	65	0	0
T9	2592	0	0	0
T10	1607	116	0	0
T11	0	12	0	0
T13	1708	19	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335057	320	0	0
T3	2602	3	0	0
T4	697	0	0	0
T5	671	3	0	0
T6	215	0	0	0
T7	366	0	0	0
T8	291	0	0	0
T9	201	0	0	0
T10	483	0	0	0
T11	360	2	0	0
T13	638	0	0	0
T52	0	3	0	0
T53	0	3	0	0
T127	0	3	0	0
T128	0	3	0	0
T129	0	2	0	0
T132	0	4	0	0
T133	0	5	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2243398	3999	0	0
T1	1338	17	0	0
T2	2702	2	0	0
T3	14915	2	0	0
T4	6638	13	0	0
T5	14941	2	0	0
T6	2442	3	0	0
T7	4714	1	0	0
T8	2952	5	0	0
T9	2592	7	0	0
T10	1607	7	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2243398	4049	0	0
T1	1338	17	0	0
T2	2702	2	0	0
T3	14915	2	0	0
T4	6638	14	0	0
T5	14941	2	0	0
T6	2442	3	0	0
T7	4714	1	0	0
T8	2952	5	0	0
T9	2592	7	0	0
T10	1607	7	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2243398	33310	0	0
T12	4961	0	0	0
T29	2378	0	0	0
T31	1782	223	0	0
T32	5017	1312	0	0
T33	0	793	0	0
T34	1317	0	0	0
T36	0	602	0	0
T48	3474	0	0	0
T49	8135	0	0	0
T52	14949	0	0	0
T54	1298	0	0	0
T71	3755	0	0	0
T134	0	493	0	0
T135	0	143	0	0
T136	0	459	0	0
T137	0	151	0	0
T138	0	1153	0	0
T139	0	34	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2243398	22924	0	0
T12	4961	0	0	0
T27	0	69	0	0
T29	2378	0	0	0
T31	1782	45	0	0
T32	5017	570	0	0
T33	0	768	0	0
T34	1317	0	0	0
T36	0	329	0	0
T48	3474	0	0	0
T49	8135	0	0	0
T52	14949	0	0	0
T54	1298	0	0	0
T71	3755	0	0	0
T134	0	280	0	0
T135	0	74	0	0
T136	0	194	0	0
T137	0	56	0	0
T138	0	851	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2243398	2059445	0	0
T1	1338	1274	0	0
T2	2702	2645	0	0
T3	14915	14865	0	0
T4	6638	5606	0	0
T5	14941	14867	0	0
T6	2442	2358	0	0
T7	4714	4651	0	0
T8	2952	2539	0	0
T9	2592	2496	0	0
T10	1607	1529	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2243398	28405	0	0
T12	4961	0	0	0
T29	2378	0	0	0
T31	1782	765	0	0
T32	5017	398	0	0
T33	0	2112	0	0
T34	1317	0	0	0
T36	0	270	0	0
T48	3474	0	0	0
T49	8135	0	0	0
T52	14949	0	0	0
T54	1298	0	0	0
T71	3755	0	0	0
T134	0	1074	0	0
T135	0	565	0	0
T136	0	225	0	0
T137	0	49	0	0
T138	0	229	0	0
T139	0	698	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2243398	1052	0	0
T3	14915	1	0	0
T4	6638	7	0	0
T5	14941	1	0	0
T6	2442	0	0	0
T7	4714	0	0	0
T8	2952	0	0	0
T9	2592	0	0	0
T10	1607	4	0	0
T11	15198	1	0	0
T13	1708	5	0	0
T18	0	13	0	0
T51	0	4	0	0
T56	0	1	0	0
T57	0	4	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2243398	140	0	0
T19	14820	20	0	0
T20	0	40	0	0
T21	0	20	0	0
T37	0	20	0	0
T38	0	40	0	0
T39	2069	0	0	0
T40	1489	0	0	0
T41	1330	0	0	0
T42	4239	0	0	0
T43	2347	0	0	0
T44	7981	0	0	0
T45	14932	0	0	0
T46	3996	0	0	0
T47	2033	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2243398	1052	0	0
T3	14915	1	0	0
T4	6638	7	0	0
T5	14941	1	0	0
T6	2442	0	0	0
T7	4714	0	0	0
T8	2952	0	0	0
T9	2592	0	0	0
T10	1607	4	0	0
T11	15198	1	0	0
T13	1708	5	0	0
T18	0	13	0	0
T51	0	4	0	0
T56	0	1	0	0
T57	0	4	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2243398	58423	0	0
T4	6638	199	0	0
T5	14941	0	0	0
T6	2442	0	0	0
T7	4714	0	0	0
T8	2952	0	0	0
T9	2592	0	0	0
T10	1607	103	0	0
T11	15198	0	0	0
T13	1708	0	0	0
T15	0	11	0	0
T18	0	111	0	0
T25	0	5	0	0
T31	0	72	0	0
T32	0	1672	0	0
T33	0	707	0	0
T48	0	100	0	0
T49	0	159	0	0
T51	1630	0	0	0