Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	40144	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

31853

1

T1

6

T2

7

T3

26

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36433	1			T1	11		T2	9		T3	30
values[0x0]	17495	1			T1	7		T2	7		T3	11
values[0x1]	18069	1			T1	4		T2	4		T3	22

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	32109	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

39888

1

T1

9

T2

9

T3

33

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	262	1			T7	1		T47	7		T66	1
valid_sources[0x01]	205	1			T3	1		T7	3		T9	1
valid_sources[0x02]	231	1			T45	2		T66	1		T15	1
valid_sources[0x03]	311	1			T2	1		T10	1		T45	1
valid_sources[0x04]	178	1			T46	1		T35	2		T36	1
valid_sources[0x05]	213	1			T7	2		T46	1		T55	1
valid_sources[0x06]	204	1			T46	1		T66	3		T82	1
valid_sources[0x07]	215	1			T7	1		T14	1		T66	2
valid_sources[0x08]	268	1			T8	1		T46	1		T32	1
valid_sources[0x09]	164	1			T46	1		T66	1		T82	2
valid_sources[0x0a]	272	1			T66	1		T51	1		T82	1
valid_sources[0x0b]	242	1			T66	1		T15	1		T51	3
valid_sources[0x0c]	251	1			T7	2		T49	2		T118	2
valid_sources[0x0d]	496	1			T5	11		T7	1		T46	1
valid_sources[0x0e]	217	1			T3	2		T7	2		T44	3
valid_sources[0x0f]	337	1			T7	2		T9	3		T46	1
valid_sources[0x10]	443	1			T7	2		T118	1		T138	1
valid_sources[0x11]	185	1			T8	2		T9	1		T45	1
valid_sources[0x12]	317	1			T118	1		T52	1		T163	5
valid_sources[0x13]	239	1			T7	1		T66	2		T133	2
valid_sources[0x14]	315	1			T66	2		T51	1		T55	2
valid_sources[0x15]	210	1			T6	4		T7	1		T66	2
valid_sources[0x16]	322	1			T7	1		T134	1		T118	1
valid_sources[0x17]	263	1			T7	1		T47	1		T66	2
valid_sources[0x18]	264	1			T10	4		T45	2		T59	1
valid_sources[0x19]	275	1			T7	1		T46	1		T47	3
valid_sources[0x1a]	392	1			T9	1		T46	2		T66	2
valid_sources[0x1b]	347	1			T66	2		T55	1		T214	1
valid_sources[0x1c]	231	1			T45	2		T46	1		T215	9
valid_sources[0x1d]	252	1			T2	1		T7	1		T46	1
valid_sources[0x1e]	471	1			T3	2		T46	1		T66	1
valid_sources[0x1f]	517	1			T45	1		T48	255		T66	1
valid_sources[0x20]	265	1			T44	8		T66	1		T216	2
valid_sources[0x21]	281	1			T3	2		T45	2		T32	2
valid_sources[0x22]	203	1			T14	1		T66	5		T120	9
valid_sources[0x23]	322	1			T7	1		T45	3		T29	34
valid_sources[0x24]	296	1			T3	1		T46	1		T66	1
valid_sources[0x25]	296	1			T6	10		T66	3		T153	1
valid_sources[0x26]	212	1			T7	1		T46	3		T66	2
valid_sources[0x27]	273	1			T9	1		T47	1		T49	2
valid_sources[0x28]	247	1			T3	1		T8	4		T46	2
valid_sources[0x29]	313	1			T7	1		T66	2		T40	1
valid_sources[0x2a]	318	1			T216	2		T118	2		T188	2
valid_sources[0x2b]	288	1			T7	1		T66	1		T217	1
valid_sources[0x2c]	369	1			T66	2		T15	2		T118	1
valid_sources[0x2d]	348	1			T6	3		T7	1		T46	1
valid_sources[0x2e]	227	1			T81	2		T216	5		T118	1
valid_sources[0x2f]	325	1			T7	1		T66	2		T15	2
valid_sources[0x30]	320	1			T7	1		T46	1		T66	1
valid_sources[0x31]	171	1			T66	1		T118	2		T87	3
valid_sources[0x32]	339	1			T15	1		T218	1		T85	8
valid_sources[0x33]	187	1			T7	1		T66	4		T49	2
valid_sources[0x34]	230	1			T7	1		T46	1		T66	2
valid_sources[0x35]	232	1			T7	1		T66	1		T15	1
valid_sources[0x36]	222	1			T6	2		T9	1		T46	1
valid_sources[0x37]	209	1			T2	1		T7	1		T66	1
valid_sources[0x38]	242	1			T3	1		T44	2		T219	1
valid_sources[0x39]	299	1			T46	1		T14	1		T32	6
valid_sources[0x3a]	209	1			T9	2		T46	1		T136	5
valid_sources[0x3b]	303	1			T7	1		T10	1		T46	1
valid_sources[0x3c]	261	1			T7	1		T66	1		T15	1
valid_sources[0x3d]	207	1			T2	1		T7	1		T46	2
valid_sources[0x3e]	340	1			T7	1		T66	2		T220	1
valid_sources[0x3f]	265	1			T2	1		T7	2		T46	1
valid_sources[0x40]	151	1			T47	2		T49	1		T134	1
valid_sources[0x41]	231	1			T118	2		T137	1		T52	1
valid_sources[0x42]	379	1			T7	1		T29	21		T137	1
valid_sources[0x43]	268	1			T3	4		T45	1		T46	1
valid_sources[0x44]	205	1			T45	1		T46	1		T66	2
valid_sources[0x45]	334	1			T3	1		T7	2		T45	1
valid_sources[0x46]	647	1			T7	1		T8	1		T46	1
valid_sources[0x47]	188	1			T66	2		T174	1		T36	1
valid_sources[0x48]	192	1			T3	2		T46	1		T47	1
valid_sources[0x49]	307	1			T45	3		T125	1		T52	1
valid_sources[0x4a]	240	1			T7	1		T81	7		T59	1
valid_sources[0x4b]	511	1			T7	1		T46	1		T66	4
valid_sources[0x4c]	226	1			T46	1		T51	1		T135	1
valid_sources[0x4d]	341	1			T46	1		T66	3		T55	1
valid_sources[0x4e]	321	1			T7	1		T10	1		T66	2
valid_sources[0x4f]	194	1			T7	2		T46	1		T32	1
valid_sources[0x50]	265	1			T44	20		T46	1		T47	2
valid_sources[0x51]	286	1			T66	1		T221	1		T40	1
valid_sources[0x52]	235	1			T46	1		T66	1		T49	1
valid_sources[0x53]	205	1			T7	1		T66	2		T126	1
valid_sources[0x54]	220	1			T10	1		T46	1		T31	27
valid_sources[0x55]	419	1			T59	1		T163	2		T222	1
valid_sources[0x56]	242	1			T46	2		T51	1		T134	1
valid_sources[0x57]	608	1			T66	1		T118	1		T222	1
valid_sources[0x58]	283	1			T3	1		T22	1		T66	1
valid_sources[0x59]	451	1			T3	1		T6	1		T66	2
valid_sources[0x5a]	449	1			T7	1		T45	1		T66	1
valid_sources[0x5b]	208	1			T30	25		T47	2		T66	1
valid_sources[0x5c]	1001	1			T45	5		T47	3		T66	2
valid_sources[0x5d]	203	1			T5	13		T7	3		T10	1
valid_sources[0x5e]	241	1			T49	2		T223	1		T172	2
valid_sources[0x5f]	244	1			T3	1		T5	19		T6	6
valid_sources[0x60]	457	1			T66	2		T16	5		T137	1
valid_sources[0x61]	256	1			T2	1		T3	1		T8	2
valid_sources[0x62]	191	1			T45	1		T46	1		T66	1
valid_sources[0x63]	248	1			T7	1		T16	5		T87	2
valid_sources[0x64]	476	1			T7	2		T8	1		T59	1
valid_sources[0x65]	204	1			T47	7		T81	13		T66	2
valid_sources[0x66]	653	1			T7	2		T66	1		T135	1
valid_sources[0x67]	253	1			T46	2		T66	1		T51	4
valid_sources[0x68]	219	1			T8	1		T46	1		T222	1
valid_sources[0x69]	313	1			T9	2		T66	1		T51	1
valid_sources[0x6a]	286	1			T4	1		T66	1		T130	1
valid_sources[0x6b]	403	1			T45	2		T66	2		T49	1
valid_sources[0x6c]	170	1			T66	1		T29	6		T55	2
valid_sources[0x6d]	301	1			T44	13		T66	1		T134	1
valid_sources[0x6e]	404	1			T44	9		T66	2		T49	1
valid_sources[0x6f]	388	1			T44	5		T66	2		T82	2
valid_sources[0x70]	284	1			T3	3		T14	1		T94	1
valid_sources[0x71]	207	1			T3	1		T46	3		T49	1
valid_sources[0x72]	164	1			T7	1		T66	1		T133	1
valid_sources[0x73]	264	1			T7	2		T46	1		T66	2
valid_sources[0x74]	393	1			T7	1		T45	1		T46	1
valid_sources[0x75]	281	1			T10	2		T46	1		T66	3
valid_sources[0x76]	197	1			T5	12		T118	3		T58	1
valid_sources[0x77]	217	1			T7	1		T45	1		T46	2
valid_sources[0x78]	322	1			T3	1		T7	2		T46	1
valid_sources[0x79]	228	1			T46	1		T32	1		T118	1
valid_sources[0x7a]	186	1			T81	3		T66	1		T59	1
valid_sources[0x7b]	257	1			T5	13		T7	2		T66	2
valid_sources[0x7c]	266	1			T2	3		T7	2		T9	1
valid_sources[0x7d]	192	1			T5	12		T7	1		T46	2
valid_sources[0x7e]	383	1			T3	3		T32	1		T66	2
valid_sources[0x7f]	307	1			T7	1		T8	1		T66	1
valid_sources[0x80]	267	1			T3	3		T7	1		T9	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

15491

1

T1

3

T2

3

T3

18

values[0x0]

all_enables

biggest_size

9322

1

T1

3

T2

3

T3

5

values[0x1]

all_enables

biggest_size

7040

1

T2

1

T3

3

T5

9