Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2886428	13546	0	0
intr_enable_rd_A	2886428	2908	0	0
reset_en_rd_A	2886428	1250	0	0
reset_en_regwen_rd_A	2886428	1309	0	0
wake_info_capture_dis_rd_A	2886428	1313	0	0
wakeup_en_rd_A	2886428	1973	0	0
wakeup_en_regwen_rd_A	2886428	1336	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2886428	13546	0	0
T23	7637	5	0	0
T24	11749	1051	0	0
T25	9684	9	0	0
T60	2071	273	0	0
T61	2738	246	0	0
T62	11497	9	0	0
T69	3261	295	0	0
T73	7930	3	0	0
T91	8855	6	0	0
T92	4900	111	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2886428	2908	0	0
T1	1154	5	0	0
T2	1438	0	0	0
T3	3134	0	0	0
T4	2558	0	0	0
T5	2146	0	0	0
T6	1833	0	0	0
T7	3117	0	0	0
T8	1275	0	0	0
T9	2177	0	0	0
T10	1838	0	0	0
T14	0	4	0	0
T38	0	8	0	0
T82	0	4	0	0
T85	0	6	0	0
T87	0	14	0	0
T88	0	12	0	0
T118	0	34	0	0
T119	0	15	0	0
T120	0	4	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2886428	1250	0	0
T62	11497	102	0	0
T63	1938	16	0	0
T65	3706	21	0	0
T93	5518	6	0	0
T99	1105	6	0	0
T107	15849	205	0	0
T112	3167	34	0	0
T113	1659	17	0	0
T121	4990	123	0	0
T122	7318	16	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2886428	1309	0	0
T62	11497	80	0	0
T63	1938	18	0	0
T65	3706	49	0	0
T93	5518	5	0	0
T99	1105	4	0	0
T101	1718	1	0	0
T103	1522	8	0	0
T107	15849	226	0	0
T121	4990	123	0	0
T123	1853	1	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2886428	1313	0	0
T62	11497	81	0	0
T63	1938	48	0	0
T65	3706	58	0	0
T99	1105	8	0	0
T101	1718	2	0	0
T103	1522	11	0	0
T107	15849	177	0	0
T121	4990	109	0	0
T122	7318	20	0	0
T123	1853	13	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2886428	1973	0	0
T62	11497	304	0	0
T65	3706	19	0	0
T93	5518	6	0	0
T99	1105	7	0	0
T103	1522	31	0	0
T107	15849	255	0	0
T112	3167	9	0	0
T121	4990	93	0	0
T122	7318	25	0	0
T123	1853	9	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2886428	1336	0	0
T62	11497	70	0	0
T63	1938	64	0	0
T65	3706	42	0	0
T93	5518	5	0	0
T99	1105	7	0	0
T101	1718	3	0	0
T103	1522	3	0	0
T107	15849	240	0	0
T121	4990	77	0	0
T123	1853	8	0	0