Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	6868341	9098	0	0
StatusRise_A	6868341	12674	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6868341	9098	0	0
T1	3462	6	0	0
T2	4314	6	0	0
T3	9402	54	0	0
T4	7674	0	0	0
T5	6438	44	0	0
T6	5499	6	0	0
T7	9351	54	0	0
T8	3825	15	0	0
T9	6531	12	0	0
T10	5514	6	0	0
T44	0	78	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6868341	12674	0	0
T1	3462	9	0	0
T2	4314	9	0	0
T3	9402	60	0	0
T4	7674	9	0	0
T5	6438	47	0	0
T6	5499	9	0	0
T7	9351	60	0	0
T8	3825	18	0	0
T9	6531	15	0	0
T10	5514	9	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	2289447	3064	0	0
StatusRise_A	2289447	4270	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2289447	3064	0	0
T1	1154	2	0	0
T2	1438	2	0	0
T3	3134	18	0	0
T4	2558	0	0	0
T5	2146	15	0	0
T6	1833	2	0	0
T7	3117	18	0	0
T8	1275	5	0	0
T9	2177	4	0	0
T10	1838	2	0	0
T44	0	26	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2289447	4270	0	0
T1	1154	3	0	0
T2	1438	3	0	0
T3	3134	20	0	0
T4	2558	3	0	0
T5	2146	16	0	0
T6	1833	3	0	0
T7	3117	20	0	0
T8	1275	6	0	0
T9	2177	5	0	0
T10	1838	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	2289447	3064	0	0
StatusRise_A	2289447	4270	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2289447	3064	0	0
T1	1154	2	0	0
T2	1438	2	0	0
T3	3134	18	0	0
T4	2558	0	0	0
T5	2146	15	0	0
T6	1833	2	0	0
T7	3117	18	0	0
T8	1275	5	0	0
T9	2177	4	0	0
T10	1838	2	0	0
T44	0	26	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2289447	4270	0	0
T1	1154	3	0	0
T2	1438	3	0	0
T3	3134	20	0	0
T4	2558	3	0	0
T5	2146	16	0	0
T6	1833	3	0	0
T7	3117	20	0	0
T8	1275	6	0	0
T9	2177	5	0	0
T10	1838	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	2289447	2970	0	0
StatusRise_A	2289447	4134	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2289447	2970	0	0
T1	1154	2	0	0
T2	1438	2	0	0
T3	3134	18	0	0
T4	2558	0	0	0
T5	2146	14	0	0
T6	1833	2	0	0
T7	3117	18	0	0
T8	1275	5	0	0
T9	2177	4	0	0
T10	1838	2	0	0
T44	0	26	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2289447	4134	0	0
T1	1154	3	0	0
T2	1438	3	0	0
T3	3134	20	0	0
T4	2558	3	0	0
T5	2146	15	0	0
T6	1833	3	0	0
T7	3117	20	0	0
T8	1275	6	0	0
T9	2177	5	0	0
T10	1838	3	0	0