Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	2289821	4570	0	0
EscTimeoutStoppedByClReset_A	2289447	82912	0	0
EscTimeoutTriggersReset_A	320173	325	0	0
RomAllowActiveState_A	2289447	3900	0	0
RomAllowCheckGoodState_A	2289447	3950	0	0
RomBlockActiveState_A	2289447	27726	0	0
RomBlockCheckGoodState_A	2289447	18837	0	0
RomIntgChkDisFalse_A	2289447	2097978	0	0
RomIntgChkDisTrue_A	2289447	32245	0	0
RstreqChkEsctimeout_A	2289447	1003	0	0
RstreqChkFsmterm_A	2289447	160	0	0
RstreqChkGlbesc_A	2289447	1003	0	0
RstreqChkMainpd_A	2289447	50452	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2289821	4570	0	0
T12	793	6	0	0
T13	15145	28	0	0
T22	2297	0	0	0
T32	2866	0	0	0
T48	6866	0	0	0
T49	2808	0	0	0
T66	7169	0	0	0
T81	1712	0	0	0
T94	1055	0	0	0
T124	2285	33	0	0
T125	0	259	0	0
T126	0	155	0	0
T127	0	122	0	0
T128	0	117	0	0
T129	0	56	0	0
T130	0	7	0	0
T131	0	8	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2289447	82912	0	0
T1	1154	21	0	0
T2	1438	11	0	0
T3	3134	325	0	0
T4	2558	100	0	0
T5	2146	0	0	0
T6	1833	11	0	0
T7	3117	363	0	0
T8	1275	103	0	0
T9	2177	84	0	0
T10	1838	12	0	0
T44	0	1012	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320173	325	0	0
T11	216	2	0	0
T12	262	5	0	0
T13	712	2	0	0
T14	347	0	0	0
T22	0	2	0	0
T30	651	0	0	0
T31	545	0	0	0
T45	1115	0	0	0
T46	1061	0	0	0
T47	661	0	0	0
T50	655	0	0	0
T124	0	3	0	0
T125	0	3	0	0
T126	0	2	0	0
T127	0	3	0	0
T128	0	2	0	0
T132	0	5	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2289447	3900	0	0
T1	1154	3	0	0
T2	1438	3	0	0
T3	3134	13	0	0
T4	2558	3	0	0
T5	2146	16	0	0
T6	1833	3	0	0
T7	3117	13	0	0
T8	1275	6	0	0
T9	2177	5	0	0
T10	1838	3	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2289447	3950	0	0
T1	1154	3	0	0
T2	1438	3	0	0
T3	3134	14	0	0
T4	2558	3	0	0
T5	2146	16	0	0
T6	1833	3	0	0
T7	3117	14	0	0
T8	1275	6	0	0
T9	2177	5	0	0
T10	1838	3	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2289447	27726	0	0
T12	792	0	0	0
T13	15145	0	0	0
T14	1181	0	0	0
T22	2297	0	0	0
T30	1146	122	0	0
T31	1595	329	0	0
T32	0	552	0	0
T46	3127	0	0	0
T47	4497	0	0	0
T48	6866	0	0	0
T59	0	174	0	0
T94	1054	0	0	0
T133	0	265	0	0
T134	0	90	0	0
T135	0	447	0	0
T136	0	439	0	0
T137	0	214	0	0
T138	0	246	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2289447	18837	0	0
T12	792	0	0	0
T13	15145	0	0	0
T22	2297	0	0	0
T31	1595	74	0	0
T32	2865	335	0	0
T48	6866	0	0	0
T59	0	13	0	0
T66	7168	0	0	0
T81	1711	0	0	0
T94	1054	0	0	0
T124	2284	0	0	0
T133	0	66	0	0
T134	0	52	0	0
T135	0	373	0	0
T136	0	388	0	0
T137	0	64	0	0
T138	0	68	0	0
T139	0	676	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2289447	2097978	0	0
T1	1154	1078	0	0
T2	1438	1341	0	0
T3	3134	2172	0	0
T4	2558	2363	0	0
T5	2146	2068	0	0
T6	1833	1751	0	0
T7	3117	2138	0	0
T8	1275	1197	0	0
T9	2177	1808	0	0
T10	1838	1749	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2289447	32245	0	0
T12	792	0	0	0
T13	15145	0	0	0
T14	1181	0	0	0
T22	2297	0	0	0
T30	1146	447	0	0
T31	1595	484	0	0
T32	0	953	0	0
T46	3127	0	0	0
T47	4497	0	0	0
T48	6866	0	0	0
T59	0	846	0	0
T94	1054	0	0	0
T133	0	69	0	0
T134	0	190	0	0
T135	0	1170	0	0
T136	0	215	0	0
T137	0	786	0	0
T138	0	54	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2289447	1003	0	0
T3	3134	2	0	0
T4	2558	0	0	0
T5	2146	0	0	0
T6	1833	0	0	0
T7	3117	7	0	0
T8	1275	1	0	0
T9	2177	0	0	0
T10	1838	0	0	0
T11	0	1	0	0
T26	2770	0	0	0
T30	0	2	0	0
T31	0	2	0	0
T44	7035	9	0	0
T45	0	4	0	0
T46	0	6	0	0
T47	0	11	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2289447	160	0	0
T19	21257	20	0	0
T20	0	20	0	0
T21	0	40	0	0
T33	0	40	0	0
T34	0	40	0	0
T35	3754	0	0	0
T36	5192	0	0	0
T37	1675	0	0	0
T38	1212	0	0	0
T39	1212	0	0	0
T40	1761	0	0	0
T41	2045	0	0	0
T42	2206	0	0	0
T43	1544	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2289447	1003	0	0
T3	3134	2	0	0
T4	2558	0	0	0
T5	2146	0	0	0
T6	1833	0	0	0
T7	3117	7	0	0
T8	1275	1	0	0
T9	2177	0	0	0
T10	1838	0	0	0
T11	0	1	0	0
T26	2770	0	0	0
T30	0	2	0	0
T31	0	2	0	0
T44	7035	9	0	0
T45	0	4	0	0
T46	0	6	0	0
T47	0	11	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2289447	50452	0	0
T3	3134	139	0	0
T4	2558	12	0	0
T5	2146	0	0	0
T6	1833	0	0	0
T7	3117	133	0	0
T8	1275	58	0	0
T9	2177	0	0	0
T10	1838	0	0	0
T26	2770	5	0	0
T30	0	62	0	0
T44	7035	1015	0	0
T45	0	120	0	0
T46	0	134	0	0
T47	0	910	0	0