Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	40460	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

29840

1

T1

120

T2

5

T3

20

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	35459	1			T1	233		T2	5		T3	32
values[0x0]	17224	1			T1	16		T2	12		T3	11
values[0x1]	17617	1			T1	17		T2	7		T3	11

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	32241	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

38059

1

T1

143

T2

7

T3

24

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	219	1			T3	3		T43	1		T45	1
valid_sources[0x01]	358	1			T9	1		T43	1		T76	1
valid_sources[0x02]	231	1			T1	2		T45	1		T194	2
valid_sources[0x03]	279	1			T42	1		T20	1		T27	4
valid_sources[0x04]	230	1			T2	1		T3	2		T10	1
valid_sources[0x05]	223	1			T1	1		T10	3		T13	1
valid_sources[0x06]	456	1			T10	1		T13	1		T14	1
valid_sources[0x07]	215	1			T16	1		T216	3		T217	5
valid_sources[0x08]	273	1			T1	3		T10	1		T78	8
valid_sources[0x09]	254	1			T1	1		T10	1		T78	2
valid_sources[0x0a]	354	1			T1	1		T3	1		T14	3
valid_sources[0x0b]	290	1			T2	1		T52	1		T45	1
valid_sources[0x0c]	246	1			T45	1		T54	9		T216	2
valid_sources[0x0d]	246	1			T3	1		T45	3		T76	7
valid_sources[0x0e]	232	1			T10	1		T53	1		T54	2
valid_sources[0x0f]	242	1			T1	1		T10	1		T14	1
valid_sources[0x10]	296	1			T13	1		T14	1		T45	3
valid_sources[0x11]	248	1			T1	3		T16	1		T76	8
valid_sources[0x12]	307	1			T1	2		T15	21		T131	4
valid_sources[0x13]	235	1			T10	1		T48	1		T79	2
valid_sources[0x14]	279	1			T1	2		T13	1		T45	3
valid_sources[0x15]	298	1			T3	2		T10	1		T13	1
valid_sources[0x16]	201	1			T10	2		T43	1		T45	1
valid_sources[0x17]	313	1			T1	6		T16	2		T17	5
valid_sources[0x18]	261	1			T10	1		T45	2		T53	1
valid_sources[0x19]	299	1			T1	2		T45	3		T53	1
valid_sources[0x1a]	347	1			T3	1		T18	1		T45	2
valid_sources[0x1b]	306	1			T1	2		T29	3		T51	2
valid_sources[0x1c]	229	1			T45	1		T114	1		T86	7
valid_sources[0x1d]	300	1			T1	1		T127	1		T45	1
valid_sources[0x1e]	312	1			T1	1		T10	1		T45	2
valid_sources[0x1f]	286	1			T82	1		T111	1		T164	3
valid_sources[0x20]	236	1			T17	5		T76	8		T53	1
valid_sources[0x21]	253	1			T1	1		T45	1		T64	1
valid_sources[0x22]	212	1			T13	1		T42	1		T76	1
valid_sources[0x23]	175	1			T1	1		T13	1		T16	1
valid_sources[0x24]	288	1			T1	2		T14	1		T45	4
valid_sources[0x25]	208	1			T9	1		T10	1		T42	1
valid_sources[0x26]	285	1			T1	3		T45	3		T15	20
valid_sources[0x27]	257	1			T14	1		T45	2		T218	3
valid_sources[0x28]	257	1			T45	1		T64	3		T55	2
valid_sources[0x29]	246	1			T43	1		T54	4		T175	1
valid_sources[0x2a]	299	1			T1	3		T14	4		T45	1
valid_sources[0x2b]	360	1			T3	1		T9	3		T14	6
valid_sources[0x2c]	295	1			T1	1		T3	1		T45	4
valid_sources[0x2d]	229	1			T1	1		T45	1		T53	1
valid_sources[0x2e]	251	1			T1	1		T10	1		T16	2
valid_sources[0x2f]	281	1			T1	1		T78	2		T45	2
valid_sources[0x30]	229	1			T1	5		T131	1		T53	1
valid_sources[0x31]	226	1			T14	1		T45	1		T54	1
valid_sources[0x32]	314	1			T13	1		T78	2		T45	2
valid_sources[0x33]	244	1			T10	1		T45	2		T175	1
valid_sources[0x34]	286	1			T1	3		T3	1		T52	1
valid_sources[0x35]	200	1			T45	1		T76	1		T216	5
valid_sources[0x36]	257	1			T1	1		T14	3		T45	2
valid_sources[0x37]	210	1			T1	1		T12	1		T51	9
valid_sources[0x38]	204	1			T1	3		T3	1		T45	1
valid_sources[0x39]	234	1			T10	1		T14	3		T45	1
valid_sources[0x3a]	333	1			T45	3		T219	6		T176	2
valid_sources[0x3b]	235	1			T1	3		T41	1		T45	1
valid_sources[0x3c]	269	1			T43	1		T78	1		T27	1
valid_sources[0x3d]	279	1			T1	2		T64	1		T27	1
valid_sources[0x3e]	384	1			T1	1		T10	1		T41	3
valid_sources[0x3f]	202	1			T1	3		T16	1		T217	1
valid_sources[0x40]	258	1			T1	3		T14	2		T45	2
valid_sources[0x41]	200	1			T1	2		T3	1		T29	4
valid_sources[0x42]	322	1			T1	1		T3	1		T41	14
valid_sources[0x43]	199	1			T3	2		T14	2		T220	1
valid_sources[0x44]	200	1			T1	1		T16	1		T45	1
valid_sources[0x45]	320	1			T16	1		T14	1		T45	1
valid_sources[0x46]	250	1			T10	2		T41	1		T45	2
valid_sources[0x47]	290	1			T41	5		T43	1		T76	4
valid_sources[0x48]	622	1			T1	1		T16	1		T42	1
valid_sources[0x49]	179	1			T1	5		T43	1		T78	1
valid_sources[0x4a]	209	1			T1	1		T3	3		T10	1
valid_sources[0x4b]	214	1			T1	2		T2	2		T41	2
valid_sources[0x4c]	272	1			T1	5		T10	1		T45	2
valid_sources[0x4d]	208	1			T1	4		T45	1		T54	3
valid_sources[0x4e]	388	1			T1	2		T2	1		T78	4
valid_sources[0x4f]	304	1			T3	1		T14	1		T51	1
valid_sources[0x50]	513	1			T10	3		T14	3		T45	2
valid_sources[0x51]	249	1			T1	1		T3	4		T41	7
valid_sources[0x52]	379	1			T1	2		T41	3		T45	2
valid_sources[0x53]	292	1			T1	3		T42	1		T51	9
valid_sources[0x54]	253	1			T3	1		T41	1		T13	1
valid_sources[0x55]	260	1			T1	1		T13	1		T45	1
valid_sources[0x56]	261	1			T1	1		T51	1		T45	1
valid_sources[0x57]	260	1			T3	1		T45	2		T53	1
valid_sources[0x58]	242	1			T14	1		T45	3		T64	1
valid_sources[0x59]	309	1			T9	4		T43	2		T45	2
valid_sources[0x5a]	287	1			T1	1		T10	1		T43	1
valid_sources[0x5b]	352	1			T9	1		T17	5		T27	2
valid_sources[0x5c]	345	1			T51	2		T45	2		T216	1
valid_sources[0x5d]	248	1			T43	1		T79	3		T53	1
valid_sources[0x5e]	214	1			T1	3		T42	1		T45	1
valid_sources[0x5f]	241	1			T3	1		T64	1		T53	2
valid_sources[0x60]	253	1			T41	4		T13	1		T45	1
valid_sources[0x61]	269	1			T14	2		T45	1		T64	1
valid_sources[0x62]	336	1			T51	2		T45	1		T54	4
valid_sources[0x63]	285	1			T1	1		T27	1		T54	1
valid_sources[0x64]	273	1			T43	1		T45	2		T76	1
valid_sources[0x65]	209	1			T1	2		T16	3		T14	2
valid_sources[0x66]	201	1			T3	1		T45	1		T76	4
valid_sources[0x67]	301	1			T1	2		T220	1		T176	2
valid_sources[0x68]	331	1			T1	3		T14	1		T45	2
valid_sources[0x69]	460	1			T78	1		T45	1		T17	195
valid_sources[0x6a]	346	1			T1	6		T14	2		T62	1
valid_sources[0x6b]	213	1			T1	3		T9	5		T45	2
valid_sources[0x6c]	471	1			T43	1		T53	2		T54	2
valid_sources[0x6d]	217	1			T1	1		T9	1		T14	2
valid_sources[0x6e]	212	1			T3	1		T6	1		T10	1
valid_sources[0x6f]	324	1			T1	4		T16	1		T53	2
valid_sources[0x70]	254	1			T1	4		T10	2		T41	1
valid_sources[0x71]	184	1			T41	3		T14	1		T45	1
valid_sources[0x72]	264	1			T2	1		T3	2		T16	1
valid_sources[0x73]	597	1			T14	1		T45	1		T76	9
valid_sources[0x74]	253	1			T10	1		T78	1		T45	1
valid_sources[0x75]	231	1			T45	2		T76	2		T216	3
valid_sources[0x76]	202	1			T10	2		T52	1		T54	4
valid_sources[0x77]	255	1			T1	3		T3	1		T4	1
valid_sources[0x78]	238	1			T10	6		T43	2		T45	2
valid_sources[0x79]	278	1			T1	2		T45	2		T76	1
valid_sources[0x7a]	279	1			T10	3		T45	4		T76	2
valid_sources[0x7b]	256	1			T1	1		T10	1		T45	2
valid_sources[0x7c]	365	1			T1	1		T2	1		T10	1
valid_sources[0x7d]	245	1			T10	1		T51	1		T45	1
valid_sources[0x7e]	289	1			T1	1		T10	3		T51	3
valid_sources[0x7f]	259	1			T42	1		T45	1		T217	2
valid_sources[0x80]	223	1			T3	1		T9	2		T15	19

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

14528

1

T1

106

T2

2

T3

16

values[0x0]

all_enables

biggest_size

8875

1

T1

8

T2

3

T3

2

values[0x1]

all_enables

biggest_size

6437

1

T1

6

T3

2

T7

1