Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	40868	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

31519

1

T1

17

T3

15

T5

14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36812	1			T1	43		T2	21		T3	13
values[0x0]	17809	1			T1	37		T3	32		T5	6
values[0x1]	17766	1			T1	26		T3	31		T4	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	32834	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

39553

1

T1

34

T2

6

T3

20

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	172	1			T10	1		T29	1		T91	2
valid_sources[0x01]	235	1			T43	3		T120	1		T29	3
valid_sources[0x02]	445	1			T15	6		T47	4		T85	2
valid_sources[0x03]	253	1			T1	2		T13	1		T210	2
valid_sources[0x04]	330	1			T210	1		T120	3		T29	4
valid_sources[0x05]	227	1			T1	1		T42	1		T43	3
valid_sources[0x06]	287	1			T210	2		T120	3		T85	1
valid_sources[0x07]	363	1			T3	5		T210	1		T33	63
valid_sources[0x08]	212	1			T42	1		T43	1		T210	1
valid_sources[0x09]	267	1			T3	2		T42	1		T43	1
valid_sources[0x0a]	266	1			T3	3		T120	2		T30	1
valid_sources[0x0b]	250	1			T210	1		T29	1		T37	1
valid_sources[0x0c]	420	1			T1	1		T13	1		T211	100
valid_sources[0x0d]	188	1			T210	1		T120	1		T36	1
valid_sources[0x0e]	281	1			T42	2		T120	1		T29	2
valid_sources[0x0f]	412	1			T210	2		T120	1		T29	1
valid_sources[0x10]	346	1			T210	1		T120	1		T41	1
valid_sources[0x11]	310	1			T29	2		T52	1		T84	2
valid_sources[0x12]	217	1			T1	2		T210	1		T120	1
valid_sources[0x13]	266	1			T43	1		T120	3		T29	1
valid_sources[0x14]	213	1			T42	1		T43	3		T52	2
valid_sources[0x15]	209	1			T120	1		T36	1		T37	4
valid_sources[0x16]	243	1			T3	2		T10	2		T42	1
valid_sources[0x17]	264	1			T1	1		T210	5		T29	1
valid_sources[0x18]	305	1			T3	2		T7	52		T13	1
valid_sources[0x19]	332	1			T39	1		T88	6		T48	1
valid_sources[0x1a]	281	1			T1	1		T10	3		T13	1
valid_sources[0x1b]	215	1			T1	1		T43	3		T36	1
valid_sources[0x1c]	466	1			T10	1		T210	1		T120	1
valid_sources[0x1d]	215	1			T10	1		T37	5		T212	1
valid_sources[0x1e]	278	1			T29	3		T52	3		T167	1
valid_sources[0x1f]	301	1			T210	2		T213	1		T214	1
valid_sources[0x20]	164	1			T120	1		T29	1		T85	2
valid_sources[0x21]	397	1			T1	1		T120	1		T29	4
valid_sources[0x22]	202	1			T1	1		T10	2		T120	2
valid_sources[0x23]	223	1			T210	1		T29	3		T85	1
valid_sources[0x24]	300	1			T1	2		T42	2		T120	1
valid_sources[0x25]	188	1			T1	1		T210	2		T120	3
valid_sources[0x26]	477	1			T15	14		T210	1		T120	2
valid_sources[0x27]	211	1			T1	2		T10	1		T21	1
valid_sources[0x28]	224	1			T39	1		T167	2		T215	4
valid_sources[0x29]	203	1			T1	1		T210	4		T36	1
valid_sources[0x2a]	224	1			T21	1		T15	13		T210	1
valid_sources[0x2b]	235	1			T1	1		T210	1		T29	1
valid_sources[0x2c]	316	1			T210	1		T120	4		T29	1
valid_sources[0x2d]	265	1			T29	3		T216	63		T213	1
valid_sources[0x2e]	337	1			T10	1		T32	1		T83	1
valid_sources[0x2f]	236	1			T210	1		T120	1		T29	1
valid_sources[0x30]	180	1			T43	1		T210	4		T85	1
valid_sources[0x31]	254	1			T15	13		T210	1		T29	2
valid_sources[0x32]	293	1			T1	1		T120	1		T36	1
valid_sources[0x33]	254	1			T210	1		T120	1		T37	16
valid_sources[0x34]	159	1			T1	1		T21	1		T43	3
valid_sources[0x35]	310	1			T43	1		T36	2		T41	1
valid_sources[0x36]	260	1			T3	1		T30	1		T87	5
valid_sources[0x37]	348	1			T210	3		T120	1		T52	1
valid_sources[0x38]	240	1			T210	2		T120	1		T29	2
valid_sources[0x39]	256	1			T1	1		T14	3		T43	2
valid_sources[0x3a]	208	1			T210	1		T29	1		T36	2
valid_sources[0x3b]	178	1			T120	1		T85	1		T39	1
valid_sources[0x3c]	299	1			T210	1		T86	13		T32	1
valid_sources[0x3d]	403	1			T120	1		T52	2		T164	2
valid_sources[0x3e]	234	1			T1	1		T210	2		T120	2
valid_sources[0x3f]	282	1			T2	21		T42	1		T29	1
valid_sources[0x40]	228	1			T1	1		T14	3		T21	2
valid_sources[0x41]	258	1			T210	2		T45	1		T120	2
valid_sources[0x42]	222	1			T1	1		T28	3		T210	1
valid_sources[0x43]	255	1			T210	1		T29	1		T82	1
valid_sources[0x44]	254	1			T43	1		T210	3		T29	1
valid_sources[0x45]	261	1			T37	2		T52	1		T91	1
valid_sources[0x46]	211	1			T21	1		T210	1		T120	1
valid_sources[0x47]	252	1			T1	1		T37	6		T82	1
valid_sources[0x48]	193	1			T10	2		T120	3		T29	1
valid_sources[0x49]	266	1			T210	1		T85	1		T36	2
valid_sources[0x4a]	291	1			T14	1		T210	3		T120	2
valid_sources[0x4b]	305	1			T1	1		T210	1		T29	2
valid_sources[0x4c]	298	1			T1	1		T80	35		T120	2
valid_sources[0x4d]	373	1			T1	1		T42	1		T210	2
valid_sources[0x4e]	210	1			T120	1		T167	1		T217	3
valid_sources[0x4f]	254	1			T210	2		T29	1		T37	2
valid_sources[0x50]	250	1			T1	1		T3	2		T51	2
valid_sources[0x51]	261	1			T1	1		T120	1		T31	3
valid_sources[0x52]	303	1			T1	1		T13	1		T21	1
valid_sources[0x53]	256	1			T10	3		T43	1		T22	1
valid_sources[0x54]	342	1			T1	1		T210	4		T52	2
valid_sources[0x55]	251	1			T1	1		T210	1		T120	1
valid_sources[0x56]	321	1			T210	1		T120	1		T52	3
valid_sources[0x57]	198	1			T210	1		T195	1		T137	1
valid_sources[0x58]	286	1			T1	1		T210	1		T29	2
valid_sources[0x59]	397	1			T42	1		T210	2		T120	3
valid_sources[0x5a]	249	1			T1	1		T42	1		T210	2
valid_sources[0x5b]	420	1			T3	2		T15	15		T120	1
valid_sources[0x5c]	205	1			T8	1		T29	3		T52	1
valid_sources[0x5d]	244	1			T15	15		T210	2		T120	1
valid_sources[0x5e]	241	1			T1	1		T120	1		T29	1
valid_sources[0x5f]	260	1			T1	2		T210	2		T120	2
valid_sources[0x60]	196	1			T210	1		T52	1		T218	3
valid_sources[0x61]	312	1			T28	3		T210	1		T120	1
valid_sources[0x62]	386	1			T1	1		T11	1		T210	1
valid_sources[0x63]	287	1			T42	1		T43	6		T15	13
valid_sources[0x64]	208	1			T210	2		T120	2		T47	1
valid_sources[0x65]	275	1			T1	1		T13	1		T43	2
valid_sources[0x66]	184	1			T1	1		T210	2		T29	4
valid_sources[0x67]	818	1			T21	2		T15	10		T120	2
valid_sources[0x68]	267	1			T210	2		T120	1		T16	11
valid_sources[0x69]	193	1			T13	1		T120	1		T47	4
valid_sources[0x6a]	401	1			T1	1		T13	1		T120	1
valid_sources[0x6b]	249	1			T1	1		T37	10		T52	1
valid_sources[0x6c]	399	1			T17	1		T210	2		T120	1
valid_sources[0x6d]	204	1			T28	2		T210	3		T30	1
valid_sources[0x6e]	305	1			T210	2		T52	1		T84	1
valid_sources[0x6f]	332	1			T36	1		T219	1		T137	1
valid_sources[0x70]	318	1			T1	1		T21	2		T29	2
valid_sources[0x71]	235	1			T10	1		T210	4		T29	1
valid_sources[0x72]	222	1			T21	2		T210	1		T39	1
valid_sources[0x73]	257	1			T21	2		T29	2		T85	1
valid_sources[0x74]	279	1			T1	1		T10	1		T42	1
valid_sources[0x75]	263	1			T120	1		T27	2		T83	2
valid_sources[0x76]	338	1			T3	8		T13	1		T210	1
valid_sources[0x77]	341	1			T52	3		T41	2		T220	1
valid_sources[0x78]	270	1			T1	1		T10	1		T42	1
valid_sources[0x79]	472	1			T14	1		T36	1		T167	1
valid_sources[0x7a]	225	1			T1	1		T43	4		T210	1
valid_sources[0x7b]	277	1			T4	1		T210	1		T120	1
valid_sources[0x7c]	202	1			T21	2		T210	1		T120	2
valid_sources[0x7d]	207	1			T10	1		T42	1		T210	2
valid_sources[0x7e]	346	1			T9	6		T85	1		T36	1
valid_sources[0x7f]	331	1			T3	10		T42	1		T29	3
valid_sources[0x80]	263	1			T1	1		T210	2		T120	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

15752

1

T1

3

T3

2

T5

9

values[0x0]

all_enables

biggest_size

9141

1

T1

8

T3

7

T5

2

values[0x1]

all_enables

biggest_size

6626

1

T1

6

T3

6

T5

3