SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 15 | 1 | T32 | 1 | T138 | 1 | T157 | 1 | ||||
others[1] | 20 | 1 | T40 | 3 | T136 | 1 | T138 | 1 | ||||
others[2] | 3 | 1 | T155 | 1 | T158 | 1 | T159 | 1 | ||||
others[3] | 15 | 1 | T135 | 1 | T137 | 1 | T160 | 1 | ||||
false | 120 | 1 | T30 | 2 | T31 | 1 | T32 | 4 | ||||
true | 2795 | 1 | T1 | 1 | T2 | 81 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 12 | 1 | T133 | 1 | T137 | 1 | T161 | 1 | ||||
others[1] | 9 | 1 | T162 | 1 | T157 | 1 | T163 | 1 | ||||
others[2] | 13 | 1 | T31 | 1 | T32 | 1 | T40 | 1 | ||||
others[3] | 14 | 1 | T30 | 1 | T40 | 1 | T135 | 1 | ||||
false | 172 | 1 | T30 | 4 | T31 | 4 | T32 | 2 | ||||
true | 2894 | 1 | T1 | 1 | T2 | 81 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 328 | 1 | T1 | 4 | T3 | 6 | T7 | 1 | ||||
others[1] | 321 | 1 | T1 | 4 | T3 | 4 | T7 | 1 | ||||
others[2] | 347 | 1 | T1 | 7 | T3 | 3 | T7 | 1 | ||||
others[3] | 605 | 1 | T1 | 11 | T3 | 11 | T43 | 9 | ||||
false | 3905 | 1 | T1 | 3 | T2 | 81 | T3 | 6 | ||||
true | 800 | 1 | T1 | 2 | T3 | 3 | T7 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |